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Amplifier fundamentals
Common-source amplifier
Common-source amplifier with current-source
supply
Reading Assignment:
Howe and Sodini; Chapter 8, Sections 8.1-8.4
Announcement:
Quiz #2: April 25, 7:30-9:30 PM at Walker. Calculator
Required. Open book.
Lecture 19
Amplifier Fundamentals
Intrinsic
Amplifier
V+
Load
Voltage Input
Supply
Current
ISUP
RS
vs
VBIAS +
vIN = VBIAS + vs
Current Input
is
iOUT = id
ISUP
RS
iIN = IBIAS + is
iD
Input
Active
Device
iD = f(input)
+
vOUT
RL
IBIAS
Lecture 19
2. Common-Source Amplifier:
Consider the following circuit:
V+=VDD
RD
iR
signal source
RS
iD
+
vOUT
vs
VBIAS
signal
load
RL
V-=VSS
Lecture 19
IR=ID
VDD-VSS
VVGG
-VSS
-VDD
- V=V
=V
SS- VSS
BIAS
ssDD
RD
VV
-V - Vss
GG
BIAS SS
-V
VVGG
-VSS
=V
BIAS
ssT= VT
0
VSS
VDD
VOUT
VSS
0
Want:
VT
VDD-VSS VGG-VSS
VBIAS - Vss
Lecture 19
ID =
W
2
nCox (VBIAS VSS VT )
2L
VDD VOUT
IR =
RD
If we select VOUT=0:
W
V DD
2
ID = IR =
C (V
VSS VT ) =
2 L n ox BIAS
RD
Then:
VBIAS =
2I D
W
n Cox
L
+ VSS + VT
Lecture 19
VDD
Signal swing:
RD
signal source
+
RS
vOUT
vs
VBIAS
VSS
vout,max = VDD
Downswing: limited by MOSFET leaving saturation.
2I D
W
n C ox
L
vout,min = VBIAS VT
Lecture 19
Rout
+
vs
vin
input
loading
Rin
Avovin
RL
vout
-
unloaded circuit
output
loading
vs
vin = Rin
Rin + Rs
Avo v in
vout = RL
Rout + RL
vout
RL
Rin
=
A
vo
Loaded voltage gain:
vs
Rin + RS
R L + Rout
Lecture 19
RD
+
vt
vgs
gmvgs
ro
vout
-
- S
vt
gmvt
(ro//RD) vout
vout = g mv t (ro // RD )
Then unloaded voltage gain:
v out
Avo =
= gm (ro // R D )
vt
6.012 Spring 2007
Lecture 19
Input Resistance
vt
-
vgs
gmvgs
(ro//RD)
RL
vt
it = 0 Rin = =
it
No effect of loading at input.
Lecture 19
Output Resistance
RS
vgs
gmvgs
(ro//RD)
vt
v gs = 0 gm v gs = 0 v t = it (ro // RD )
vt
Rout =
= ro // RD
it
Lecture 19
10
Rs
Rout
+
vs
vin
input
loading
Rin
Avovin
RL
vout
-
Intrinsic circuit
output
loading
v out
Rin
RL
=
Avo
vs
Rin + RS
RL + Rout
vout
RL
= g m(ro // RD )
= gm (ro // RD // RL )
vs
RL + ro // RD
Lecture 19
11
vSUP
1
roc
ISUP
iSUP
_
vSUP
vSUP
ISUP
roc
roc
large-signal model
small-signal model
Lecture 19
12
iSUP
signal source
iD
RS
+
vOUT
vs
VBIAS
signal
load
RL
VSS
Loadline View
iSUP=ID
load line
VBIAS-VSS=VDD-VSS
ISUP
VBIAS-VSS
VBIAS-VSS=VT
0
VSS
6.012 Spring 2007
VDD
VOUT
Lecture 19
13
VB
iSUP
signal source
iD
RS
vOUT
vs
VBIAS
VSS
W
2
I SUP = I Dp = p Cox VDD VB + VTp
2L p
W
2
I SUP = I Dn = nCox (VBIAS VSS VTn )
2L n
2I SUP
VBIAS =
+ VSS + VT
W
nC ox
L n
6.012 Spring 2007
Lecture 19
14
VDD
Signal swing:
VB
iSUP
signal source
iD
RS
vOUT
vs
VBIAS
VSS
vout,min = VBIAS VT
6.012 Spring 2007
Lecture 19
15
VB
iSUP
signal source
iD
RS
vOUT
vs
VBIAS
VSS
Lecture 19
16
W
nCox
L
1
L
ro
n I D I D
gm = 2I D
Then:
Circuit Parameters
|Avo|
Device*
Parameters gm(ro//roc)
ISUP
Rin Rout
ro//roc
Lecture 19
17
Bias Calculations
Signal Swing
Small Signal Circuit Parameters
Voltage Gain - AVO
Input Resistance - Rin
Output Resistance - Rout
Lecture 19
18