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Subrahmanya et al.
(54)
(56)
US 6,760,573 B2
Jul. 6, 2004
References Cited
(75)
Inventors: sparvathjnalfnljssulmhma? L.
unnyva 6
(
)>Jeremy
Sunnyva1e> CA(US)
'
"1
5,659,573 A *
6,389,060 B1 *
6,608,858 B1 *
CA US
(
(*)
Notice,
WO
WO
Wo0038343 A1 *
0229978 A2
6/2000
......... .. H04B/1/707
4/2002
* cited by examiner
(57)
ABSTRACT
(60)
(51)
(52)
(58)
2002.
RESET WEIGHTED
FREQUENCY SUM
21.5
SATUHATE RSSIG)
Em
SATU RATE freq_9st(j)
535
N
SATURATE WEIGHTED
WEIGHTED
FREQUENCY SUM +=
FREQUENCY SUM
m
RSSIU) '1req_es1(j)
5.40
L0 ADJUST ACCUMULATOR +=
WEIGHTED FREQUENCY SUM -
FILTER GAIN
{0
CONTROL LO
SATURATE LO ADJUST
WITH LO ADJUST _
ACCUMULATOR
ACCUM.
5m
{.65
U.S. Patent
Jul. 6, 2004
Sheet 1 0f 7
US 6,760,573 B2
M104b
FIG.1
04a
1
U.S. Patent
Jul. 6,2004
Sheet 2 6f7
US 6,760,573 B2
FINGER1
24QA
210
q?
II
DEMODULATOR
II
II
_>
RECEIVER
FINGER N
210m
SEARCHER
250
II
II
II
II
3Bii8p
OSCIZ-QTOR
PROCESSOR
260
II
MEMORY
m
II
__
TRANSMITTER
220
106 j
FIG. 2
U.S. Patent
Jul. 6, 2004
Sheet 3 0f 7
US 6,760,573 B2
310
Af
320
LOOP FILTER
M
G
31G
FILTER
QQQ
FIG. 3
FROM
RECEIVER
ROTATOR
PILOT ESTIMATION
?Q
2Q
II
INITIALIZE
VIA 260
240 j
INNER LOOP
CONTROL
iQQ
FIG. 4
U.S. Patent
Jul. 6, 2004
Sheet 4 0f 7
US 6,760,573 B2
LOAD LO ADJUST
@ ACCUMULATQR
QQQ
510
N
REsET WEIGHTED
FREQUENCY SUM
.5l5
j:
5A)
525
FINGER]
sATURATE Rss|(j)
lN LOCK?
sATURATE WEIGHTED
FREQUENCY SUM
WEIGHTED
FREQUENCY SUM +=
RSS'U) * freq_est(j)
55
510
L0 ADJUST ACCUMULATQR +=
WEIGHTED FREQUENCY SUM *
FILTER GAIN
'
5?
WFT|NJgEJ'-[%T
ACCUM.
51(2
sATURATE LO ADJUST
<-_
ACCUMULATOR
65
U.S. Patent
Jul. 6, 2004
Sheet 5 0f 7
US 6,760,573 B2
ASSIGN MID-RANGE
@ VALUE
TO LO ADJUST
ACCUMULATOR
I29
I
FREEZE OUTER LOOP
.QZQ
I
SEARCH OVER RANGE
OF FREQUENCY
HYPOTHESES
ESQ
640
ACQ. SUCCESS?
.63
I
UN-FREEZE OUTER
LOOP
5.6.0
I
TRACK USING
IN-LOCK FINGERS
51G
@
FIG. 6
U.S. Patent
Jul. 6, 2004
Sheet 6 0f 7
CALCULATE
freq_common
ASSIGN NEW
FINGER?
INITIALIZE FINGER
ROTATOR LOOP WITH
freq_common
ZQQ
FIG. 7
US 6,760,573 B2
U.S. Patent
Jul. 6, 2004
Sheet 7 0f 7
CALCULATE DRIFT
USING freq_common
AND SLEEP DURATION
I
ADJUST PN OFFSET TO
ACCOMMODATE DRIFT
I
RE-ACQ. WITH
UNADJUSTED ACCUM.
VALUES IN OUTER
FIG. 8
US 6,760,573 B2
US 6,760,573 B2
1
RELATED APPLICATIONS
SUMMARY
FIELD
20
30
station;
FIG. 4 depicts a portion of an eXemplary ?nger;
inner loops;
communication performance.
25
DETAILED DESCRIPTION
US 6,760,573 B2
3
15
other embodiments.
Each base station 104 and mobile station 106 is equipped
With a local timing reference used for modulation and
demodulation of transmitted and received signals. In the
40
outer loop.
In alternate embodiments, outer loop processor 260 may
be a Digital Signal Processor (DSP) or any general-purpose
lead to timing drift. KnoWn in the art are various methods for
45
or more received signals Will be referred to herein as an 55 hardWare, a general-purpose processor, or a combination of
outer loop.
FIG. 2 depicts an embodiment of a portion of an exem
the tWo. Those of skill in the art Will also readily partition the
tasks described herein betWeen tWo or more processors.
scenario.
US 6,760,573 B2
6
5
varying amplitudes and phase and timing offsets. This
ing techniques are knoWn in the art, and any technique can
be deployed for use in searcher 250. One example searching
technique, applicable to combined inner and outer loop time
tracking, as described herein, is disclosed in co-pending US.
15
track the signal at that offset, i.e., the ?nger is in lock, then
determined to exist.
The outputs of one or more ?ngers 240 are delivered to
35
change rapidly.
40
45
65
US 6,760,573 B2
7
15
25
35
55
inner loops. Thus, the outer and inner loops interrelate, and
US 6,760,573 B2
10
loops, to re-converge. Rapid shifts in Doppler of a moving
10
15
20
25
Once all the ?ngers have been tested, and the Weighted
frequency estimates of the in-lock ?ngers have been incor
porated into the overall Weighted frequency estimate
(Weightedifreqisum), proceed to step 555. In step 555 the
Weighted frequency sum is saturated. In the exemplary
embodiment, the Weighted frequency sum falls Within the
range [128,127]. The Weighted frequency sum is saturated
to prevent instability. The change from iteration to iteration
is kept sloW enough to alloW the inner loops to re-converge
in betWeen outer loop control changes. In the exemplary
embodiment, the outer loop is updated every 10 ms. By
contrast, the inner loops update every 512 chips, Which is on
the order of 100 microseconds. The rate of change is related
30
40
ment the saturated RSSI value falls Within the range [0,127].
Proceed to step 535 and saturate the frequency estimate of
55
60
?nger Would require all the inner loops, as Well as the outer
65
US 6,760,573 B2
11
12
Those of skill in the art Will understand that information
10
15
step 730, initialiZe the neW ?nger rotator loop With freqi
25
Wake up and determine as quickly as possible if it can return 35 the processor may be any conventional processor, controller,
to the sleep state. While the mobile station is sleeping, there
microcontroller, or state machine. A processor may also be
can be frequency drift betWeen the local timing references in
implemented as a combination of computing devices, e.g., a
the base station and the mobile station, since the frequency
combination of a DSP and a microprocessor, a plurality of
tracking loops are not operating. Note that, in steady state,
microprocessors, one or more microprocessors in conjunc
the local oscillator error is tuned out and freqicommon, or 40 tion With a DSP core, or any other such con?guration.
45
terminal.
65
US 6,760,573 B2
14
13
What is claimed is:
1. An apparatus comprising:
strength indicators;
generating a Weighted average of the plurality of fre
quency error estimates Weighted respectively by the
10
strength indicators;
limiting each component signal strength indicator to a
15
cators; and
generating a timing reference control signal in response
to the Weighted average.
2. The apparatus of claim 1, Wherein the outer loop
processor further limits the plurality of frequency error
strength indicators;
limiting each component signal strength indicator to a
parameter.
3. The apparatus of claim 1, further comprising a timing
reference, the frequency of the timing reference variable in
response to the timing reference control signal.
4. The apparatus of claim 3, Wherein the Weighted average
35
cators; and
generating a timing reference control signal in response
to the Weighted average.
15. A method of frequency tracking, operable With a
strength indicators;
cators; and
generating a timing reference control signal in response
to the Weighted average.
period; and
tors; and
generating a timing reference control signal in response to
the Weighted average frequency error.
16. The method of claim 15, further comprising generat
ing a timing reference With frequency variable in response to
65
US 6,760,573 B2
15
16
age.
error.
1O
error estimate.
inner loops;
a time period;
estimating frequency drift in response to the common
frequency error estimate and the time period; and
adjusting a PN sequence in response to the frequency drift
estimate.
indicators; and
25
folloWing steps:
inner loops;
inner loops;
folloWing steps:
receiving a signal strength indicator and a frequency error
estimate from each of the plurality of inner loops;
computing a Weighted average frequency error over the
indicators; and
means for generating a timing reference control signal in
response to the Weighted average frequency error.
26. The apparatus of claim 25, further comprising means
for limiting the Weighted average frequency error to a
maXimum frequency error parameter prior to generating the
45