Lesson 12

Sequential Circuits: Flip-Flops

1. Overview of a Synchronous Sequential Circuit
We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This
instability can be reduced by adding a control/enable signal throughout the system, with each latch only
permitted to switch states when enabled. This single enable signal, which periodically activates, thereby
enabling all of the devices at the same instant, ensuring that all state shifts are synchronized, is called a clock
signal.
A system of sequential elements that all change their states at the same time is termed synchronous systems. A
general block diagram of a synchronous sequential system is shown below.

From Mano and Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th edition

In a synchronous system, all memory elements (flip flops) can change state only once per periodic clock signal,
and no elements can alter their states between clock signals. Clock signals, such as those shown below, are
periodic signals characterized by two values.

From A. Marcovitz, Introduction to Logic Design, McGraw Hill, 2010

The period, T, which is the length of one cycle.

The frequency of the clock is defined as 1 .

The duty cycle, which is the percentage of the period that the clock signal is active (i.e., 1 for active high, 0 for
active low).
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The two signals above have the same period but different duty cycles.

Do you think that we want clocks to have a high frequency or a low frequency (or it doesnt matter)?
High frequency! All computer operations are based on state changes. State changes only occur once per
clock cycle. The more clock cycles per second, the more state changes per second, and the more a
computer can do per second.
As we saw from the previous lesson, the SR latch with an enable signal will respond to the input signals when
the enable single is active (level sensitive). The problem with this while the enable signal is active, the latch will
respond to new input values and a new output may occur. This leads to unpredictable situation since the state of
the latches may keep changing due to the different propagation delay of the input signals. The key to proper
operation in a sequential system is that all the elements should change state at the same time during the clock
signal transition. These transitions are known as clock edges. Example of the level response, positive edge (or
rising edge = 0 to 1 transition) response, and negative edge (or falling edge = 1 to 0 transition) response are
shown below.

From Mano and Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th edition

Memory elements that operate based on clock signal transitions are call edged-triggered flip-flops. In this
lesson, we will look at three types of flip flops:

D flip-flop
JK flip-flop
T flip-flop

2. D Flip Flop
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As mentioned in the previous lesson, the SR latches are rarely used in practical applications but they are the
building blocks for flip-flops. The construction of a D flip-flop based on two D latches is shown below.

From Mano and Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th edition

When the clock is 1, the output Y of the master latch is set to the correct value (based on the input value of D),
and this value is then passed to the output Q via the second latch, the slave, when the clock goes from 1 to 0.
This is termed a negative-edge triggered D flip-flop since the output of the device changes when the clock goes
from 1 to 0. Note that the change in the output of the flip-flop can only be triggered by and during the transition
of the clock (e.g. negative/falling edge in the above block diagram). For example, once the clock has
transitioned to the negative level, the master latch is disabled; hence the output Y of the master latch will remain
stable regardless of the input D. Therefore, the output Q of the flip-flop will also remain stable.
Notes:
There is a minimum time called the setup time during which the input D must stay constant right before
the clock edge.
There is also a minimum time called the hold time during which the input D must stay constant right
after the clock edge.
There is a propagation delay associated with a flip-flop which is defined as the time interval between
the active clock edge and the stabilization of the output.
All of these parameters are specified in the device datasheet produced by the manufacturers.
For timing analysis in this class, we will only consider the propagation delay.
Symbol
The logic symbols for positive-edge and negative-edge triggered D flip-flop are shown below.

From Mano and Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th edition

Characteristic Table
Characteristic tables are used to define the operations of the flip-flops. For a D flip-flop, we consider the input
D at time t = 0 and the output will be Q after the circuit delay (next state). We will denote the next state as
Q(t+1). Write the state table for the D flip-flop:

From Mano and Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th edition

So, in summary, what does the D flip flop do?

The input at D shows up as the output Q at the next active clock transition.
Put another way
The next state of the D flip flop is equal to the value of D before the clock transition.

Characteristic Equation
The function of a D flip-flop can also be described as
Q(t+1) = D
which states that next state of the output will be equal to the value of the input D after the clock transition.

Timing Diagram
Another way to illustrate the behavior of the D flip flop is to use a timing diagram.
The important point: evaluate the output of the each flip-flop based on the current input right before the active
clock edge (e.g. negative/falling edge).
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Example. Sketch the output Q of a negative-edge triggered D flip flop whose inputs are shown below.

Q
From A. Marcovitz, Introduction to Logic Design, McGraw Hill, 2010

Example. Sketch the output Q of a positive-edge triggered D flip flop whose inputs are shown below.

Q
From A. Marcovitz, Introduction to Logic Design, McGraw Hill, 2010

Example. Consider the circuit below. Sketch the behavior of the intermediate signal q and the value of the
output r for the input signal D shown below.

Q
R
From A. Marcovitz, Introduction to Logic Design, McGraw Hill, 2010

Preset and Clear Signals

Sometimes, a flip-flop has direct inputs that bring the flip-flop to a known starting state at initialization. These
direct inputs are force the output of the flip-flop to a known state independent of the clock signal. These direct
inputs are called Clear (CLR) and Preset (PRE) signals.
A symbol of a D flip flop with active-low CLR and PRE inputs is shown below.

PRE
D

Q
CLK
Q
CLR

These two new inputs work as follows:

The CLR and PRE inputs affect the flip flop immediately, overriding the clock input.
When the CLR signal is active (i.e., CLR = 0), the output of the flip flop is forced to 0 immediately
When the PRE input is active (PRE = 0), the output of the flip flop is forced to 1 immediately.
When would the D flip flop operate as described before?
When CLR = 1 and PRE = 1.
Can you see a situation that is not permitted?
CLR = 0 and PRE = 0 (both can NOT be active at the same time).
Example. Sketch the output Q of a negative-edge triggered D flip flop whose inputs are shown below.

CLR
PRE

From A. Marcovitz, Introduction to Logic Design, McGraw Hill, 2010

3. JK Flip Flop
Another type of flip-flop is JK flip-flop which is built based on a D flip-flop. The circuit diagram and symbol of
a JK flip-flop is shown below.

From Mano and Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th edition

A symbol of a JK flip flop with active-low CLR and PRE inputs is shown below.
PRE
J

Q
CLK

Q
CLR

Characteristic Table
Lets explore the operation of this flip flop by building the state table.
Suppose Q is 0 (and Q is 1), J is 0, and K is 0. What
will be the next state Q(t+1)?

D is 0. So, Q(t+1)=0

Suppose Q is 1 (and Q is 0), J is 0, and K is 0. What

will be the next state Q(t+1)?

D is 1. So, Q(t+1)=1.

Bottom line: When J and K are both 0, the J-K flip flop
holds its current output.
Suppose Q is 0 (and Q is 1), J is 0, and K is 1. What
will be the next state Q(t+1)?

D is 0. So, Q(t+1)=0.
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Suppose Q is 1 (and Q is 0), J is 0, and K is 1. What

will be the next state Q(t+1)?

D is 0. So, Q(t+1) = 0.

Bottom line: When J = 0 and K = 1, the J-K flip flop

resets to Q(t+1)=0.
Suppose Q is 0 (and Q is 1), J is 1, and K is 0. What
will be the next state Q(t+1)?

D is 1. So, Q(t+1) = 1.

Suppose Q is 1 (and Q is 0), J is 1, and K is 0. What

will be the next state Q(t+1)?

D is 1. So, Q(t+1) = 1

Bottom line: When J = 1 and K = 0, the J-K flip flop

sets to Q(t+1) = 1.
Suppose Q is 0 (and Q is 1), J is 1, and K is 1. What
will be the next state Q(t+1)?

D is 1. So, Q(t+1) = 1.

Suppose Q is 1 (and Q is 0), J is 1, and K is 1. What

will be the next state Q(t+1)?

D is 0. So, Q(t+1) = 0.

Bottom line: When J = 1 and K = 1, the J-K flip flop

Toggles! It will complement its output!

The characteristic table for the J-K flip flop is presented below

From Mano and Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th edition

Characteristic Equation
The characteristic equation for a JK flip-flop is determined based on the current state of the flip-flop and inputs
J and K. The characteristic table for the a JK flip-flop can be rewritten as
8

Q(t+1)

We can then derive the characteristic equation of a JK flip-flop using a 3-variable K-map.
JK
Q

00

01

11

10

0
1

Q(t+1) = JQ + KQ

Timing Diagram
The behavior of a JK flip-flop can be illustrated with a timing diagram.
Example: Show the output of the J-K flip flop whose input is shown below (assume negative-edge triggered
with active-low CLR signal).

CLR

Q
From A. Marcovitz, Introduction to Logic Design, McGraw Hill, 2010

Example: How would the example above change if we also had an active-low preset signal shown below.

CLR

PRE

From A. Marcovitz, Introduction to Logic Design, McGraw Hill, 2010

4. T Flip Flop
The last type of flip-flop is the T(toggle) flip-flop which is a complementing flip-flop. The T flip-flop can be
obtained from a JK flip-flop (J and K inputs tied together) or a D flip-flop (with a XOR gate) as shown below.

From Mano and Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th edition

A symbol of a JK flip flop with active-low CLR and PRE inputs is shown below.
PRE
T

Q
CLK
Q
CLR

10

Characteristic Table
Explain the operation of this flip flop.
When T = 0, the flip flop holds its state.
When T = 1, the flip flop toggles
The characteristic table for the J-K flip flop is presented below.

From Mano and Ciletti, Digital Design: With an Introduction to the Verilog HDL, 5th edition

Characteristic Equation
The characteristic equation for a T flip-flop is determined based on the current state of the flip-flop and input T.
The characteristic equation for a T flip-flop is
Q(t+1) = T Q(t)
Timing Diagram
The behavior of a T flip-flop can be illustrated with a timing diagram.
Example: Show the output of the T flip flop whose input is shown below (assume negative-edge triggered with
active-low CLR signal).

CLR

Q
From A. Marcovitz, Introduction to Logic Design, McGraw Hill, 2010

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