#include<lpc21xx.

h>
unsigned char spi_rec;
//void
//void
//char
//void
//void

spi_ini();
spi_tr1(unsigned int x);
spi_re();
spi_tr(unsigned char cmd,unsigned char data);
spi_str(unsigned char *str);

unsigned int ar[10]={ 0x7e,0x60,0x6d,0x79,0x33,0x5b,0x5f,0x70,0x7f,0x7b };

unsigned int ar1[8]={0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08};
//void pll();
void delay_ms(unsigned int x);
void pll()
{
/*PLL IS CONFIGURED TO GET 60HZ pCLK*/
PLLCFG=0X24;
// SET PSEL=2 AND MSEL=5
PLLCON=0X01;
//PLL IS ACTIVE BUT NOT YET CON
NECT
PLLFEED=0XAA;
//FEED SEQUENCE
PLLFEED=0X55;
//FEED SEQUENCE
while((PLLSTAT & 0X400)==0); //WAIT FOR FEED SEQUENCE
TO BE INSERTED
PLLCON=0X03;

// PLL HAS BEEN ACTIVE AND BEING

VPBDIV=0X01;
PLLFEED=0XAA;
PLLFEED=0X55;

// SET PCLK SAME AS FCCLK

//FEED SEQUENCE
//FEED SEQUENCE

CONNECTRD

}
void spi_ini()
{
PINSEL0 |=0x1500;
/* P0.4, P0.5, P0.6, P0.7 are set as
SCK, MISO, MOSI and GPIO */
//IODIR0 |= 0X80;
/* SSEL is out
put */
//IOSET0 |=0X80;
/* set SSEL to
high */
S0SPCCR=8;
/*
SPI clock prescale register minimum value is 8. */
S0SPCR=0x0030;
/* Device se
lect as master, Set data to 8-bit, CPOL = 0, CPHA = 0*/
}
void spi_tr1(unsigned int x)
{
S0SPDR =x;
while ( !(S0SPSR & 0x80) );
icate trabsfer complete */
}

/* Wait until the SPIF bit is set to ind

char spi_re()
{
while ( !(S0SPSR & 0x80) ); /* Wait until the SPIF bit is set to ind

icate trabsfer complete */

spi_rec= S0SPDR;
return spi_rec;
}
void spi_str(unsigned char *str)
{
while(*str!='\0')
{
spi_tr1(*str);
str++;
}
}
void spi_tr(unsigned char cmd,unsigned char data)
{
IO0CLR=(1<<7); //enable transmission
spi_tr1(cmd);
spi_tr1(data);
IO0SET=(1<<7); // disable transmission
}
void delay_ms(unsigned int x)
{
int i;
while(x--)
{
for(i=0;i<100;i++);
}
}
int main()
{

//

int i,a,b,c,d,e,f,g,h;
a=b=c=d=e=f=g=h=0;
PINSEL0=0X00000000;
IO0DIR=0XFFFFFFFF;
pll();
spi_ini();
spi_tr(0x0a,0xf);
spi_tr(0x0b,0xf);
//for(i=0;i<9;i++)

//{
spi_tr(0x01,0x7e);
spi_tr(0x02,0x7e);
spi_tr(0x03,0x7e);
spi_tr(0x04,0x7e);
spi_tr(0x05,0x7e);
spi_tr(0x06,0x7e);
spi_tr(0x07,0x7e);
spi_tr(0x08,0x7e);

delay_ms(1000);
delay_ms(1000);
delay_ms(1000);
delay_ms(1000);
delay_ms(1000);
delay_ms(1000);
delay_ms(1000);
delay_ms(1000);

delay_ms(1000);
spi_tr(0x0c,0x01);
while(1)
{//
spi_tr(0x0a,0xf);
//spi_tr(0x0b,0xf);

// delay_ms(1000);
spi_tr(0x08,ar[a]);
// delay_ms(1000);
spi_tr(0x07,ar[b]);
// delay_ms(1000);
spi_tr(0x06,ar[c]);
// delay_ms(1000);
spi_tr(0x05,ar[d]);
// delay_ms(1000);
spi_tr(0x04,ar[e]);
// delay_ms(1000);
spi_tr(0x03,ar[f]);
// delay_ms(1000);
spi_tr(0x02,ar[g]);
// delay_ms(1000);
spi_tr(0x01,ar[h]);
// delay_ms(1000);
a++;delay_ms(1000);
//spi_tr(0x0c,0x01);
// delay_ms(1000);
if(a==10)
{
a=0;
b++;delay_ms(1000);
}
if(b==10)
{
a=b=0;
c++;delay_ms(1000);
}
if(c==10)
{
a=b=c=0;
d++;delay_ms(1000);
}
if(d==10)
{
a=b=c=d=0;
e++;delay_ms(1000);
}
if(e==10)
{
a=b=c=d=e=0;
f++;delay_ms(1000);
}
if(f==10)
{
a=b=c=d=e=f=0;
g++;delay_ms(1000);
}
if(g==10)
{
a=b=c=d=e=f=g=0;
h++;delay_ms(1000);
}
if(h==10)
{
a=b=c=d=e=f=g=h=0;delay_ms(1000);
}
delay_ms(3000);

}
}