ESc201A:IntroductiontoElectronics

Sequential Circuit Design -1

1
Flip Flop / Latch

Dr. M. J. Akhtar
Dept. of Electrical Engineering
IIT Kanpur
15/04/2015

SR Latch

clk
Q

Positive edge triggered flipflop

D

clk

Negative edge triggered flipflop

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State

SET

RESET

HOLD

INVALID

JK Flip-flop
JK flip flop is
refinement of RS flip
flop where
i d t
indeterminate
i t state
t t off
RS flip flop is defined.

Q
0
0
0
0
1
1
1
1

J
0
0
1
1
0
0
1
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1

K
0
1
0
1
0
1
0
1

Q(t+1)
0
0
1
1
1
0
1
0

Q(t 1) JQ (t ) K Q(t )
JK

00

01

11

10

Q(t)

Toggle or T Flip-flop

Q
0
0
1
1

T
0
1
0
1

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Q(t+1)
0
1
1
0

Q(t 1) T Q(t )

Characteristic table
Given a input and the present state of the flip-flop, what is the next state of
the flip-flop

D Flip-flop
D

Inputs (D)

clk

Q(t+1)

Characteristic equation:

Q(t 1) D

JK Flip-flop
Inputs J

clk
K

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Characteristic equation:

K Q(t+1)

Q(t)

Q(t)

Q(t 1) JQ (t ) K Q(t )
5

Toggle or T Flip-flop
Inputs (T)

clk

Q(t+1)

Q(t)

Q(t)

Characteristic equation:

Q(t 1) T Q(t )

Excitation Table
What inputs are required to effect a particular state change
Excitation Table

Q
T
0
0
0
1
1
0
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Q(t+1)
0
1
1
0

Q(t)

Q(t+1)

Inputs

0
6

Excitation Table
J

clk
K

Inputs
J

Q( )
Q(t+1)

Q(t)

Q(t)

Characteristic Table

Q(t+1)

Q(t)

Excitation Table

Q(t+1)

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Excitation Table
D

clk

Q(t+1)

Characteristic Table

Q
0
0
1
1

D
0
1
0
1

Q(t+1)
( )
0
1
0
1

Inputs
Q(t)
()

( )
Q(t+1)

Excitation Table
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Convert a D FF to JK FF
J
D

CC

clk
lk

Q Q(t+1) D

Inputs

Inputs
Q(t 1)
Q(t+1)

Q(t)

Q(t)

15/04/2015 Excitation

Q(t+1)

Table

Excitation Table

Convert a D FF to JK FF

J
D

CC

clk
lk

Q Q(t+1) D

1
1

1
1

D Q.J Q.K
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Convert a D FF to JK FF

D Q.J Q.K

Inputs J

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K Q(t+1)

Q(t)

Q(t)

Q(t+1)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

11

Sequential Circuits
The binary information stored in the storage elements at any
given time defines the state of the sequential circuit at that time
X

CC

St
Storage
elements

Output is a function of input as well as the present state of the

storage elements.

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Synchronous Sequential Circuits

SynchronousSequentialCircuits
Combinational
C
bi ti
l
Circuit

Input

Output

Flipflops
Clock

Employs signals that affect the storage elements only at

discrete instants of time.
Synchronization is achieved via the clock pulses.

SynchronousClockedSequentialCircuits

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13

Analysis
Next state Logic

Output Logic

A
x

B
A
x

B
x

clk
lk

memory
Output z depends on the input x and on the state of the memory (A,B)
The memory has 2 FFs and each FF can be in state 0 or 1. Thus there
are four possible states: AB: 00,01,10,11.
To describe the behavior of a sequential circuit, we need to show
1 How the system goes from one memory state to the next as the input
1.
changes
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2. How the output responds to input in each state