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PD-95020A

IRFR9120NPbF
IRFU9120NPbF
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Ultra Low On-Resistance


P-Channel
Surface Mount (IRFR9120N)
Straight Lead (IRFU9120N)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
Lead-Free

HEXFET Power MOSFET


D

VDSS = -100V
RDS(on) = 0.48

ID = -6.6A

Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.

D-Pak
TO-252AA

I-Pak
TO-251AA

Absolute Maximum Ratings


ID @ TC = 25C
ID @ TC = 100C
IDM
PD @TC = 25C
V GS
EAS
IAR
EAR
dv/dt
TJ
TSTG

Parameter

Max.

Continuous Drain Current, VGS @ -10V


Continuous Drain Current, VGS @ -10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds

-6.6
-4.2
-26
40
0.32
20
100
-6.6
4.0
-5.0
-55 to + 150

Units
A
W
W/C
V
mJ
A
mJ
V/ns

300 (1.6mm from case )

Thermal Resistance
Parameter
RJC
RJA
RJA

www.irf.com

Junction-to-Case
Junction-to-Ambient (PCB mount)**
Junction-to-Ambient

Typ.

Max.

Units

3.1
50
110

C/W

1
12/14/04

IRFR/U9120NPbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance

Qg
Qgs
Qgd
td(on)
tr
td(off)
tf

Gate-to-Source Forward Leakage


Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time

Min.
-100

-2.0
1.4

Typ.

-0.11

14
47
28
31

LD

Internal Drain Inductance

4.5

LS

Internal Source Inductance

7.5

Ciss
Coss
Crss

Input Capacitance
Output Capacitance
Reverse Transfer Capacitance

350
110
70

V(BR)DSS

IDSS
IGSS

Drain-to-Source Leakage Current

Max. Units
Conditions

V
VGS = 0V, ID = -250A
V/C Reference to 25C, ID = -1mA
0.48

VGS = -10V, I D = -3.9A


-4.0
V
VDS = VGS, ID = -250A

S
VDS = -50V, ID = -4.0A
-25
VDS = -100V, VGS = 0V
A
-250
VDS = -80V, VGS = 0V, TJ = 150C
100
VGS = 20V
nA
-100
VGS = -20V
27
ID = -4.0A
5.0
nC VDS = -80V
15
VGS = -10V, See Fig. 6 and 13

VDD = -50V

ID = -4.0A
ns

RG = 12

RD =12 , See Fig. 10


D
Between lead,

6mm (0.25in.)
nH
G
from package

and center of die contact


S

VGS = 0V

pF
VDS = -25V

= 1.0MHz, See Fig. 5

Source-Drain Ratings and Characteristics


IS
ISM

V SD
t rr
Qrr
ton

Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time

Notes:

Repetitive rating; pulse width limited by

max. junction temperature. ( See fig. 11 )


Starting TJ = 25C, L = 13mH
RG = 25, IAS = -3.9A. (See Figure 12)
ISD -4.0A, di/dt 300A/s, VDD V(BR)DSS,
TJ 150C

Min. Typ. Max. Units

Conditions
D
MOSFET symbol
-6.6
showing the
A
G
integral reverse
-26
p-n junction diode.
S
-1.6
V
TJ = 25C, IS = -3.9A, VGS = 0V
100 150
ns
TJ = 25C, IF = -4.0A
420 630
nC di/dt = 100A/s
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Pulse width 300s; duty cycle 2%.


This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact

Uses IRF9520N data and test conditions.

** When mounted on 1" square PCB (FR-4 or G-10 Material ) .


For recommended footprint and soldering techniques refer to application note #AN-994

IRFR/U9120NPbF
100

100

VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V

VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
TOP

-I D , Drain-to-Source Current (A)

-I D , Drain-to-Source Current (A)

TOP

10

-4.5V
20s PULSE WIDTH
TJ = 25 C

0.1
0.1

10

100

10

-4.5V

0.1
0.1

2.5

R DS(on) , Drain-to-Source On Resistance


(Normalized)

-I D , Drain-to-Source Current (A)

100

TJ = 25 C
TJ = 150 C

V DS = -50V
20s PULSE WIDTH
4

-VGS , Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

10

100

Fig 2. Typical Output Characteristics

Fig 1. Typical Output Characteristics

0.1

-VDS , Drain-to-Source Voltage (V)

-VDS , Drain-to-Source Voltage (V)

10

20s PULSE WIDTH


TJ = 150 C

10

ID = -6.7A

2.0

1.5

1.0

0.5

0.0
-60 -40 -20

V GS = -10V
0

20

40

60

80 100 120 140 160

TJ , Junction Temperature ( C)

Fig 4. Normalized On-Resistance


Vs. Temperature

IRFR/U9120NPbF
20

0V,
f = 1MHz
Cgs + Cgd , Cds SHORTED
Cgd
Cds + Cgd

-VGS , Gate-to-Source Voltage (V)

VGS =
Ciss =
Crss =
Coss =

600

Ciss

Coss

400

Crss
200

ID = -4.0 A

VDS =-80V
VDS =-50V
VDS =-20V

16

12

FOR TEST CIRCUIT


SEE FIGURE 13

10

100

10

15

20

25

QG , Total Gate Charge (nC)

-VDS , Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs.


Drain-to-Source Voltage

Fig 6. Typical Gate Charge Vs.


Gate-to-Source Voltage

100

100

OPERATION IN THIS AREA LIMITED


BY RDS(on)
10us

10

-IID , Drain Current (A)

-ISD , Reverse Drain Current (A)

C, Capacitance (pF)

800

TJ = 150 C
TJ = 25 C

0.1
0.2

V GS = 0 V
0.8

1.4

2.0

-VSD ,Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode


Forward Voltage

10
100us

1ms
1
10ms

TC = 25 C
TJ = 150 C
Single Pulse

0.1

2.6

10

100

-VDS , Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

1000

IRFR/U9120NPbF
8.0

VGS

-ID , Drain Current (A)

RD

VDS

D.U.T.

RG

6.0

VDD

-10V
Pulse Width 1 s
Duty Factor 0.1 %

4.0

Fig 10a. Switching Time Test Circuit


2.0
td(on)

tr

t d(off)

tf

VGS
10%

0.0

25

50

75

100

125

150

TC , Case Temperature ( C)
90%
VDS

Fig 9. Maximum Drain Current Vs.


Case Temperature

Fig 10b. Switching Time Waveforms

Thermal Response (Z thJC )

10

D = 0.50
1
0.20
0.10
0.05
0.1

0.01
0.00001

0.02
0.01

P DM

SINGLE PULSE
(THERMAL RESPONSE)

t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC

0.0001

0.001

0.01

0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

10

IRFR/U9120NPbF
L

VDS

- V
V DD
+ DD

D.U.T

RG

IAS
-20V

tp

DRIVER
0.01

15V

Fig 12a. Unclamped Inductive Test Circuit


I AS

EAS , Single Pulse Avalanche Energy (mJ)

250

TOP
200

BOTTOM

ID
-1.7A
-2.5A
-3.9A

150

100

50

0
25

50

75

100

125

150

Starting TJ , Junction Temperature ( C)

Fig 12c. Maximum Avalanche Energy


Vs. Drain Current

tp
V(BR)DSS

Fig 12b. Unclamped Inductive Waveforms


Current Regulator
Same Type as D.U.T.

50K

QG

12V

-10V

.2F
.3F

QGS

QGD

D.U.T.

+VDS

VGS

VG

-3mA

Charge

Fig 13a. Basic Gate Charge Waveform

IG

ID

Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit

IRFR/U9120NPbF
Peak Diode Recovery dv/dt Test Circuit
+

D.U.T*

Circuit Layout Considerations


Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer

RG

dv/dt controlled by RG
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test

VGS

+
-

VDD

Reverse Polarity of D.U.T for P-Channel

Driver Gate Drive


P.W.

Period

D=

P.W.
Period

[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current

Body Diode Forward


Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt

Re-Applied
Voltage

Body Diode

[VDD]

Forward Drop

Inductor Curent
Ripple 5%

*** VGS = 5.0V for Logic Level and 3V Drive Devices


Fig 14. For P-Channel HEXFETS

[ISD ]

IRFR/U9120NPbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information


EXAMPLE: THIS IS AN IRFR120
WITH ASSEMBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"

PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO

Note: "P" in assembly line position


indicates "Lead-Free"

IRFU120
12

916A
34

ASSEMBLY
LOT CODE

DATE CODE
YEAR 9 = 1999
WEEK 16
LINE A

OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO

IRFU120
12

ASSEMBLY
LOT CODE

34

DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WEEK 16
A = ASSEMBLY SITE CODE

IRFR/U9120NPbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information


EXAMPLE: T HIS IS AN IRF U120
WIT H AS SEMBLY
LOT CODE 5678
ASS EMB LED ON WW 19, 1999
IN T HE AS S EMBLY LINE "A"

INT ERNAT IONAL


RECT IF IER
LOGO

PART NUMBER
IRF U120
919A
56
78

AS SEMBLY
LOT CODE

Note: "P" in assembly line


position indicates "Lead-F ree"

DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A

OR
INT ERNAT IONAL
RECT IFIER
LOGO

PART NUMBER
IRF U120
56

ASS EMB LY
LOT CODE

78

DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 19
A = AS SEMB LY S IT E CODE

IRFR/U9120NPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR

TRR

16.3 ( .641 )
15.7 ( .619 )

12.1 ( .476 )
11.9 ( .469 )

FEED DIRECTION

TRL

16.3 ( .641 )
15.7 ( .619 )

8.1 ( .318 )
7.9 ( .312 )

FEED DIRECTION

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Data and specifications subject to change without notice.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04

Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/

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