Simulating a VHDL MIG DDR2

Controller with ModelSIM SE

February 7, 2008
Version 9.2

Overview
ModelSIM SE is a multi-language simulator available from Mentor Graphics
(www.modelsim.com). This is the simulator supported with MIG VHDL designs. A
multi-language simulator is required since the DDR2 model from Micron is Verilog
while the controller is VHDL.
MIG generates sim.exe and sim.do files to automate simulation within ModelSIM. For
instructions on running in batch mode or from the ModelSIM GUI, read the
simulation_help.chm file in the ./sim directory.
A few steps are required in setting up ModelSIM and getting the simulation to run from
ISE Project Navigator. Therefore, this tutorial demonstrates how to get a MIG DDR2
VHDL simulation working with ModelSIM SE in Project Navigator.

Objectives
Set up ModelSIM SE to simulate Xilinx designs. Add simulation files and settings to
Project Navigator. Simulate a MIG DDR2 VHDL controller from Project Navigator.

Experiment Setup
Software
The software used to test this reference design is:
WindowsXP 32-bit
Xilinx ISE 9.2i with Service Pack 41
ModelSIM SE 6.3c
o This experiment assumes that ModelSIM SE is installed and licensed. If
you need help with this, please contact your local Mentor distributor
(http://www.mentor.com/company/worldwide_distributors/index.cfm).

Hardware
The hardware setup used by this reference design includes:
Computer with a minimum of 950 MB to complete an XC3SD1800A design2
The Xilinx Spartan-3A DSP 1800A Starter Platform is the target hardware although the
hardware itself is not used in this tutorial.

1
2

All Service Packs are available at www.xilinx.com/download

Refer to www.xilinx.com/ise/products/memory.htm

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Experiments
Experiment 1: Generate the MIG Controller
The first step is to generate the MIG controller. This step is not covered in detail in this
tutorial. Refer to Labs 1 and 2 of the Avnet Practical Guide to DDR2 Design with
Spartan-3A DSP Speedway for detailed information.
The parameters to use are identical to those of the referenced Lab 1, including:
XC3SD1800A-4FG676
VHDL
32Mx32 interface
Micron MT47H32M16
125 MHz system clock
Bank 3 for address, control, and data
Bank 0 for clock
The steps covered in Labs 1 and 2 are:
Generate the controller
Use the create_ise.bat script to create a ProjNav project for the example_design
Create an ISE launch file that includes the environment variable
XIL_ROUTE_ENABLE_DATA_CAPTURE
Launch the example_design project in ProjNav
Update the design UCF and clocking structure to match the Spartan-3A DSP
1800A Starter board.
These steps have already been completed, so the design can simply be launched.
1. Browse to the .\Xil3SD1800A_MIG_sim_VHDL_v92\par directory and
double-click the ddr2_speedway.bat batch file.
2. In Project Navigator, select the device xc3sd1800a-4fg676.

3. Right-click and select Properties. Change the Simulator to Modelsim-SE Mixed

and the Preferred Language to VHDL. Click OK.

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Experiment 2: Compile and map Xilinx simulation libraries

If you are not familiar with simulation in the Xilinx environment, the following materials
are recommended for reading:

Synthesis and Simulation Design Guide

o Simulating Your Design Chapter
o %XILINX%\doc\usenglish\books\docs\sim\sim.pdf
Development System Reference Guide
o COMPXLIB Chapter
o %XILINX%\doc\usenglish\books\docs\dev\dev.pdf
Compiling HDL Simulation Libraries [Project Navigator]
o

http://toolbox.xilinx.com/docsan/xilinx9/help/iseguide/iseguide.htm#mergedProj
ects/dkxilinx/html/pp_process_compile_hdl_simulation_libraries.htm

Skip to Experiment 3 if you have previously compiled the Xilinx simulation libraries for
ModelSIM SE.
4. Browse to the installation directory for ModelSIM. Back-up the modelsim.ini
file. Modify the properties for modelsim.ini to turn off the Read-Only attribute.
5. In Project Navigator, select the device xc3sd1800a-4fg676.
6. Expand the Design Utilities option in the Process window. Right-click on
Compile HDL Simulation Libraries and select Properties.
7. Change the property for Language to All. Check each box for UNISIM,
SIMPRIM, and XilinxCoreLib. Modify the Compiled Library Directory if
desired. Click OK.

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8. Double-click Compile HDL Simulation Libraries

When finished, the Xilinx libraries for Spartan-3A DSP are compiled and the
modelsim.ini is updated with the following entries:
UNISIMS_VER = C:\Xilinx92\verilog\mti_se\unisims_ver
SIMPRIMS_VER = C:\Xilinx92\verilog\mti_se\simprims_ver
XILINXCORELIB_VER = C:\Xilinx92\verilog\mti_se\XilinxCoreLib_ver
UNISIM = C:\Xilinx92\vhdl\mti_se\unisim
SIMPRIM = C:\Xilinx92\vhdl\mti_se\simprim
XILINXCORELIB = C:\Xilinx92\vhdl\mti_se\XilinxCoreLib

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Experiment 3: Add and Modify Files

The simulation testbench and .do file are not automatically imported to Project Navigator
when the MIG create_ise.bat script is run. This has been done manually. The steps have
already been completed. If youd like to understand how to do this, continue reading. If
not, skip to Experiment 4.
9. In the Processes window, double-click Add Existing Source.
10. Browse to the ./sim directory and select the ddr2_model.v and sim_tb_top.vhd
files. Click Open.

11. In the Adding Source Files... dialog box, change the Association for ddr2_model
to Simulation Only. Click OK.

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The Sources view has changed to the Behavioral Simulation context, showing sim_tb_top
as the top-level.

12. With sim_tb_top selected in the Sources window, expand ModelSim Simulator in
the Processes window. Right-click and select Properties for Simulate Behavioral
Model.

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13. Check the Use Custom Do File box. Browse and set the Custom Do File to
../sim/sim.do. Uncheck the Use Automatic Do File check box. Click OK.

14. Edit sim_tb_top.vhd. The default DDR2 design was changed from a differential
system clock to match the 1800A board, which has a single-ended clock. The
testbench must be changed to match. Comment out sys_clkb in the port definition
in the component declaration and in the instantiation of the controller
(DDR2_32Mx32 in this design).
Comment out the signal declarations and
assignments for sys_clk_n and sys_clk_p. Replace four other references to
sys_clk_p with sys_clk.
15. Edit ddr2_32Mx32_infrastructure_top.vhd. Around line 129, change
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if( counter200 < 33400) then
to
--if( counter200 < 33400) then
if( counter200 < 0) then
This prevents the simulation from waiting the full 200 us.
implement this design in hardware, change this back.

When ready to

16. The ddr2_model references a parameters file. Project Navigator must be aware of
the full path to this parameters file. Edit ddr2_model.v. Around line 132, change
`include "ddr2_model_parameters.vh"
to
`include "../sim/ddr2_model_parameters.vh"
17. The sim.do file references the DDR2 model. This must be changed to provide the
full path to the model. Edit sim.do. Around line 37, change
vlog

+incdir+. +define+x512Mb +define+sg5E +define+x16 ddr2_model.v

to
vlog

+incdir+. +define+x512Mb +define+sg5E +define+x16 ../sim/ddr2_model.v

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Experiment 4: Simulate
18. Double-click process Simulate Behavioral Model. Project Navigator launches
ModelSIM. The HDL files are compiled and the simulation runs as specified by
the sim.do file. As explained in the simulation_help.chm document,
Run time depends on completion of calibration or memory
initialization. After completion of calibration/initialization,
simulation is run for 50us more.
For example, if it takes 212us for the calibration to complete then
the total run time will be 212 + 50 = 262us.User may still increase or
decrease the run time. Please refer Changing simulation Run Time
section to know how to do this.
19. Once the simulation has run for 50 us beyond initialization completion, the
ModelSIM Transcript window displays # TEST PASSED. A dialog window
pops open asking if you want to click. Since selecting Yes will close ModelSim,
Click No.

20. The simulation then continues to run. Select Simulate Break to stop the
simulation Now select the Zoom Full icon
DDR2 transactions being simulated.

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. This view now shows many

Simulating a VHDL MIG DDR2 Controller with

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In the screenshot below, several points are highlighted that demonstrates what happens
with the default example_design. The example logic loops through a Write-ReadCompare Data sequence over and over again. In this screenshot from ModelSim, these
stages are clearly visible.
Note that each stage is working with 40 datawords. This is the result of having a burst of
8 per transaction and 5 consecutive transactions. For example, during the Write stage,
notice the following sequence of events:

RAS asserted to open the row specified by BA and ADDRESS

CAS and WE simultaneously asserted 5 consecutive times
In between each CAS/WE assertion, 8 datawords are written

At this point, the user can choose to customize the simulation view to look at other
internal signals. The user can also modify the simulation testbench, the sim.do file, or the
controller code and re-simulate.

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Simulating a VHDL MIG DDR2 Controller with

v9.2 February 7, 2008

Revision History
Date
02/07/08

Version
9.2

Revision
Initial Avnet release.

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