Investigation of 6T-SRAM performance and

comparision using the experimental data of 70 nm

technology MOSFET and 22 nm FinFET
Razaidi Hussin1,2, Fikru Adamu-Lema1, Xingsheng Wang1, Louis Gerrer1 , Jie Ding1 , Liping Wang1 , Salvatore M.
Amoroso3 , Binjie Cheng3 , Dave Reid3, Andrew R. Brown3 , Pieter Weckx4 , Marco Simicic4 , Jacopo Franco4 , Naoto
Horiguchi4 , Ben Kaczer4 and Asen Asenov1,3
1

Device Modelling Group, University of Glasgow, G12 8LT, Glasgow, UK

2
School of Microelectronic Engineering, Universiti Malaysia Perlis,
3
Gold Standard Simulations Ltd, G12 8QQ, Glasgow, UK, 4imec, 3001 Leuven, Belgium
Abstract- Performance of 6T-SRAM circuit between 70 nm
conventional transistor and 22 nm FinFET architecture have been
compared and analised. The SNM values in both cases has been
investigated. Correlations betwee figure of merit of individual devices
obtained from compact model extraction and TCAD simulation are
presented. The aging process and their effect on SRAM circuits at
different degradation levels in varioius oprationsl senarios are
discussed.
Key words: SRAM; Variability; Reliability; compact model

I.

INTRODUCTION

SRAM cell array is critically important as the memory cache

in modern chips and its performance depends on the quality of
design and the proper synthesis of building block devices. As it
is sensitive to the limit of the particular technology, its
performance relies mainly on how good the performance of the
building transistors is. Since SRAM is designed with the
minimized transistors to increase the cell density which renders
it to be the most vulnerable to variability and reliability
(including to global and statistical local variability), in this study
we mainly focus on the evaluation of the SRAM performance
(e.g. static noise margin) subject to random trap induced
reliability. The highlighted design work flow in general includes
calibration of device to experimental data, extensive simulation
and multiple modelling stages to ensure that the products will
deliver the expected performances and yield in the context of
increasing circuits complexity. As device dimensions are scaled
down, the suitable device structure, which has very good device
performance, result in excellent circuit performance.
II.

TCAD CALIBRATION AND SIMULATION

In this paper, two device structures are used for the purpose
of the investigation and comparison of SRAM cells. The first is
the conventional transistor 70 nm technology fabricated at imec
for comparision purpose. The experimental data is extracted
from the device featuring a gate length of 60 nm and width of 90
nm. The gate oxide thickness of 2.2 nm is considered using SiON
as gate oxide material. The second device, which is used in this
work is an Intel 22 nm FinFET with a 60 nm fin pitch and 90 nm
gate pinch [1].Fig.1 illustrated for both calibrated TCAD model.
The main calibration process of these device is illustrated on the

Figure 1: Figure 2: Carrior concentration profile of the calibrated TCAD model

which is based on the conventional transistor (left) and FinFET (right)

flow chart shown in Fig. 2. It consists of three stages of

calibration process. Firstly, it estimates the realistic doping
profile for the uniformly doped device. The second stage
includes the calibration to statistical variability sources to match
with the measured atomistic device, and finally it is the
calibration of the effect of reliability.
Before the calibration, the TCAD structures for both devices
are extracted by means of TEM image. This is an important
method to obtain an accurate dimensions of gate oxide thickness,
gate length, fin width, fin height and fin length. The calibration
of the uniform device starts with the matching of the doping
profile to the conventional device, by using analytical process
simulator ANADOP [2]. The doping profile estimated at this
stage is further refined by considering the back-bias dependence
of the profile. This will help us to get a realistic vertical doping
profile. To calibrate the horizontal doping profile the threshold
voltage roll-off dependence is used which gives a realistic
approximation of doping profile in horizontal direction.
Regarding the design and modeling of 22 nm Intel FinFETs,
due to limited information on important device stricture and
electrical characteristics, three assumptions has been made for
this calibration purpose.
1) The VT for Medium Power (MP) device is calibrated by
WF engineering in order to kept low channel doping.
2) The High Power (HP) device performance is based on
reduction of channel length.
3) The Low Power (LP) device performance is based on the
improvement in channel doping concentrattion.

Figure 3: Calibration in Uniform p-channel device of I

(left) FinFET.(right)

conventional device

Figure 4: Statistical distribution of threshold voltage for p-channel device at

different stages in conventional device (left) FinFET (right).

Figure 2: TCAD model calibration flow used in this study.

The main target in uniform calibration stage is to get a very

good electrostatic property of the device of interest when
compared with an average of measurement results. Fig. 3 shows
an excellent agreement in term of subthreshold slope (SS), drain
induced barrier lowering effect (DIBL), leackage current (IOFF)
and drive current (ION) between the TCAD simulation and
measured device for the conventional device and the published
data of the Intel 22nm FinFET.
The calibration process in conjunction with the process
induced variability on device performance is continued in the
second stage. In the 70nm conventional device, a typical
parameter for line edge roughness (LER) and Fermi pining in
polysilicon grain (PSG) boundaries allows a fine tuning of the
doping level at the interface to improve the estimation of SV
from the measured data. However, since information regarding
the variability and reliability has not been published, the
parameter in gate edge roughness (GER) and metal grain
granularity (MGG) (like correlation length and grain diameter
respectively) are defined as close as to the current technology.
Finally the conventional device is simulated in BTI stress
induced condition by introducing trap sheet density [3]. This was
done after having an observation of single trapped charge impact
on the threshold against the measurement data [4]. In the Intel
FinFET, the simulation in time dependent variability (TDV) is
carried out at two levels of degradation with given values of
4.6E11 cm-2 and 1.2E12 cm-2. The corresponding threshold
voltage quantile distribution from the degraded devices is
illustrated in Fig. 4. It is important to note that the BTI
degradation can be predicted in these devices without taking the
reliability measurement based on the statistical simulation
results. Complete simulation data for both devices is published
in [5-7].

III.

COMPAT MODEL EXTRACTION AND GENERATION

The compact model (CM) library is generated by a GSSs

Mystic as described in details elsewhere in [8-10]. The extraction
process consists of three stages starting from the TCAD model
extraction in uniform device, followed by statistical extraction of
statistical compact model, which is extended for CM extraction
for the degraded device with different level of degradation. The
advantages of CM extraction over analytically generated
parameter dispersion is that it uniquely captures the correlation
between the figure of merit in each devices [9]. Figure 5
illustrated the figures of merit for fresh p-channel device in (a)
conventional device and (b) Intel 22 nm FinFET showing an
excellent agreement between the extracted CM and TCAD
simulations. Once the CM library is established, the statistical
sample can be generated for a higher sigma to allow a proper
SRAM reliability assessment [11]. Note that, the sample in
arbitrary level of degradation can also be interpolated using a
GSS Mystic.
IV.

6T-SRAM CELL AGEING

The extracted and generated statistical CM and library The

extracted statistical CM and generated statistical CM library
respectively for both devices are used to evaluate the 6T-SRAM
performance in terms of static noise margin (SNM) distributions.
Figure 6 illustrated the 6T-SRAM circuit configured by 1:1:1
(PU:PD:PG) in terms of width ratio or fin number is used in this
study and the summary of several scenarios used for
investigation. Scenario A corresponds to the holding 0
operation for a long period. This means that the N1 and P2
devices are subject to a BTI stress condition. As the operation
continues for a long period, the total degradation is characterized
based on the permanent and recoverable ageing process.
Scenario B is related to the fast reading and writing operations.

TABLE I.

SUMMARIZED
DEGRADATION RATIO.

Scenario A
NT_NMOS=NT_PMOS

SIMULATION

Scenario B
NT_NMOS=NT_PMOS
#

SCENARIO

WITH

DEVICE

Scenario C
NT_NMOS=NT_PMOS
#

NT_NMOS= NT_PMOS NT_NMOS=$NT_PMOS NT_NMOS=$NT_PMOS

NT_NMOS= NT_PMOS NT_NMOS=&NT_PMOS NT_NMOS=&NT_PMOS

30

25

25

20
15
10
0

NT_NMOS=NT_PMOS
NT_NMOS=NT_PMOS/2
NT_NMOS=NT_PMOS/4

2
4
8
6
11
-2
Trap Density [x10 cm ]

10

$
#

$
#

&

PG= NT_NMOS= NT_PMOS

PG= NT_NMOS= NT_PMOS
30

NT_NMOS=NT_PMOS
NT_NMOS=NT_PMOS/2

20

25

15

15
10
0

10

NT_NMOS=NT_PMOS/4
NT_PG=NT_NMOS/2=NT_PMOS/2

20

10
0

2
4
8
6
11
-2
Trap Density [x10 cm ]

NT_NMOS=NT_PMOS
NT_NMOS=NT_PMOS/2

NT_NMOS=NT_PMOS/4

SNM [mV]

30

SNM [mV]

(a)

SNM [mV]

Additional scenario focused on a

realistic degradation in SRAM circuit

NT_PG=NT_NMOS/2=NT_PMOS/4

2
4
8
6
11
-2
Trap Density [x10 cm ]

10

Figure 7: SNM standard deviation for three considered scenario in the

conventional device for scenarios A, B & C.
30

NT_NMOS=NT_PMOS

Figure 5: Correlation between extracted Figure of Merit from the fresh p-channel
device of (a) the conventional device and (b) FinFET.

Figure 6. Investigated 6T-SRAM cell (left) and considered scenarios chart (right):
scenario A corresponds to the hold phase; B to fast writing and reading as well
as C which includes Pass-Gate degradation. NMOS degradation level is
successively considered as equivalent to, half and quarter of the PMOS devices
degradation.

In this operation, N1 and P2 are alternately in ON state with the

N2 and P1, which are operating at a higher frequency. By
assuming that this frequency is faster than the recoverable period.
It means that the total degradation is based on permanent and
recoverable ageing. Finally, in Scenario C, the Pass Gate (PG)
transistor degradation is taken into account when performing
reading in worldline boosting subsystems.

NT_NMOS=NT_PMOS/4

SNM [mV]

SNM [mV]

(b)

30

NT_NMOS=NT_PMOS
NT_NMOS=NT_PMOS/2

NT_NMOS=NT_PMOS/2

25
20

25
20

25

15

15

15

10
0

10
0

10

2
4
8
6
11
-2
Trap Density [x10 cm ]

10

NT_NMOS=NT_PMOS/4
NT_PG=NT_NMOS/2=NT_PMOS/2

20

10
0

2
4
8
6
11
-2
Trap Density [x10 cm ]

NT_NMOS=NT_PMOS
NT_NMOS=NT_PMOS/2

NT_NMOS=NT_PMOS/4

SNM [mV]

30

NT_PG=NT_NMOS/2=NT_PMOS/4

2
4
8
6
11
-2
Trap Density [x10 cm ]

10

Figure 8: SNM standard deviation for three considered scenario in Intel FinFETs
for scenarios A, B & C.

The degradation in n-channel device and p-channel device didnt

have a similar sensitivity as measured in [12]. The NBTI
phenomenon triggered earlier and induce more degradation
compare with the PBTI. This is because of the different charge
injection into a traps. Based on measured data in [12], the NBTI
degradation is considered as three times larger compare to the
PBTI degradation. In order to observe the SNM distribution for
these devices, we have considered three different cases: 1) when
the NMOS degradation is equal to the PMOS degradation, 2)
when the NMOS degradation is half of the PMOS degradation
and finally the NMOS degradation is quarter of the PMOS
degradation. In Scenario C, where the degradation in PG has
taken into account, another two cases have been added. In
Scenario C, case four, the PG degradation is half of the NMOS
and PMOS. On the other hand, case five, the PG degradation is
half of the NMOS and quarter of the PMOS transistors. Table 1
summarized the scenario setup with revice degradation ratio.
Figure 7 and Figure 8 illustrate the standard deviation for
both devices. For all cases, the standard deviations are increased
as device degradation level increases. We observed that,
Scenario A produce more variability when compared to Scenario
B. For the conventional transistor, there is an increment of 47%
in Scenario A while only 14.6% in Scenario B due to the trapped
charge reaching the largest value here 1E12 cm-2. On the other
hand, in the Intel FinFET, Scenario A produces 13.4% increment
when compared with the Scenario B which is only 3% increment.
The higher variability in Scenario A is due to the ageing of the
device and the imbalance of the degrade inverter pair as well.

0.19

0.18

0.18

0.16
0.14
0.12
0.10
0

NT_NMOS=NT_PMOS
NT_NMOS=NT_PMOS/2

2
4
8
6
11
-2
Trap Density [x10 cm ]

0.16
0.14
0.12

NT_NMOS=NT_PMOS/4

10

<SNM> [V]

0.20

0.18

<SNM> [V]

<SNM> [V]

0.20

0.10
0

NT_NMOS=NT_PMOS
NT_NMOS=NT_PMOS/2

0.15

NT_NMOS=NT_PMOS/4

2
4
8
6
11
-2
Trap Density [x10 cm ]

0.17
0.16

0.14
0

10

[3]

NT_NMOS=NT_PMOS
NT_NMOS=NT_PMOS/2
NT_NMOS=NT_PMOS/4
NT_PG=NT_NMOS/2=NT_PMOS/2
NT_PG=NT_NMOS/2=NT_PMOS/4

2
4
8
6
11
-2
Trap Density [x10 cm ]

10

Figure 9: average SNM for three considered scenario in conventional device

80

90
NT_NMOS=NT_PMOS

85

NT_NMOS=NT_PMOS/2

<SNM> [mV]

<SNM> [mV]

85

NT_NMOS=NT_PMOS/4

75
70
65
0

80

90
NT_NMOS=NT_PMOS

85

NT_NMOS=NT_PMOS/2

<SNM> [mV]

90

NT_NMOS=NT_PMOS/4

75
70

2
4
8
6
11
-2
Trap Density [x10 cm ]

10

65
0

NT_NMOS=NT_PMOS
NT_NMOS=NT_PMOS/2

[4]

NT_NMOS=NT_PMOS/4
NT_PG=NT_NMOS/2=NT_PMOS/2

80

NT_PG=NT_NMOS/2=NT_PMOS/4

75
70

2
4
8
6
11
-2
Trap Density [x10 cm ]

10

65
0

2
4
8
6
11
-2
Trap Density [x10 cm ]

10

Figure 10: Average SNM for three scenarios that are considered in FinFET

Note that the calibrated FinFET device simulated here is not fully
optimized for SRAM circuit but we can still take an advantages
in predicting the device performance.
Figure 9 and Figure 10 illustrated the average SNM in both
devices. Based on the average SNM distribution, it shows that
the SRAM of Intel FinFET is more stable compare to the that of
conventional bulk device due to the minimum shifting after
device have been degraded. For example, in Scenario A, the
conventional device SNM is reduced by about 35% when
compared to Intel FinFET that exhibits just only 11.7%
reduction.
Another important point that we would like to highlight is the
increments of average SNM in several cases. Generally, when all
devices in the SRAM cell are ageing, its performance will be
affected as well. However, in the case of Scenario C, both
technologies have an increment of average SNM for device
having a similar degradation level in each device. The increasing
in VT resulted an increasing in SNM distribution. We also
observed that the degradation level in PG transistor impacts on
the drivevibility ratio between PG and PD transistors, which
leads to a different trend in average SNM distribution.
V.

CONCLUSIONS

The SNM distributions observed in both technologies

manifest that the holding 0 operation is not good because the
variability impact produces the SRAM SNM distribution. We
also observed that the Intel FinFET is more stable compare to the
convention device since less variation in average SNM value.
Finally, the impact of similar level of degradation in all
transistors has increased the SNM distribution.

[5]

[6]

[7]

[8]

[9]

[10]
[11]

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