LAB#05

Task#01:
module dataflow;
reg [3:0]A;
reg [3:0]B;
reg [3:0]C;
reg [3:0]D;
reg [3:0]E;
reg [3:0]F;
reg [0:3]G;
reg [0:3]H;
reg [0:3]I;
reg [0:3]J;
initial begin
A=4'd5;
B=4'd2;
G=4'b0101;
assign C=A*B;
assign D=A+B;
assign E=A/B;
assign F=A%B;
assign H=G>>1;
assign I=G<<1;
assign J=A<B;
end
endmodule

LAB#05

Introduction To Behaiv
TASK#01:

module mux(out,in1,in2,sel);
output reg out;
input in1,in2,sel;
always@(in1 or in2)
if (sel)
out=in1;
else
out=in2;
endmodule

initial begin
// Initialize Inputs
in1 = 1;
in2 = 0;
sel = 1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

in1 = 0;
in2 = 1;
sel = 0;
#100;

end

endmodule

Task#02
module mux(out,in1,in2,sel);
output reg out;
input in1,in2,sel;
always@(in1 or in2)
case(sel)
1'b0: out=in1; // value of sel statement when sel=0 in1=1
1'b1: out=in2;
endcase
endmodule

Task#03
module ROM(Add,Out);
input [1:0]Add;
output reg [7:0]Out;
reg [7:0]rom[3:0]; //4 locqations of 8-bit each
initial
begin
rom[0]=8'd255;
rom[1]=8'd127;
rom[2]=8'd244;
rom[3]=8'd23;
end
always@(Add)
Out=rom[Add];
endmodule

initial begin
// Initialize Inputs
Add = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

Add=4'd1;
#100;
Add=4'd2;
#100;
Add=4'd3;

end

endmodule

LAB TASK
Blocking assign
module stimulus;
reg x,y,a,b,m;
initial

m=1'b0;
initial begin
#5 a=1'b1;
#25 b=1'b0;
end
initial
begin
#10 x=1'b0;
#25 y=1'b1;
end
initial
#50 $finish;
endmodule

NON-blocking
module stimulus;
reg x,y,a,b,m;
initial
m=1'b0;

initial begin
#5 a<=1'b1;
#25 b<=1'b0;
end
initial
begin
#10 x<=1'b0;
#25 y<=1'b1;
end
initial
#50 $finish;
endmodule