LAB #04

Task #01: Implement 4X1 mux by calling 2x1 mux ?

Code:module mux4using2(i0,i1,i2,i3,s0,s1,y);
input i0,i1,i2,i3,s0,s1;
output y;
wire w1,w2;
mux mux1(w1,i0,i1,s0);
mux mux2(w2,i2,i3,s0);
mux mux3(y,w1,w2,s1);
endmodule
module mux(cout,a,b,s);
output cout;
input a,b,s;
wire w1,w2,w3;
not(w1,s);
and a1(w2,w1,a);
and a2(w3,s,b);
or(cout,w2,w3);
endmodule
RTL Schematic :

Twst Bench coding:

i0 = 1;
i1 = 0;
i2 = 0;
i3 = 0;
s0 = 0;
s1 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here

i0 = 0;
i1 = 1;
i2 = 0;
i3 = 0;
s0 = 1;
s1 = 0;
#100;
i0 = 0;
i1 = 0;
i2 = 1;
i3 = 0;
s0 = 0;
s1 = 1;
#100;
i0 = 0;
i1 = 0;
i2 = 0;
i3 = 1;
s0 = 1;
s1 = 1;
#100;
end
endmodule
Waveform:

Task#02 : Implement 1 bit full Adder ?

Code:module bit1fulladder(a,b,c_in,c_out,sum);
input a,b,c_in;
output sum,c_out;
wire s1,s2,c1;
xor(s1,a,b);
and(c1,a,b);
xor(sum,s1,c_in);
and(s2,c_in,s1);
xor(c_out,s2,c1);
endmodule

Waveform:

Task#03: Implemnt 4 bit adder by calling 1 bit full adder in verilog ?

Code:
module bitadder(sum1,cout1,a,b,cin);
input [3:0]a;
input [3:0]b;
input cin;
output [3:0]sum1;
output cout1;
wire c1,c2,c3;
bit bitadder1(sum1[0],c1,a[0],b[0],cin);
bit bitadder2(sum1[1],c2,a[1],b[1],c1);
bit bitadder3(sum1[2],c3,a[2],b[2],c2);
bit bitadder4(sum1[3],cout1,a[3],b[3],c3);

endmodule
module bit(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
wire w1,w2,w3;
xor(w1,a,b);
and(w2,a,b);
xor(sum,w1,cin);
and(w3,w1,cin);
xor(cout,w3,w2);
endmodule
RTL SCHEMATIC:

TESTBENCH:
initial begin
// Initialize Inputs
a = 4'b0000;
b =4'b0000;

cin =1'b0;
#100;
a = 4'b0011;
b =4'b0100;
cin =1'b0;
#100;
a = 4'b1010;
b =4'b0101;
cin =1'b1;
#100;
end
endmodule
Waveform:

Data Flow Modeling:

i)Models Boolean expression
ii) No routing is required
Example:

Task #04:coding of above Expression in verilog?

Coding:
module expression(A,B,C,D,E,F3);
input A,B,C,D,E;
output F3;
assign F3=(A&B)|(C&D)|(C&E);
endmodule
RTL SCHEMATIC:

Task#05:Implement 2x1 mux using conditional operators?

Coding:
module sd(sel,out,in1,in2);

output out;
input in1,in2,sel;
assign out=sel ? in1:in2;
endmodule
RTL SCHEMATIC:

TEST BENCH:
initial begin
sel = 0;// Initialize Inputs
in1 = 0;// Initialize Inputs
in2 = 1;// Initialize Inputs
#100;
sel = 1;// Initialize Inputs
in1 = 1;// Initialize Inputs
in2 = 0;// Initialize Inputs
#100;
end
endmodule

WAVEFORM:

Task#06: Implement a 4-bit Adder using Data Flow Modeling and

write its test bench?
Coding of 4 bit adder using Data flow modeling:
module fulladder(s,co,a,b,cin);
output [3:0]s;
output co;
input [3:0]a,b;
input cin;
assign {co,s}=a+b+cin;
endmodule
RTL SCHEMATIC:

TEST BENCH:
initial begin
a =4'b0000;

// Initialize Inputs

b = 4'b0000;

// Initialize Inputs

cin = 0;

// Initialize Inputs

#100; // Wait 100 ns for global reset to finish

a =4'b0011;
b =4'b0100;
cin = 0;
#100;
a =4'b0010;
b =4'b0101;
cin = 0;
#100;
a =4'b1001;
b =4'b1001;
cin = 0;
#100;
a =4'b1010;
b =4'b1111;
cin = 0;
#100;
a = 4'b1010;
b =4'b0101;
cin = 1;

#100;
end
endmodule
WAVEFORM:

Task#07: Design a 4-Bit Comparator using Data Flow Modeling?

Coding:
module comparator(a,b,greater,less,equal);
input [3:0]a;
input [3:0]b;
output greater;
output less;
output equal;
assign greater=a>b;
assign less=a<b;
assign equal=a==b;
endmodule
RTL SCHEMATIC:

TEST BENCH:
initial begin
a =4'b0000; // Initialize Inputs
b =4'b0000; // Initialize Inputs
#100; // Wait 100 ns for global reset to finish
a =4'b0001;
b =4'b0010;
#100;
a = 0;
b = 0;
#100;
a =4'b0100;
b =4'b0011;
#100;
end
endmodule

Waveform: