ADC Lab Manual

Common Emitter Amplifier circuit diagram
CE Amplifier without Feedback :
CE Amplifier with Feedback
COMMON EMITTER AMPLIFIER

EXPERIMENT:
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using voltage divider
bias and to determine its:
a. DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d. andwidth of the amplifier
e. Gain -Bandwidth Product
2. REQUIREMENTS:
S.no
Requiremen
t
Name
Transistor
[Active]
Resistor
[Passive]
Components
BC 107
61k, 10k,
1k,
4.7k
1
1,1,1,2
Capacitor
[Passive]
10f, 100f
2,1
Signal Generator
(0-3)MHz
CRO
30MHz
(0-30)V
Equipment
6
DESIGN
Quantit
y
Range
8 Accessories
PROCEDURE:
Regulated power
supply
Bread Board
Connecting
Wires
Given specifications:
VCC= 10V, IC=1.2mA, AV= 30, hFE= 100
(i) To calculate RC:
The voltage gain is
given by, AV= -hfe
(RC|| RF) / hie h ie
= re
re = 26mV / IE = 26mV / 1.2mA
= 21.6 hie = 150 x 21.6
=3.2K
Apply KVL to output loop,
VCC= IC RC + VCE+ IE RE ----- (1)
Single strand
1
as
required
Where VE = IE RE
(IC= IE)
VE= VCC / 10= 1V

Therefore RE= 1/1.2x10-3=0.8K= 1K
VCE= VCC/2= 5V
From equation (1), RC= ( Vcc - VCE - IE RE / IC ) = ________
(ii) To calculate R1&R2:
S=1+ (RB/RE)
Where RE = 1 K and S = 9
RB= (S-1) RE= (R1 || R2) =1K
RB=( R 1R2 ) /( R1+ R2) ------- (2)
VB= VBE + VE = 0.7+ 1= 1.7V
VB= VCC (R2 / R1+ R2 )------- (3)
Solving equation (2) & (3),
R1= ____ & R2= ______
(iii) Input coupling capacitor :
Xci= Rif / 10= 2.4 (since XCi << Rif)
Ci = 1/ 2fXCi = _____
(iv) Output coupling capacitor:
XCO= Rof /10= 5.2
CO = 1/ 2fXCO = _____
3. THEORY:
A common emitter amplifier is type of BJT amplifier which increases the
voltage level of the applied input signal Vin at output of collector.
The CE amplifier typically has a relatively high input resistance (1 - 10 K)
and a fairly high output resistance. Therefore it is generally used to drive
medium to high resistance loads. It is typically used in applications where a
small voltage signal needs to be amplified to a large voltage signal like radio
receivers.
The input signal Vin is applied to base emitter junction of the transistor and
amplifier output Vo is taken across collector terminal. Transistor is
maintained at the active region by using the resistors R1,R2 and Rc. A very
small change in base current produces a much larger change in collector
current. The output Vo of the common emitter amplifier is 180 degrees out
of phase with the applied the input signal V in.
4.
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier using AC
analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from
0Hz to 1MHz in incremental steps and note down the corresponding output
voltage Vo for at least 20
different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi) dB
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB
on y-axis., Bandwidth, BW
= f2-f1
where f1 lower cut-off frequency
a.
f2 upper cut-off frequency

DC ANALYSIS:
It is the procedure to find the operating region of transistor

Steps:
i)
Set Vin = 0 by reducing the amplitude of the input

signal from signal generator
ii)
Open circuit the capacitors since it blocks DC voltage
iii)
Set VCC= +10v and measure the voltage drop across the
Resistor VRC, voltage across Collector- Emitter Junction VCE
and Voltage drop across base emitter junction. V BE
iv)
Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1
. VBE :
2
. VRC
3. VCE
(forward bias)
= ____________
= _______ (REVERSE BIAS)
4
. Ic( Ic = (Vcc VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be
handled by the amplifier, so that it amplifies the input signal without
any distortion.
Procedure:
i.
Apply input signal V in = 20 mV of 1Khz frequency to the amplifier

using the
signal generator between base emitter junction of the
transistor. Find the sinusoidal output using CRO across R L.
ii.
By increasing the amplitude of the input signal find maximum

input voltage V
MSH
across VBE at which the sinusoidal signal
gets distorted during the process which can be seen in the

CRO. The amplitude obtained at this point is maximum
voltage that can be applied to the transistor for efficient
operating of transistor.
V
MSH
MODEL GRAPH:
= _________ volts
TABULATION [Without Feedback ] :

Input voltage (Vin=V MSH/2) =____________V
S. NO
FREQU
ENCY
[Hz]
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
With Feedback :
Input voltage (Vin=V
6.
S. NO
FREQU
ENCY
[Hz]
MSH/2)
=____________ V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
RESULT:
log Vo/Vi
INFERENCE:
The Common Emitter Amplifier was constructed and the following results were
determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
Common Collector Amplifier Circuit Diagram:
MODEL GRAPH:
COMMON COLLECTOR AMPLIFIER

EXPERIMENT: 02
DATE:
1. OBJECTIVE:
To Design and Construct a Common collector Amplifier and to determine its:
a. DC Characteristics
b. Maximum Signal Handling Capacity
c. Gain of the amplifier
d. Bandwidth of the amplifier
e. Gain -Bandwidth Product using frequency response curve
2.
REQUIREMENTS:
S.N
o
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
0-3MHz
0-30MHz
0-30 V
Components
2
Resistor [Passive]
Capacitor [Passive]
Signal Generator
Equipment
CRO
Regulated power
supply
Bread Board
Accessories
8
Connecting Wires
Single strand
Design of Common collector amplifier:

VCC= 15V, IC=1.2mA, hie = 2.1k hFE= 75 hib= 27.6
as
required
(i)
To calculate Zb ( Device input impedance )

Zb = hie + hfe ( RE || RL)
Assume RE = 4.7 K and RL= 3.3 K
Zb = 2.1k + 75 (4.7 K || 3.3 K) = __________
(ii)
To calculate Zi ( Input Impedance )

Zi = R1 || R2 || Zb
Assume R1= R2= 10k
Zi = _______
(iii) To Calculate Voltage gain Av :

Av = [ ( RE || RL ) / ( hib + ( RE || RL) ) ]
Av = _____
3. THEORY:
A common collector amplifier is a unity gain BJT amplifier used for
impedance matching and as a buffer amplifier.
Circuit Operation : When a positive half-cycle of the input signal is applied to
Base emitter junction of transistor the forward bias voltage Vbe is increased,
which in turn increases the base current I b of transistor. Since emitter current Ie
is directly proportional to Ib the voltage drop across the Emitter Ve= IeRe is
increased, hence, output voltage Vo is increased, thus, we get positive halfcycle of the output. It means that a positive-going input signal results in a
positive going output signal and, consequently, the input and output signals are
in phase with each other. Similarly the negative half cycle of input signal
produces negative going output signal.
Characteristics of a CC Amplifier
1.high input impedance (20-500 K )
2.low output impedance (50-1000 )
3.high current gain of (1 + ) i.e. 50 500
4.voltage gain of less than 1 (unity)
5.power gain of 10 to 20 dB
6.no phase reversal of the input signal
4.
PROCEDURE:
3. Determine Maximum input voltage that can be applied to CE amplifier using

analysis.
3. Set the input voltage Vin=V MSH /2 and vary the input signal frequency
from 0Hz to 1MHz in incremental steps and note down the corresponding
output voltage Vo for at least 15 different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vin)
= f2-f1
Where f1 - lower cut-off frequency
f2 - upper cut-off frequency
a. DC ANALYSIS:
Steps:
i)
ii)
iii)
iv)

1
. VBE :
2
. VRC
3. VCE
(forward bias)
= ____________
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ
=______ ) b. Maximum signal handling
capacity :
any distortion.
AC
Procedure:
i.
ii.
Apply input signal Vin = 1 V of 1Khz frequency to the CC amplifier

using the
input voltage V MSH across VBE at which the sinusoidal signal
V
5.
TABULATION
MSH /2)
S. NO
FREQU
ENCY
[Hz]
MSH
= _________ volts
=____________ volts
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
6. RESULT:
The common collector amplifier was constructed and input resistance and gain
were determined. The results are found to be as given below
a) Gain of the amplifier (in dB) :
b) Bandwidth of the amplifier (in Hz) :
c) Gain-Bandwidth product (GBWP) :
Common Base Amplifier Circuit Diagram:
MODEL GRAPH:
COMMON BASE AMPLIFIER
EXPERIMENT:03
DATE:
1. OBJECTIVE:
To Design and Construct a Common Base Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.No
.
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
Connecting Wires
DESIGN PROCEDURE:
Given Transistor specifications:
hie = 2.1k ; hfe = 75 ; hfb =0.987
Single strand
as
required
i) To find Device input impedance :

hib = ( hie / (1+ hfe))
hib = ____
ii) To find Circuit input impedance (Zi) :
Zi = hib || Re ,Where Re= 2.2 k
Zi = _____
iii) To find Circuit output impedance (Zo) :
Zo = Rc ; where Rc = 4.7 k
iv) To find Voltage Gain (Av) :

Av = [ hfb (Rc || RL) / hib ]
Where RL= 10k
Av = _____
THEORY:
A common base amplifier is type of BJT amplifier which increases the

voltage level of the applied input signal Vin at output of collector.
The Common base amplifier typically has good voltage gain and relatively
high output impedance. But the Common base amplifier unlike CE amplifier has
very low input impedance which makes it unsuitable for most voltage amplifier. It
is typically used used as an active load for a cascode amplifier and also as a
current follower circuit.
Circuit Opeartion:
A positive-going signal voltage at the input of a CB pushes the transistor
emitter in a positive direction while the base voltage remains fixed, hence Vbe
reduces. The reduction in VBE results in reduction in VRC, consequently VCE
increases. The rise in collector voltage effectively rises the output voltage. The
positive going pulse at the input produces a positive-going output, hence the
there is no phase shift from input to output in CB circuit. In the same way the
negative-going input produces a negative-going output.
4. PROCEDURE:
2. Determine the Q-point of the CB amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE

amplifier using AC analysis.
4. Set the input voltage Vin=V
/2 and vary the input signal frequency

output voltage Vo for atleast 20 different values for the considered range.
MSH
5. The voltage gain is calculated as Av = 20log (V0/Vi)

= f2-f1
where f1 lower cut-off frequency
f2 upper cut-off frequency
a. DC ANALYSIS:
Steps:
i)
ii)
iii)
iv)

1
. VBE :
2
. VRC
(forward bias)
3. VCE
= ____________
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
b. Maximum signal handling capacity :
any distortion.
Procedure:
i.
Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier
using the
ii.
MSH
= _________ volts
5. TABULATION
S. NO
FREQU
ENCY
[Hz]
MSH
/ 2) =____________V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
RESULT:
The Common base amplifier was constructed and input resistance and gain were
determined. The results are found to be as given below
Darlington Amplifier Circuit Diagram:
MODEL GRAPH:
DARLINGTON AMPLIFIER
EXPERIMENT:04
DATE:
1. OBJECTIVE:
To Design and Construct a BJT amplifier using Darlington pair and to determine its:
a.
b.
c.
d.
e.
2.
DC Characteristics
Gain -Bandwidth Product using frequency response curve
REQUIREMENTS:
S.No
.
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
Connecting Wires
Single strand
as
required
DESIGN PROCEDURE:
VCC= 12V, IC=1.2mA, AV= 30, f1 = 300 HZ, f2 = 500KHZ, hFE= 150
Assume R2 = 10K and Ic = 1mA.
Since voltage amplification is done in the Darlington transistor amplifier
circuit, we assume equal drops across VCE and load resistance RC. The ICQ
= 1mA is assumed.
Drop across Re is assumed to be 1V.

The drop across VCE with a supply of 1.2 V
is given by 12 1 = 1V.
It is equal to VRC & VCE = 5.5V x RC
Therefore, Rc = 5.5 K (4.7 K) ; IC = 1mA
(ii) To calculate R1&R2:
S=1+ (RB/RE)
RB= (S-1) RE= (R1 || R2) =1K
RB=( R 1R2 ) /( R1+ R2) ------- (2)
VB= VBE + VE = 0.7+ 1= 1.7V
VB= VCC (R2 / R1+ R2 )------- (3)
Solving equation (2) & (3),
Since R2=10k , the other resistor is found to be, R1= 47k
(iii) To Find Cin :
Cin = * 1 / 2f1 (Zi / 10) ]
Where Zi = ( RB || hie ) = 1.1K and
f1 = Lower cut-off
frequency= 25HZ =
57.9F
(iv) To Find CO :
C0 = * 1 / 2f2 ( (RC + RL) / 10) ]
Where RC = 9K; RL = 90K and
f2 = Upper cut-off frequency=
500KHZ = 64 F
3. THEORY:
The Darlington transistor (often called a Darlington pair) is compound
structure consisting of two bipolar transistors connected in such a way that
the First transistor does current amplification of input signal and then it will be
fed to the second transistor which performs voltage amplification.
This configuration gives a much higher gain than each transistor taken
separately and, in the case of integrated devices, can take less space than two
individual transistors because they can use a shared collector. The Darlington
amplifier typically has a relatively high input resistance (1 - 10 K) and a fairly
high output resistance. Therefore it is generally used to drive medium to high
resistance loads. It is typically used in applications where a small voltage signal
needs to be amplified to a large voltage signal like radio receivers.
4.
PROCEDURE:
2. Determine the Q-point of the Darlington amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to Darlington
MSH /2 and vary the input signal frequency

output voltage Vo for at least 20 different values for the considered range.

6. Find the Bandwidth and Gain-Bandwidth Product from Semilog graph taking frequency on x-axis and gain in dB on yaxis.,
Bandwidth, BW = f2-f1
where f1 - lower cut-off frequency
a. DC ANALYSIS:
Steps:
i)
ii)
iii)
iv)

1
. VBE :
2
. VRC
(forward bias)
3. VCE
= ____________
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
=______
Q-point: ( ICQ =_____ ; VCEQ
handling capacity :
b. Maximum signal

any distortion.
Procedure:
i.
using the
ii.

V MSH = _________ volts

5. TABULATION
S. NO
FREQU
ENCY
[Hz]
MSH/2)
=____________ V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
RESULT:
The Darlington amplifier was constructed and the results are found to be
a. Gain of the amplifier :
b. Bandwidth of the amplifier :
c. Gain-Bandwidth product :
Common Source Amplifier Circuit Diagram:
MODEL GRAPH
COMMON SOURCE AMPLIFIER

EXPERIMENT:05
1.
DATE:
OBJECTIVE:
To Design and Construct a Common source amplifier using the

bootstrapped gate resistance and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Gain -Bandwidth Product
2. REQUIREMENTS:
S.No
.
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BFW10
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Equipment
Bread Board
Accessories
Connecting Wires
Single strand
as
required
DESIGN ANALYSIS :
Given :
VDD = 20 V, IDSS = 5mA, ID = 1.5 mA,
i) To Find the voltage across the Gate-source region (V GS)
VGS = ID RS
Assume RS = 3.3K,
VGS = 1.5mA x 3.3K = _____
ii) To find Voltage Across Drain to Source (VDS)

VDS= VDD - ID ( RD + Rs) ; Where RD= 3.3 K
= 20V 1mA ( 3.3 K + 3.3 K)
= ________
iii) To Find input impedance :
Zi = RG ; Assume RG = 1M
iv) To Find output impedance :
ZO = RD ||rd
3. THEORY
There are three basic types of FET amplifier or FET transistor namely
common source amplifier, common gate amplifier and source follower amplifier.
The common-source (CS) amplifier may be viewed as a transconductance
amplifier or as a voltage amplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating
the current going to the load.
ii)As a voltage amplifier, input voltage modulates the amount of current
flowing through the FET, changing the voltage across the output resistance
according to Ohm's law.
However, the FET device's output resistance typically is not high enough
for a reasonable transconductance amplifier (ideally infinite), nor low enough for
a decent voltage amplifier (ideally zero). Another major drawback is the
amplifier's limited high-frequency response. Therefore, in practice the output
often is routed through either a voltage follower (common-drain or CD stage), or
a current follower (common-gate or CG stage), to obtain more favorable output
and frequency characteristics
4. PROCEDURE:
2. Determine the Q-point of the CS amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency
output voltage Vo for atleast 20 different values for the considered range.
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log
graph taking frequency on x-axis and gain in dB on y-axis.,
a. DC ANALYSIS:
Steps:
i)

ii)
iii)
iv)
1
. VGS :
2
. VDS
3 ID
= ____________
= ____________
= _______

any distortion.
Procedure:
i.
Apply input signal Vin = 1 V of 1Khz frequency to the CS amplifier
using the
ii.
MSH
= _________ volts
5. TABULATION
S. NO
FREQU
ENCY
[Hz]
MSH/2)
=____________V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
6. RESULT:
INFERENCE:
The common Source amplifier was constructed and input resistance and gain
were determined. The results are found to be as given below
a) Gain of the amplifier (in db) :
b) Bandwidth of the amplifier (in HZ) :
c) Gain-Bandwidth product (GBWP) :
Cascade amplifier Circuit Diagram:
MODEL GRAPH:
CASCADE AMPLIFIER
EXPERIMENT:06
DATE:
1. OBJECTIVE:
To Design and Construct a Cascade Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
2. REQUIREMENTS:
S.No
.
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Bread Board
Accessories
Connecting Wires
Single strand
DESIGN PROCEDURE:
VCC= 14 V, IC1=1.2mA, RL = 40K hFE= 100
(i) To calculate R5 :
Assume VE1 = 5V , VCE1 = VCE2 = 3V;
VB2 = VC1 = VE1 + VCE1 = 5V + 3V = 8V
VE2 = VB2 VBE = 8V 0.7V = 7.3V
as
required
VR5 = Vcc VE2 VCE2 = 14V 7.3V 3V = 3.7V

Choose R5 = RL / 10 = 40K / 10 = 4K ;
IC2 = ( VR5 / R5 ) = 3.7V / 3.9K = 1000A
(ii) To calculate R6 :
VR6 = VE2 / IC2 = 7.7K;
IC2 = VE2 / R6 = 7.3V / 8.2 K = 890A
(iii) To calculate R1, R2 , R3 & R4:
Voltage across resistor R3 is given by
VR3 = Vcc VC1 = 14V 8V = 6V
R3 = VR3 / IC1 = 6V / 1mA = 6K
R4 = VE1 / IC1 = 5V/ 1mA = 4.7K
Voltage across resistor R2 is given by
VR2 = VE1 VBE = 5V + 0.7V =5.7V
R2 = 10 R4 = 4.7 K
VR1 = VCC VB1 = 14V + 5.7V =8.3V
R1 = [ VR1 x R2 / VR2] = 68.4 K
3. THEORY:
A cascade is type of multistage amplifier where two or more single stage
amplifiers are connected serially. Many times the primary requirement of the
amplifier cannot be achieved with single stage amplifier, because Of the
limitation of the transistor parameters. In such situations more than one
amplifier stages are cascaded such that input and output stages provide
impedance matching requirements with some amplification and remaining
middle stages provide most of the amplification. These types of amplifier circuits
are employed in designing microphone and loudspeaker.
4.
PROCEDURE:
2. Determine the Q-point of the amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using AC
analysis.
MSH /2 and vary the input signal frequency

output voltage Vo for atleast 20

6. Find the Bandwidth and Gain-Bandwidth Product from Semilog graph taking frequency on x-axis and gain in dB on yaxis.,
DC ANALYSIS:
Steps:
v)

vi)
vii)
viii)
1
. VBE :
2
. VRC
(forward bias)
= ____________
3. VCE
4
. Ic( Ic = (Vcc VCE ) / Rc) =________
Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )

any distortion.
Procedure:
iii.
using the
transistor.Find the sinusoidal output using CRO across R L.
gets distorted during the processwhich can be seen in the
iv.
MSH
= _________ volts
5. TABULATION
MSH/2)
=____________ volts
6.RES
The
Cascade
amplifier
was
ULT:
S. NO
FREQU
ENCY
[Hz]
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
constructed and input resistance and gain were determined. The results are
found to be as given below
Cascode amplifier Circuit Diagram:
MODEL GRAPH:
CASCODE AMPLIFIER
EXPERIMENT: 07
DATE:
1. OBJECTIVE:
To Design and Construct a Cascode Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
2. REQUIREMENTS:
S.No
.
Requireme
nt
Name
Range
Quantity
Transistor [Active]
BC 107
Resistor [Passive]
61k, 10k,
1k,
4.7k
Capacitor [Passive]
10f, 100f
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Bread Board
Components
1,1,1,2
2,1
Equipment
Accessories
8
Connecting Wires
Single strand
DESIGN PROCEDURE:
VCC= 20V, IC =1.2mA, AV= 30, , RL = 90K ;
Transistor Parameters: hFE= 50 , hie = 1.2K and hib= 24
Rc = RL / 10 = 90k / 10 = 9K
(ii) To calculate RE:
Assume VCE1 = VCE2 = 3V, and VE = 5V;
The voltage drop across collector resistor is given by,
VRC = VCC - VCE1 - VCE2 VE
as
required
= 20V 3V
3V- 5V VRC = 9V
RE = VE / IE ; Where IE = Ic
= 1.1mA RE = 4.5K
(iii) To Calculate Bias Resistors R1, R2, R3 :
a. R3 = 10 RE = 47K
b. Voltage Across the base of Transistor 1 is given by,
VB1 = VBE + VE
VB1 = 5V + 0.7V = 5.7V
c. Voltage Across the base of Transistor 2 is given by
VB2 = VBE2 + VE + VBE2
= 5V + 3V + 0.7V
= 8.7V
d. Voltage across resistor R2 is given by
VR2 = VB2 - VB1
VR2 = 8.7V 5.7V = 3V
e. The resistor R2 is given by R2 = (VR2 / I3 ) =
(3V / 121A) R2 = 24.8K
f. Resistor R1 = [VCC - VB2 / I3 ]
= [ 20V 8.7V / 121 A]
= 93.4 K
Determination of Capacitor Values:
To Find C1 :
C1 = * 1 / 2f1 (Zi / 10) ]
Where Zi = ( R3 || R2 ) = 1.1K and
f1 = Lower cut-off
frequency= 25HZ =
57.9F
To Find C2 :
C2 = * 1 / 2f1 (hie2 / 10) ] = 53 F
Where hie2= 1.2 K and f1 = Lower cut-off frequency= 25HZ;
To Find C3 :
C3 = * 1 / 2f1hib ]
Where hib= 24 and
f1 = Lower cut-off
frequency= 25HZ =
256F
To Find C4 :
C4 = * 1 / 2f1 ( (RC + RL) / 10) ]
Where RC = 9K; RL = 90K and
f1 = Lower cut-off
frequency= 25HZ = 0.64
F
THEORY:
The cascode configuration has one of two configurations of multistage
amplifier. In each case the collector of the leading transistor is connected to the
emitter of the following transistor. The arrangement of the two transistors is
shown in the circuit diagram. The cascode amplifier consists of CE stage
connected in series with CB stage. The arrangement provides a relatively high
input impedance with low voltage gain for the first stage to ensure the input
miller capacitance is at a minimum, whereas the following CB stage provides an
excellent high frequency response.
Features:
1. It provides high voltage gain and has high input impedance.
2. It provides high stability and has high output impedance
PROCEDURE:
3. Determine Maximum input voltage that can be applied to CE amplifier using AC
analysis.
MSH /2 and vary the input signal frequency from

0Hz to 1MHz in incremental steps and note down the corresponding output
voltage Vo for atleast 20 different
values for the considered range.
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph

taking frequency on x-axis and gain in dB on y-axis.,
where f1 - lower cut-off
frequency f2 - upper
cut-off frequency
a. DC ANALYSIS:
Steps:
ix)

x)
xi)
xii)
1
. VBE :
2
. VRC
(forward bias)
= ____________
3. VCE
4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q point analysis:
Q-point: ( ICQ =_____ ; VCEQ =______ )
any distortion.
Procedure:
v.
using the
transistor.Find the sinusoidal output using CRO across R L.
gets distorted during the processwhich can be seen in the
vi.
MSH
= _________ volts
5. TABULATION
S. NO
FREQU
ENCY
[Hz]
MSH/2)
=____________ V
GAIN= 20
log Vo/Vi
S. NO
FREQUENCY
[Hz]
GAIN= 20
log Vo/Vi
6. RESULT:
The Cascode amplifier was constructed and input resistance and gain were
Differential amplifier Circuit Diagram:

Common Mode :
EXPERIMENT: 08
DATE:
DIFFERENTIAL AMPLIFIER
1. OBJECTIVE:
To Design and Construct a Differential Amplifier using BJT and to determine its:
a.
b.
c.
d.
Transfer Characteristics
Gain of the amplifier in common mode
Gain of the amplifier in differential mode
CMRR (Common Mode Rejection Ratio)
2. REQUIREMENTS:
S.No
Requireme
.
nt
1
Name
Transistor [Active]
Range
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated power
supply
(0-30)V
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
Accessories
8
Connecting Wires
Single strand
as
required
3. THEORY:
A differential amplifier is a type of electronic amplifier that amplifies the
difference
between two voltages but does not amplify the particular voltages. The need for
differential
amplifier arises in many physical measurements where response from D.C to many
MHZ is
required. It is also used in input stage of integrated amplifier.
DESIGN PROCEDURE:
VCC= 12V, IC=1.2mA, VCE = 5V
Assume Q1 = Q2
Where Q1 = Transistor 1 and Q2 = Transistor 2.
The Collector resistance Rc1 is given by using KVL at the transistor 1
Vcc = IcRc1 VCE Ie1Re1
Rc1 = (Vcc + VCE + Ie1Re1 ) / Ic,
Where VCE = 5V and Ic = 1.2mA, Ie1 = Ic/10 and assume Re1 = 470
Now Rc1 = 1k .
MODEL GRAPH:
Differential amplifier Transfer Characteristics:
The output signal in differential amplifier is proportional to the difference

between the two input signals.
Vo = Ad (V1 V2 ).
Where V1,V2 are the input voltages and Ad is the differential gain.
If V1 = V2, then output voltage is zero. A non zero output voltage is obtained if V1
and V2
are not equal.
i)
The difference mode input voltage is defined as V d = (V1-V2)
ii)
iii)
The common mode input voltage is defined as the V cm= (V1+V2)/2

The CMRR is defined as the ratio of the differential gain Ad to
common mode gain Ac and is generally expressed in dB.
CMRR= 20 log10 ( Ad / Ac)

4. PROCEDURE:
2. Determine the Q-point of the Differential amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to
4. Determine the Transfer characteristics of Differential amplifier by plotting
the graph for normalized differential input voltage [ (Vb1 V b2) / VT ] vs.
Normalized collector current [ Ic / Io].
5. Calculate the voltage gain of differential amplifier for differential mode
as Ad = 20log (V0/Vi) , Where Vi = V1 V2
6. Calculate the voltage gain of differential amplifier for
Common mode as AC = 20log (V0/Vi) , Where Vi = (V1+
V2 / 2 )
7. Find the Common mode rejection ratio of differential amplifier using the formula
given
below.
CMRR= 20 log10 ( Ad/Ac)
Where Ad- Differential mode gain in dB
Ac Common Mode gain in dB
a. DC ANALYSIS:
Steps:
i)
ii)
iii)
iv)

1
. VBE :
2
. VRC
(forward bias)
= ____________
3. VCE
4
. Ic( Ic = (Vcc VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the operating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )

any distortion.
Procedure:
vii.
using the
viii.
V
5.

MSH
= _________ volts
TABULATION
a. Transfer Characteristics Calculation:
S.no
Input Voltage
Vi = (Vb1 Vb2) in Volts
Output Current
Ic2 in Ampere
1.
2.
3.
4.
5.
6.
b. CMRR
Calculation:
To Find Differential Gain (Ad ) :
S. NO
INPUT
VOLTAGE
in volts
1.
Vi1
2.
Vi2
OUTPUT VOLTAGE Diffrential mode gain in

[ VO]
dB
in Volts
AC = 20log (V0/Vi)
where Vi = (V1- V2 )
To Find Common Mode Gain (AC ) :
S. NO
INPUT
VOLTAGE
in volts
1.
Vi1
2.
Vi2
OUTPUT VOLTAGE
[ VO]
in Volts
Common mode gain in

dB
AC = 20log (V0/Vi)
where Vi = (V1+ V2 / 2 )
6. RESULT:
The Differential amplifier was constructed and input resistance and gain were
Trans-Conductance of Differential amplifier ( in
d) millisiemens) :
Differential mode gain in
e) dB
:
f) Common Mode Gain in dB
g) CMRR in dB

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Common Emitter Amplifier circuit diagram

CE Amplifier without Feedback :

CE Amplifier with Feedback

COMMON EMITTER AMPLIFIER

VE= VCC / 10= 1V

f2 upper cut-off frequency

It is the procedure to find the operating region of transistor

Set Vin = 0 by reducing the amplitude of the input

Open circuit the capacitors since it blocks DC voltage

= _______ (REVERSE BIAS)

Apply input signal V in = 20 mV of 1Khz frequency to the amplifier

By increasing the amplitude of the input signal find maximum

across VBE at which the sinusoidal signal

gets distorted during the process which can be seen in the

TABULATION [Without Feedback ] :

Common Collector Amplifier Circuit Diagram:

COMMON COLLECTOR AMPLIFIER

Design of Common collector amplifier:

To calculate Zb ( Device input impedance )

To calculate Zi ( Input Impedance )

(iii) To Calculate Voltage gain Av :

3. Determine Maximum input voltage that can be applied to CE amplifier using

Set Vin = 0 by reducing the amplitude of the input

= _______ (REVERSE BIAS)

4. Ic( Ic = (Vcc VCE ) / Rc) =________

Apply input signal Vin = 1 V of 1Khz frequency to the CC amplifier

Common Base Amplifier Circuit Diagram:

COMMON BASE AMPLIFIER

i) To find Device input impedance :

iv) To find Voltage Gain (Av) :

A common base amplifier is type of BJT amplifier which increases the

3. Determine Maximum input voltage that can be applied to CE

/2 and vary the input signal frequency

5. The voltage gain is calculated as Av = 20log (V0/Vi)

Set Vin = 0 by reducing the amplitude of the input

= _______ (REVERSE BIAS)

4. Ic( Ic = (Vcc VCE ) / Rc) =________

Darlington Amplifier Circuit Diagram:

Drop across Re is assumed to be 1V.

MSH /2 and vary the input signal frequency

5. The voltage gain is calculated as Av = 20log (V0/Vi)

Set Vin = 0 by reducing the amplitude of the input

= _______ (REVERSE BIAS)

4. Ic( Ic = (Vcc VCE ) / Rc) =________

Q-point: ( ICQ =_____ ; VCEQ

It is the process to find the maximum input voltage that can be

signal generator between base emitter junction of the

V MSH = _________ volts

COMMON SOURCE AMPLIFIER

To Design and Construct a Common source amplifier using the

ii) To find Voltage Across Drain to Source (VDS)

Set Vin = 0 by reducing the amplitude of the input

b. Maximum signal handling capacity :

Cascade amplifier Circuit Diagram:

VR5 = Vcc VE2 VCE2 = 14V 7.3V 3V = 3.7V

MSH /2 and vary the input signal frequency

5. The voltage gain is calculated as Av = 20log (V0/Vi)

Set Vin = 0 by reducing the amplitude of the input

b. Maximum signal handling capacity :

Cascode amplifier Circuit Diagram:

MSH /2 and vary the input signal frequency from

6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph

Set Vin = 0 by reducing the amplitude of the input

= _______ (REVERSE BIAS)

Q-point: ( ICQ =_ ; VCEQ =__ )