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For the neuropsychological concept related to human medical electronics, and so on. In addition to being nonmemory, see Flashbulb memory.
volatile, ash memory oers fast read access times, as
Flash memory is an electronic non-volatile computer fast as dynamic RAM, although not as fast as static RAM
or ROM. Its mechanical shock resistance helps explain
its popularity over hard disks in portable devices, as does
its high durability, being able to withstand high pressure,
temperature, immersion in water, etc.[2]
Although ash memory is technically a type of EEPROM, the term EEPROM is generally used to refer
specically to non-ash EEPROM which is erasable in
small blocks, typically bytes. Because erase cycles are
slow, the large block sizes used in ash memory erasing
give it a signicant speed advantage over non-ash EEPROM when writing large amounts of data. As of 2013,
ash memory costs much less than byte-programmable
EEPROM and has become the dominant memory type
wherever a system requires a signicant amount of nonvolatile, solid-state storage.
A USB ash drive. The chip on the left is the ash memory. The
controller is on the right.
1 History
Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba
circa 1980.[3][4] According to Toshiba, the name ash
was suggested by Masuokas colleague, Shji Ariizumi,
because the erasure process of the memory contents reminded him of the ash of a camera.[5] Masuoka and
colleagues presented the invention at the IEEE 1984 InWhereas EPROMs had to be completely erased before ternational Electron Devices Meeting (IEDM) held in San
being rewritten, NAND type ash memory may be writ- Francisco.[6]
ten and read in blocks (or pages) which are generally
Intel Corporation saw the massive potential of the invenmuch smaller than the entire device. NOR type ash al- tion and introduced the rst commercial NOR type ash
lows a single machine word (byte) to be writtento an
chip in 1988.[7] NOR-based ash has long erase and write
erased locationor read independently.
times, but provides full address and data buses, allowing
The NAND type is primarily used in memory cards, USB
ash drives, solid-state drives (those produced in 2009 or
later), and similar products, for general storage and transfer of data. NAND or NOR ash memory is also often
used to store conguration data in numerous digital products, a task previously made possible by EEPROM or
battery-powered static RAM. One signicant disadvantage of ash memory is the nite number of read/write
cycles in a specic block.[1]
density and lower cost per bit than NOR ash; it also has
up to ten times the endurance of NOR ash. However, the
I/O interface of NAND ash does not provide a randomaccess external address bus. Rather, data must be read on
a block-wise basis, with typical block sizes of hundreds
to thousands of bits. This makes NAND ash unsuitable
as a drop-in replacement for program ROM, since most
microprocessors and microcontrollers required byte-level
random access. In this regard, NAND ash is similar to
other secondary data storage devices, such as hard disks
and optical media, and is thus very suitable for use in
mass-storage devices, such as memory cards. The rst
NAND-based removable media format was SmartMedia
in 1995, and many others have followed, including:
MultiMediaCard
Secure Digital
Memory Stick, and xD-Picture Card.
A new generation of memory card formats, including RSMMC, miniSD and microSD, and Intelligent Stick, feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm2 , with a thickness of less than 1 mm. microSD capacities range from
64 MB to 200 GB, as of March 2015.[10]
Source
Line
Bit Line
Word Line
Control Gate
PRINCIPLES OF OPERATION
Float Gate
N
Principles of operation
Despite the need for high programming and erasing voltages, virtually all ash chips today require only a single
supply voltage, and produce the high voltages using onchip charge pumps.
Over half the energy used by a 1.8 V NAND ash chip
is lost in the charge pump itself. Since boost converters are inherently more ecient than charge pumps, researchers developing low-power SSDs have proposed returning to the dual Vcc/Vpp supply voltages used on all
the early ash chips, driving the high Vpp voltage for all
ash chips in a SSD with a single shared external boost
converter.[12][13][14][15][16][17][18][19]
2.3
2.2
NAND ash
NOR ash
0V
open
SOURCE
oating
gate
200A
DRAIN
12 V
Word
Line 0
Word
Line 1
N, GND
Word
Line 2
Word
Line 3
N, GND
Word
Line 4
Word
Line 5
N, GND
2.2.2 Erasing
12 V
0V
SOURCE
oating
gate
200A
DRAIN
12 V
LIMITATIONS
2.4.1 Structure
Bit Line
Ground
Select
Transistor
Word
Line 0
Word
Line 1
Word
Line 2
Word
Line 3
Word
Line 4
Word
Line 5
Word
Line 6
Bit Line
Select
Transistor
Word
Line 7
2.4.2 Construction
Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers
and insulating silicon dioxide layers.[22]
The next step is to form a cylindrical hole through these
layers. In practice, a 128 Gibit V-NAND chip with 24
layers of memory cells requires about 2.9 billion such
holes. Next the holes inner surface receives multiple
coatings, rst silicon dioxide, then silicon nitride, then a
second layer of silicon dioxide. Finally, the hole is lled
with conducting (doped) polysilicon.[22]
2.4.3 Performance
3 Limitations
2.4
Vertical NAND
3.1 Block erasure
3.3
Read disturb
5
routers, which are programmed only once or at most a few
times during their lifetimes.
3.2
Memory wear
Another limitation is that ash memory has a nite number of programerase cycles (typically written as P/E cycles). Most commercially available ash products are
guaranteed to withstand around 100,000 P/E cycles before the wear begins to deteriorate the integrity of the
storage.[23] Micron Technology and Sun Microsystems
announced an SLC NAND ash memory chip rated for
1,000,000 P/E cycles on 17 December 2008.[24]
The guaranteed cycle count may apply only to block zero
(as is the case with TSOP NAND devices), or to all blocks
(as in NOR). This eect is partially oset in some chip
rmware or le system drivers by counting the writes and
dynamically remapping blocks in order to spread write
operations between sectors; this technique is called wear
leveling. Another approach is to perform write verication and remapping to spare sectors in case of write failure, a technique called bad block management (BBM).
For portable consumer devices, these wearout management techniques typically extend the life of the ash
memory beyond the life of the device itself, and some
data loss may be acceptable in these applications. For
high reliability data storage, however, it is not advisable
to use ash memory that would have to go through a large
number of programming cycles. This limitation is meaningless for 'read-only' applications such as thin clients and
4 LOW-LEVEL ACCESS
Low-level access
4.1
NOR memories
Typical NOR ash does not need an error correcting some bad blocks. These are typically marked according
code.[32]
to a specied bad block marking strategy. By allowing
7
some bad blocks, the manufacturers achieve far higher interfaces for nonvolatile memory subsystems, including
yields than would be possible if all blocks had to be ver- the ash cache device connected to the PCI Express
ied good. This signicantly reduces NAND ash costs bus.
and only slightly decreases the storage capacity of the
parts.
When executing software from NAND memories, virtual 5 Distinction between NOR and
memory strategies are often used: memory contents must
NAND ash
rst be paged or copied into memory-mapped RAM and
executed there (leading to the common combination of
NOR and NAND ash dier in two important ways:
NAND + RAM). A memory management unit (MMU)
in the system is helpful, but this can also be accomplished
the connections of the individual memory cells are
with overlays. For this reason, some systems will use
dierent
a combination of NOR and NAND memories, where a
smaller NOR memory is used as software ROM and a
the interface provided for reading and writing the
larger NAND memory is partitioned with a le system
memory is dierent (NOR allows random-access for
for use as a non-volatile data storage area.
reading, NAND allows only page access)
NAND sacrices the random-access and execute-inplace advantages of NOR. NAND is best suited to sys- These two are linked by the design choices made in the
tems requiring high capacity data storage. It oers higher development of NAND ash. A goal of NAND ash dedensities, larger capacities, and lower cost. It has faster velopment was to reduce the chip area required to impleerases, sequential writes, and sequential reads.
ment a given capacity of ash memory, and thereby to
reduce cost per bit and increase maximum chip capacity
so that ash memory could compete with magnetic stor4.3 Standardization
age devices like hard disks.
NOR and NAND ash get their names from the structure of the interconnections between memory cells.[43]
In NOR ash, cells are connected in parallel to the bit
lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In
NAND ash, cells are connected in series, resembling a
NAND gate. The series connections consume less space
a standard physical interface (pinout) for NAND than parallel ones, reducing the cost of NAND ash. It
ash in TSOP48, WSOP-48, LGA52, and does not, by itself, prevent NAND cells from being read
BGA63 packages
and programmed individually.
a standard command set for reading, writing, and Each NOR ash cell is larger than a NAND ash cell
erasing NAND ash chips
10 F2 vs 4 F2 even when using exactly the same
semiconductor device fabrication and so each transistor,
a mechanism for self-identication (comparable to contact, etc. is exactly the same sizebecause NOR ash
the serial presence detection feature of SDRAM cells require a separate metal contact for each cell.[44]
memory modules)
When NOR ash was developed, it was envisioned as a
more economical and conveniently rewritable ROM than
The ONFI group is supported by major NAND ash contemporary EPROM and EEPROM memories. Thus
manufacturers, including Hynix, Intel, Micron Technol- random-access reading circuitry was necessary. Howogy, and Numonyx, as well as by major manufacturers of ever, it was expected that NOR ash ROM would be read
devices incorporating NAND ash chips.[40]
much more often than written, so the write circuitry inOne major ash device manufacturer, Toshiba, has cho- cluded was fairly slow and could only erase in a blocksen to use an interface of their own design known as Tog- wise fashion. On the other hand, applications that use
gle Mode (and now Toggle V2.0). This interface isn't ash as a replacement for disk drives do not require worddirectly, pin for pin compatible with the ONFI speci- level write address, which would only add to the complexcation. The result is a product designed for one vendors ity and cost unnecessarily.
devices, can't use other vendors devices.[41]
Because of the series connection and removal of wordA group of vendors, including Intel, Dell, and Microsoft,
formed a Non-Volatile Memory Host Controller Interface
(NVMHCI) Working Group.[42] The goal of the group is
to provide standard software and hardware programming
CAPACITY
5.1
Write endurance
7 Capacity
9.2
More recent ash drives (as of 2012) have much greater There are two major SPI ash types. The rst type is
capacities, holding 64, 128, and 256 GB.[54]
characterized by small pages and one or more internal
A joint development at Intel and Micron will allow the SRAM page buers allowing a complete page to be read
production of 32 layer 3.5 terabyte (TB) NAND ash to the buer, partially modied, and then written back
sticks and 10 TB standard-sized SSDs. The device in- (for example, the Atmel AT45 DataFlash or the Micron
cludes 5 packages of 16 x 48 GB TLC dies, using a oat- Technology Page Erase NOR Flash). The second type
has larger sectors. The smallest sectors typically found
ing gate cell design.[55]
in an SPI ash are 4 kB, but they can be as large as 64
Flash chips continue to be manufactured with capacities kB. Since the SPI ash lacks an internal SRAM buer,
under or around 1 MB, e.g., for BIOS-ROMs and embed- the complete page must be read out and modied before
ded applications.
being written back, making it slow to manage. SPI ash
is cheaper than DataFlash and is therefore a good choice
when the application is code shadowing.
Transfer rates
10
13
REFERENCES
12 See also
10
Industry
One source states that, in 2008, the ash memory industry includes about US$9.1 billion in production and sales.
Other sources put the ash memory market at a size of
more than US$20 billion in 2006, accounting for more
than eight percent of the overall semiconductor market
and more than 34 percent of the total semiconductor
memory market.[64] In 2012, the market was estimated
at $26.8 billion.[65]
13 References
[1] A Flash Storage Technical and Economic Primer. ash-
11
Unsung hero.
12
13
REFERENCES
[34] Kim, Jesung; Kim, John Min; Noh, Sam H.; Min, Sang
Lyul; Cho, Yookun (May 2002). A Space-Ecient Flash
Translation Layer for CompactFlash Systems (PDF).
Proceedings of the IEEE 48 (2). pp. 366375. Retrieved
2008-08-15.
[54] http://www.pcworld.com/businesscenter/article/225370/
look_out_for_the_256gb_thumb_drive_and_the_
128gb_tablet.html; http://techcrunch.com/2009/07/20/
kingston-outs-the-first-256gb-flash-drive/ 20 July 2009,
Kingston DataTraveler 300 is 256 GB.
13
14
External links
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15.2
Images
15.3
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