CD4027BM/CD4027BC Dual J-K Master/Slave

Flip-Flop with Set and Reset

General Description

Features

These dual J-K flip-flops are monolithic complementary

MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors. Each flip-flop has
independent J, K, set, reset, and clock inputs and buffered
Q and Q outputs. These flip-flops are edge sensitive to the
clock input and change state on the positive-going transition
of the clock pulses. Set or reset is independent of the clock
and is accomplished by a high level on the respective input.
All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS.

Y
Y
Y

Y
Y

Wide supply voltage range

High noise immunity
Low power TTL
compatibility
Low power
Medium speed operation

3.0V to 15V
0.45 VDD (typ.)
Fan out of 2 driving 74L
or 1 driving 74LS
50 nW (typ.)
12 MHz (typ.)
with 10V supply

Schematic and Connection Diagrams

TL/F/5958 1

Dual-In-Line Package

Order Number CD4027B

TL/F/5958 2

Top View

C1995 National Semiconductor Corporation

TL/F/5958

RRD-B30M105/Printed in U. S. A.

CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

February 1988

Absolute Maximum Ratings

Recommended Operating
Conditions (Note 2)

(Note 1 and 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

DC Supply Voltage (VDD)

Input Voltage (VIN)
Operating Temperature Range (TA)
CD4027BM
CD4027BC

b 0.5 VDC to a 18 VDC

DC Supply Voltage (VDD)
b 0.5V to VDD a 0.5 VDC
Input Voltage (VIN)
b 65 C to a 150 C
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)
260 C

3V to 15 VDC
0V to VDD VDC
b 55 C to a 125 C
b 40 C to a 85 C

DC Electrical Characteristics CD4027BM (Note 2)

Symbol

Parameter

b 55 C

Conditions

Min

Max

a 25 C

Min

IDD

Quiescent Device Current VDD e 5V, VIN e VDD or VSS

VDD e 10V, VIN e VDD or VSS
VDD e 15V, VIN e VDD or VSS

VOL

Low Level
Output Voltage

lIOl k 1 mA
VDD e 5V
VDD e 10V
VDD e 15V

High Level
Output Voltage

lIOl k 1 mA
VDD e 5V
VDD e 10V
VDD e 15V

VIL

Low Level
Input Voltage

VDD e 5V, VO e 0.5V or 4.5V

VDD e 10V, VO e 1V or 9V
VDD e 15V, VO e 1.5V or 13.5V

VIH

High Level
Input Voltage

VDD e 5V, VO e 0.5V or 4.5V

VDD e 10V, VO e 1V or 9V
VDD e 15V, VO e 1.5V or 13.5V

3.5
7.0
11.0

3.5
7.0
11.0

IOL

Low Level Output

Current (Note 3)

VDD e 5V, VO e 0.4V

VDD e 10V, VO e 0.5V
VDD e 15V, VO e 1.5V

0.64
1.6
4.2

0.51
1.3
3.4

IOH

High Level Output

Current (Note 3)

VDD e 5V, VO e 4.6V

VDD e 10V, VO e 9.5V
VDD e 15V, VO e 13.5V

b 0.64
b 1.6
b 4.2

b 0.51
b 1.3
b 3.4

IIN

Input Current

VDD e 15V, VIN e 0V

VDD e 15V, VIN e 15V

VOH

Typ

1
2
4
0.05
0.05
0.05
4.95
9.95
14.95

0
0
0
4.95
9.95
14.95

0.1

Max

Min

Units

Max

1
2
4

30
60
120

mA
mA
mA

0.05
0.05
0.05

0.05
0.05
0.05

V
V
V

5
10
15

1.5
3.0
4.0

b 0.1

a 125 C

4.95
9.95
14.95
1.5
3.0
4.0

V
V
V
1.5
3.0
4.0

V
V
V

3.5
7.0
11.0

V
V
V

0.88
2.25
8.8

0.36
0.9
2.4

mA
mA
mA

b 0.88
b 2.25
b 8.8

b 0.36
b 0.9
b 2.4

mA
mA
mA

b 10 b 5 b 0.1

10b5

0.1

b 1.0

1.0

mA
mA

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides conditions for actual device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.

DC Electrical Characteristics CD4027BC (Note 2)

Symbol

Parameter

b 40 C

Conditions

Min

Max

a 25 C

Min

IDD

Quiescent Device Current VDD e 5V, VIN e VDD or VSS

VDD e 10V, VIN e VDD or VSS
VDD e 15V, VIN e VDD or VSS

VOL

Low Level
Output Voltage

lIOl k 1 mA
VDD e 5V
VDD e 10V
VDD e 15V

High Level
Output Voltage

lIOl k 1 mA
VDD e 5V
VDD e 10V
VDD e 15V

VIL

Low Level
Input Voltage

VDD e 5V, VO e 0.5V or 4.5V

VDD e 10V, VO e 1V or 9V
VDD e 15V, VO e 1.5V or 13.5V

VIH

High Level
Input Voltage

VDD e 5V, VO e 0.5V or 4.5V

VDD e 10V, VO e 1V or 9V
VDD e 15V, VO e 1.5V or 13.5V

3.5
7.0
11.0

3.5
7.0
11.0

IOL

Low Level Output

Current (Note 3)

VDD e 5V, VO e 0.4V

VDD e 10V, VO e 0.5V
VDD e 15V, VO e 1.5V

0.52
1.3
3.6

0.44
1.1
3.0

IOH

High Level Output

Current (Note 3)

VDD e 5V, VO e 4.6V

VDD e 10V, VO e 9.5V
VDD e 15V, VO e 13.5V

b 0.52
b 1.3
b 3.6

b 0.44
b 1.1
b 3.0

IIN

Input Current

VDD e 15V, VIN e 0V

VDD e 15V, VIN e 15V

VOH

Typ

4
8
16
0.05
0.05
0.05
4.95
9.95
14.95

0
0
0
4.95
9.95
14.95

0.3

Max

Min

Units

Max

4
8
16

30
60
120

mA
mA
mA

0.05
0.05
0.05

0.05
0.05
0.05

V
V
V

5
10
15

1.5
3.0
4.0

b 0.3

a 85 C

4.95
9.95
14.95
1.5
3.0
4.0

V
V
V
1.5
3.0
4.0

V
V
V

3.5
7.0
11.0

V
V
V

0.88
2.25
8.8

0.36
0.9
2.4

mA
mA
mA

b 0.88
b 2.25
b 8.8

b 0.36
b 0.9
b 2.4

mA
mA
mA

b 10 b 5 b 0.3

10b5

0.3

b 1.0

1.0

mA
mA

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides conditions for actual device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.

AC Electrical Characteristics* TA e 25 C, CL e 50 pF, trCL e tfCL e 20 ns, unless otherwise specified

Typ

Max

Units

tPHL or tPLH

Symbol

Propagation Delay Time

from Clock to Q or Q

Parameter

VDD e 5V
VDD e 10V
VDD e 15V

Conditions

Min

200
80
65

400
160
130

ns
ns
ns

tPHL or tPLH

Propagation Delay Time

from Set to Q or Reset to Q

VDD e 5V
VDD e 10V
VDD e 15V

170
70
55

340
140
110

ns
ns
ns

tPHL or tPLH

Propagation Delay Time

from Set to Q or
Reset to Q

VDD e 5V
VDD e 10V
VDD e 15V

110
50
40

220
100
80

ns
ns
ns

tS

Minimum Data Setup Time

VDD e 5V
VDD e 10V
VDD e 15V

135
55
45

270
110
90

ns
ns
ns

tTHL or tTLH

Transition Time

VDD e 5V
VDD e 10V
VDD e 15V

100
50
40

200
100
80

ns
ns
ns

fCL

Maximum Clock Frequency

(Toggle Mode)

VDD e 5V
VDD e 10V
VDD e 15V

2.5
6.2
7.6

trCL or tfCL

Maximum Clock Rise

and Fall Time

VDD e 5V
VDD e 10V
VDD e 15V

15
10
5

tW

Minimum Clock Pulse

Width (tWH e tWL)

VDD e 5V
VDD e 10V
VDD e 15V

100
40
32

200
80
65

ns
ns
ns

tWH

Minimum Set and

Reset Pulse Width

VDD e 5V
VDD e 10V
VDD e 15V

80
30
25

160
60
50

ns
ns
ns

CIN

Average Input Capacitance

Any Input

7.5

pF

CPD

Power Dissipation Capacity

Per Flip-Flop
(Note 4)

35

5
12.5
15.5

MHz
MHz
MHz
ms
ms
ms

pF

*AC Parameters are guaranteed by DC correlated testing.

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the
devices should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides conditions for actual
device operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics application
note, AN-90.

Typical Applications
Ripple Binary Counters

TL/F/5958 3

Shift Registers

TL/F/5958 4

Truth Table
X t Outputs
n

# tnb1 Inputs
CL U

L
L
L
L
K
X
X
X

I
X
O
X
X
X
X
X

X
O
X
I
X
X
X
X

O
O
O
O
O
I
O
I

O
O
O
O
O
O
I
I

O
I
O
I
X
X
X
X

I
I
O
O

O
O
I
I
(No Change)
O
I
I

Where:

I e High Level
O e Low Level
U e Level Change
X e Dont Care
# e tnb1 refers to the time interval prior to the positive clock pulse transition
X e tn refers to the time intervals after the positive clock pulse transition

I
O
I

CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4027BMJ or CD4027BCJ
NS Package Number J16A

Molded Dual-In-Line Package (N)

Order Number CD4027BMN or CD4027BCN
NS Package Number N16E
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