Professional Documents
Culture Documents
TM
CONFERENCE
PROGRAM
TABLE OF CONTENTS
GENERAL CHAIRS WELCOME..................................................4
Conference Sponsor..................................................................................... 5
Conference Details....................................................................................... 6
DVCon India 2016 Committees.................................................................. 8
Keynotes...................................................................................................... 11
THURSDAY AGENDA................................................................ 12
Thursday Session Details.......................................................................... 14
FRIDAY AGENDA....................................................................... 28
Friday Session Details................................................................................ 30
GAURAV JALAN
General Chair - Aricent
I am pleased to welcome you all to the 3rd edition of DVCon India planned for 15-16, September 2016 at the Leela
Palace Hotel, Bangalore.
DVCon India is a must attend conference dedicated to design and verification of IPs, SoCs and electronic systems. The
conference provides an excellent platform for attendees to discuss, network and contribute to the standards, flows and
methodologies enabling silicon product realization. Following the grand success of DVCon US, the Indian edition of this
conference has been receiving overwhelming response for the last two years.
Today, the semiconductor industry is experiencing a major change in its landscape. Post the PC & mobile era, all eyes
are on IoT which is an ecosystem of interconnected devices that are high on performance, low on power consumption,
cheap and highly customized to the end user expectations. This requires a paradigm shift in how we design and
develop designs enabling first silicon success faster than ever before. Starting from the concept exploration at the
system level and bringing it down to the IPs interconnected on the SoC, DVCon India touches different aspects of
design and verification. The discussions and information exchange covers a wide variety of topics, representing the
latest developments and future trends in this domain.
The committee has worked relentlessly to come up with a 2 day packed agenda covering keynotes from industry
luminaries, tutorials from the gurus, panel discussions with experts, papers and posters from the fraternity. Attendees
are free to choose between ESL and DV track based on the topics of interest and learn further from whats next at the
exhibitor stalls. Both the days provide multiple opportunities to network and connect with the peers in the industry.
The technical sessions are spiced up with a lot of fun at the gala dinner on DAY 1. With a track record of more than 600
experts, representing 80+ organizations from all over the world, DVCon India is a unique conference for all members of
the semiconductor ecosystem.
I am looking forward to meet you and join hands to connect, contribute and celebrate at DVCon India 2016!
CONFERENCE SPONSOR
TM
System, software, and semiconductor design are converging to meet the increasing challenges to create complex integrated
circuits and system on chips. This convergence has brought to the forefront the need for a single organization to facilitate the
creation of system-level, semiconductor design, and verification standards. Leading industry standards associations Accellera
Organization Inc. and the Open SystemC Initiative (OSCI) merged in 2011 to form a single organization, Accellera Systems Initiative,
to address the needs of the system and semiconductor designers who must find new and smarter ways to create and produce
increasingly complex chips. The new organization will evolve to create more comprehensive standards that benefit the global
electronic design community.
Membership
Accellera members directly influence development of the most important and widely used standards in electronic design. Member
companies protect and leverage their investment in design languages through their funding of a proven, effective and responsible
organization. In addition, our members have a higher level of visibility in the EDA industry as active participants in Accellerasponsored activities and as contributors to its decisions, which impact the EDA industry. For a full list of technical activities that
are supported by Accellera, and for information on how to join us, please visit our website at www.accellera.org.
CONFERENCE DETAILS
REGISTRATION HOURS
Location: Foyer Area Next to the Grand Staircase
Thursday, September 15 ------ 8:00am 6:30pm
Friday, September 16---------- 8:00am 6:00pm
Thank You to Our Sponsors:
EXPO HOURS
Location: Pre-Function Area Mezzanine Level
Thursday, September 15 ------ 11:00am - 6:30pm
Friday, September 16---------- 11:00am - 4:00pm
GALA DINNER
Thursday, September 15, 7:15 - 9:00pm | Location: Royal Ballroom
Wrap up a great day of sessions by networking with fellow conference attendees while enjoying drinks and
a buffet dinner.
CONFERENCE DETAILS
TEA BREAKS & EXHIBITS NETWORKING
Enjoy a tea break while you mingle with DVCon Indias exhibitors, located in hallways throughout the
conference area.
Friday, September 16
11:00 - 11:30am | Location: Pre-Function Area
Mezzanine Level
3:30 - 4:00pm | Location: Pre-Function Area
Mezzanine Level
Thursday, September 15
11:00 - 11:30am | Location: Pre-Function Area
Mezzanine Level
3:30 - 4:00pm | Location: Pre-Function Area
Mezzanine Level
5:30 - 6:15pm | Location: Grand Ballroom/
Pre-Function Area Mezzanine Level
AWARDS PRESENTATION
Friday, September 16, 5:30 to 6:15pm | Location: Grand Ballroom
Join us to close the conference with an awards ceremony, featuring the 2016 Best Paper and Best Poster
award winners and more!
2016 COMMITTEES
STEERING COMMITTEE
GENERAL CHAIR
Gaurav Jalan
Aricent
gaurav.jalan@aricent.com
ESL/TPC CHAIR
DV/TPC CHAIR
Pushkar Naik
Applied Micro
pnaik@apm.com
Swaminathan Ramachandran
CircuitSutra Technologies Pvt Ltd.
swaminathan.ramachandran@
circuitsutra.com
TUTORIAL CHAIR
TUTORIAL CO-CHAIR
(ESL)
PROMOTIONS CHAIR
PROMOTIONS CO-CHAIR
CONFERENCE &
EXHIBITION CHAIR
FINANCE CHAIR
PAST CHAIR
ACCELLERA LIAISON
ACCELLERA
REPRESENTATIVE
& DVCON US
IEEE LIAISON
CONFERENCE
MANAGEMENT
CONFERENCE
MANAGEMENT
DV/TPC CO-CHAIR
Srivatsa Vasudevan
Synopsys, Inc.
Srivatsa.Vasudevan@
synopsys.com
Bishnupriya Bhattacharya
Cadence Design Systems, Inc.
bpriya@cadence.com
Samuel V. Dorairaj
Intel Corp.
Samuel.v.dorairaj@intel.com
Dennis Brophy
Mentor Graphics Corp.
Dennis_brophy@mentor.com
Kevin Lepine
MP Associates
Kevin@MPAssociates.com
Anupam Bakshi
Agnisys, Inc.
anupam@agnisys.com
Lynn Bannister-Garibaldi
Accellera Systems Initiative
lynn@accellera.org
Yatin Trivedi
Synopsys, Inc.
ytrivedi@yahoo.com
Nannette Jordan
MP Associates.
Nannette@MPAssociates.com
Pradeep Salla
Mentor Graphics Corp.
pradeep_salla@mentor.com
Tom Anderson
Breker Verification Systems, Inc.
toma@brekersystems.com
Ajeetha Kumari
CVC Pvt. Ltd.
akumari@cvcblr.com
Sri Chandra
IEEE
Sri.chandra@ieee.org
2016 COMMITTEES
ADVISORY COMMITTEE
Umesh Sisodia
CircuitSutra Technologies Pvt Ltd.
usisodia@circuitsutra.com
Srinivasan Venkataramanan
CVC Pvt. Ltd.
srini@cvcblr.com
Saurabh Tiwari
Intel Corp.
Saurabh.tiwari@intel.com
Veeresh Shetty
Mentor Graphics Corp.
Veeresh_shetty@mentor.com
DV/TPC CHAIR
Srivatsa Vasudevan
Synopsys, Inc.
Srivatsa.Vasudevan@
synopsys.com
Pushkar Naik
Applied Micro
pnaik@apm.com
Amit Agarwal
NVIDIA Corp.
Anil Keste
Seagate Technology, LLC
Lisa Piper
Real Intent, Inc.
Mike Bartley
Test and Verification Solutions
Neyaz Khan
Maxim Integrated
Logie Ramachandran
VeriKwest Systems Inc.
Sundaresan Chidambaram
Manipal Univ.
Thorsten Klose
Infineon Technologies AG
Pradeep Salla
Mentor Graphics Corp.
Manu Chopra
Cadence Design Systems, Inc.
Ajeetha Kumari
CVC Pvt., Ltd.
Ambar Sarkar
eInfochips Ltd.
Deepak Gupta
Synapse Design
Sean Smith
Soft Machines
Sundararajan Haran
Microsemi Corp.
Paul Marriot
Verilab, Inc.
Palaniappan Somasundaram
ARM, Inc.
Gaurav Jalan
Aricent
Mike Mintz
Trusster, Inc.
Ranganath Kempanahally
elitePLUS Semiconductors Technologies
Rama Namburi
Cannon India Pvt. Ltd.
Srinivasan Venkataramanan
CVC Pvt., Ltd.
Prasanna Kesavan
Broadcom Corp.
Kunal Panchal
Applied Micro
Viba Viswanathan
Centaur Technology
2016 COMMITTEES
ESL TECHNICAL PROGRAM COMMITTEE
ESL/TPC CHAIR
Swaminathan Ramachandran
CircuitSutra Technologies Pvt Ltd.
swaminathan.ramachandran@
circuitsutra.com
Ashwani Aggarwal
Canon India Pvt. Ltd.
Chetan Nayak
Infineon Technologies AG
Anupam Bakshi
Agnisys, Inc.
Murali Krishnan
Qualcomm, Inc.
Mark Burton
GreenSocs Ltd.
Anoop Kumar
Qualcomm, Inc.
Melwyn Scudder
Intel Mobile Communication
Amit Garg
Synopsys, Inc.
Manish Makkar
SanDisk Corp.
Dinesh Selvaraj
Infineon Technologies India Pvt. Ltd
Karthick Gururaj
Vayavya Labs Pvt., Ltd.
Saurabh Tiwari
Intel Corp.
Sandeep Jain
NXP Semiconductors
Abhilash Nair
NVIDIA Corporation
Vikas Tyagi
Mentor Graphics Corp.
PROMOTIONS COMMITTEE
PROMOTIONS CHAIR
PROMOTIONS CO-CHAIR
Anupam Bakshi
Agnisys, Inc.
anupam@agnisys.com
Tom Anderson
Breker Verification Systems, Inc.
toma@brekersystems.com
Barun Kumar De
Aricent
Madhavi Rao
Cadence Design Systems, Inc.
Ajeetha Kumari
CVC
Amarnatha Reddy
CircuitSutra Technologies Pvt Ltd.
Gaurav Jalan
Aricent
Girish Nanappa
Synopsys, Inc.
Praveen Wadikar
NVIDIA Corporation
Prasanna Kesavan
Broadcom Corp.
10
KEYNOTES
THURSDAY, SEPTEMBER 15
DESIGN VERIFICATION: CHALLENGING
YESTERDAY, TODAY AND TOMORROW
Thank You to
Our Sponsor:
Thank You to
Our Sponsor:
FRIDAY, SEPTEMBER 16
TODAYS SOC VERIFICATION
CHALLENGES: MOBILE AND BEYOND
Sushil Gupta - Synopsys, Inc.
11
Thank You to
Our Sponsor:
THURSDAYS AGENDA
9:30 9:45am
DVCon
India
2016
Expo
Exhibit
Hours
11:00am6:30pm
DVCon
India
2016
Expo
9:45 10:30am
10:30 11:00am
11:00 11:30am
11:30am 12:10pm
12:10 1:00pm
ESL Invited Panel: An Entry Level Vehicle for IoT Market Space | Room:
1:00 2:00pm
2:00 3:30pm
3:30 4:00pm
4:00 5:30pm
Thank You to
Our Sponsor:
TM
Thank You to
Our Sponsor:
5:30 6:15pm
6:15 7:15pm
7:15 9:00pm
THURSDAYS AGENDA
Tomorrow | Walden Rhines - Mentor Graphics Corp. | Room: Grand Ballroom
Thank You to
Our Sponsor:
by RISE Group, IIT Madras | Kamakoti Veezhinathan - Indian Institute of Technology Madras
ine Level
Thank You to
Our Sponsor:
Royal Ballroom
DV Tutorial: Advanced
Validation and Functional
Verification Techniques for
Complex Low Power
System-on-Chips
Room: Diya
Thank You to
Our Sponsor:
Thank You to
Our Sponsor:
ine Level
DV Tutorial: An Industry
Proven UVM Reuse
Methodology for Coverage
Driven Block Level Verification
to Software Driven Chip Level
Verification Across Simulation
and Emulation
Room: Grand Ballroom
Thank You to
Our Sponsor:
DV Tutorial: Thinking
Ahead - Advanced
Verification and Debug
Techniques for the Imminent
IoT Wave
Room: Sitara
Thank You to
Our Sponsor:
Thank You to
Our Sponsor:
13
THURSDAY, SEPTEMBER 15
Thank You to
Our Sponsor:
14
THURSDAY, SEPTEMBER 15
THURSDAY, SEPTEMBER 15
Speakers:
Subrangshu Das - Canon India Pvt. Ltd.
16
THURSDAY, SEPTEMBER 15
Speakers:
Alok Jain - Cadence Design Systems, Inc.
Thank You to
Our Sponsor:
ESL Invited Panel: An Entry Level Vehicle for IoT Market Space
Time: 12:10pm - 1:00pm | Room: Royal Ballroom
Moderator:
Dineshkumar Selvaraj - Infineon Technologies India
Pvt. Ltd
IoT is one of the hottest buzzword in the technology arena
and is projected to be the next big wave of technology
revolution. ESL has long promised to be an evangelization
vehicle for rapid prototyping, early exploration and speedier
exploration. The focus of the panel discussion is to present
and brainstorm on how the ESL promise can be applied to
enable IoT market to foster Innovation and Development to
create next generation of market and technology leaders in
the industry.
17
THURSDAY, SEPTEMBER 15
Thank You to
Our Sponsor:
Lunch Break
Time: 1:00pm - 2:00pm | Room: Pre-Function Area Mezzanine Level
Take time to network and mingle with other conference
attendees while enjoying a buffet lunch.
EVENING ENTERTAINMENT
AND NETWORKING
After sessions close at 5:30pm on Thursday, look forward to an evening of excellent
networking and entertainment from stand-up comedian Praveen Kumar, followed by
a dinner buffet and drinks. Be sure to stop by and visit DVCon Indias many interesting
exhibitors, located throughout the conference hallways, before exhibits close at 6:30pm!
18
THURSDAY, SEPTEMBER 15
Speaker:
Sandeep Dager - Mentor Graphics (India) Pvt. Ltd.
Thank You to
Our Sponsor:
19
THURSDAY, SEPTEMBER 15
Organizer:
Larry Melling - Accellera Systems Initiative
Portability of reusable test cases has long been a goal for
semiconductor verification and validation teams. No one
wants to reinvent the wheel by having to rewrite similar
tests again and again. The widely accepted Accellera
Universal Verification Methodology (UVM) standard enabled
reuse of testbench components and constrained-random tests
at the IP (block) level, but limitations in terms of reuse at
subsystem and full-chip level, and lack of portability across
execution platforms, required a fresh look at addressing the
portable stimulus and test challenge. The upcoming Accellera
portable test and stimulus standard (PSS) specification will
permit the creation of a reusable model for a variety of
users across different levels of integration under different
configurations. This model will enable the generation of
different test implementations for multiple execution
platforms, including IP simulation, full system-on-chip (SoC)
simulation, emulation, FPGA prototyping, and silicon. With
such a standard in place, EDA vendors can produce tools that
automatically generate stimulus, results checks, and coverage
metrics tuned for a particular target platform. This tutorial
will examine unique portable stimulus challenges such as
linking verification to diagnostics and software, portability
to every platform, and resource management. The tutorial
outlines a set of common usage examples that emphasize
specific verification, reuse, and portability challenges.
Verification challenges include randomization of both data
and control flow. Reuse challenges include migrating tests
from IP level to SoC. Portability challenges include growing
tests to improve coverage when running on faster platforms
and executing at the full platform speed. Finally, the tutorial
will show how portable stimulus can address the usage
examples.
Thank You to
Our Sponsor:
TM
20
THURSDAY, SEPTEMBER 15
Thank You to
Our Sponsor:
Speakers:
Srikanth Nuni - Mentor Graphics (India) Pvt. Ltd.
Praveen Shukla - Mentor Graphics (India) Pvt. Ltd.
Thank You to
Our Sponsor:
21
THURSDAY, SEPTEMBER 15
Speakers:
Praveen Tiwari - Cadence Design Systems, Inc.
Vijay Birange - Cadence Design Systems, Inc.
Thank You to
Our Sponsor:
22
THURSDAY, SEPTEMBER 15
Speakers:
Praveen Tiwari - Cadence Design Systems, Inc.
Thank You to
Our Sponsor:
23
THURSDAY, SEPTEMBER 15
Thank You to
Our Sponsor:
24
Speakers:
Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.
Keshav Joshi - Mentor Graphics (India) Pvt. Ltd.
Thank You to
Our Sponsor:
THURSDAY, SEPTEMBER 15
Thank You to
Our Sponsor:
LOOKING FOR DV OR
ESL CONTENT?
If youre looking for DV or ESL content, youre in the right place! A navigation tip
DV Track sessions are located in the Grand Ballroom, Diya Room, and Sitara Room,
while attendees with an ESL focus should head toward the Royal Ballroom and
Kamal Room for ESL Track content.
25
THURSDAY, SEPTEMBER 15
Speakers:
Vamsi Krishna Doppalapudi - Synopsys, Inc.
Thank You to
Our Sponsor:
Evening Entertainment
Time: 6:15pm - 7:15pm | Room: Grand Ballroom
Meet up with other conference attendees
after a full days program for an update
on whats new at Accellera, followed
by evening entertainment from Praveen Kumar,
stand-up comedian.
join us in europe!
2016
TM
FRIDAYS AGENDA
9:30 9:45am
DVCon
India
2016
Expo
Exhibit
Hours
11:00am4:00pm
9:45 10:30am
10:30 11:00am
11:00 11:30am
11:00am 5:30pm
Tea
and
Exhibits
Networking
| Room:
Hallway
ESL Break
Posters
| Room:
Pre-Function
Area
Mezzanine
Level
11:00am 5:30pm
Tea
Break and
Exhibits
Networking
Room: Hallway
DV Posters
| Room:
Pre-Function
Area| Mezzanine
Level
11:30am 1:00pm
1:00 2:00pm
DVCon
India
2016
Expo
Opening
Opening Talks
Talks || Room:
Room: Grand
Grand Ballroom
Ballroom
2:00 3:30pm
Tea
Break
and
Exhibits
Networking
| Room:
Hallway
Lunch
Break
| Room:
Pre-Function
Area
Mezzanine
Level
ESL Papers: ESL Power &
Energy Modeling
3:30 4:00pm
4:00 5:30pm
5:30 6:15pm
Tea
Break
and Exhibits
Networking
| Room:
Hallway
Closing
Ceremony
and Awards
| Room:
Grand
Ballroom
28
FRIDAYS AGENDA
Thank You to
Our Sponsor:
ine Level
Room: Diya
Room: Sitara
DV Papers: Topics in
Assertions and Formal
Verification
Room: Diya
Room: Sitara
ine Level
Room: Diya
29
Room: Sitara
FRIDAY, SEPTEMBER 16
Opening Talks
Time: 9:30am - 9:45am | Room: Grand Ballroom
Join us as we re-open the conference on Friday, looking
forward to an interesting schedule of keynotes, an invited
tutorial, posters, and the technical paper sessions.
Thank You to
Our Sponsor:
Invited Keynote
Time: 10:30am - 11:00am | Room: Grand Ballroom
30
FRIDAY, SEPTEMBER 16
ESL Posters
Time: 11:00am - 5:30pm | Room: Pre-Function Area Mezzanine Level
14.1 A
Hardware Efficient Reduced Latency
Architecture for Configurable Mixed-Radix
FFT Processor
Sandeep Dager - Mentor Graphics (India) Pvt. Ltd. & Mentor
Graphics Corp.
Vikas Tyagi, Vishal Sinha- Mentor Graphics (India)
Pvt. Ltd.
DV Posters
Time: 11:00am - 5:30pm | Room: Pre-Function Area Mezzanine Level
15.1 M
ethodology to combine Formal and fault
simulator to measure safety metrics
Ranga Kadambi, Holger Busch, Kirankumar
Bandlamudi, Gaurav Jain - Infineon Technologies AG
15.6 H
idden gems of UVM Base Class Library debug techniques for UVM users
Pranesh Sairam A, Azhar Ahammad, Arun P C - CVC
Pvt., Ltd.
15.2 P
re-Silicon Power Management Verification
of Complex SOCs: Experiences with Intel
Moorefield
Rajeev Muralidhar, Nivedha Krishnakumar,
Bryan Morgan, Neil Rosenberg - Intel Corp.
15.3 S
calable and Configurable Automated
Interrupt Verification Approach
Chethan D. Narayana Murthy - Infinera India Pvt Ltd
15.4 C
ode Coverage on System Verilog Testbench
as a Verification Signoff metric
Ponnambalam Lakshmanan, Kunal Jani - Analog Devices,
Inc.
Swati Ramachandran - Cadence Design Systems, Inc.
15.5 I mplementing a Reusable, Auto Configurable
Functional Coverage Model
Santosh Moharana - Synopsys, Inc. & Synopsys India Pvt.
Ltd.
31
FRIDAY, SEPTEMBER 16
Chair:
1.2
1.3
Chair:
32
2.2
2.3
FRIDAY, SEPTEMBER 16
3.1
3.2
3.3
Lunch Break
Time: 1:00pm - 2:00pm | Room: Pre-Function Area Mezzanine Level
Take time to network and mingle with other conference
attendees while enjoying a buffet lunch. Exhibits will be open
throughout the conference area, so be sure to stop by the
booths and see whats new.
33
FRIDAY, SEPTEMBER 16
Chair:
4.2
5.2
5.3
Chair:
6.3
34
FRIDAY, SEPTEMBER 16
7.1
7.2
7.3
8.2
8.3
FRIDAY, SEPTEMBER 16
9.2
9.3
Chair:
10.3 R
un-time Elaboration and Dynamic
Configuration of Virtual Platform
Rajesh Jain, Sandeep Jain - NXP Semiconductors
Chair:
11.2 T
aking UVM to wider user base the opensource way
Nagasundaram Thillaivasagam, Gurubasappa Kinagi,
SanthoshKumar Mathavan - CVC Pvt., Ltd.
11.3 V
erification challenges with parameterized IP
generators in UVM
Arpita Jain, Rajdeep Mondal, Surabhi S. Gujar,
Karan Gupta, Sandesh Panchaksharaiah, Shaloob K P
- NVIDIA Corporation
36
FRIDAY, SEPTEMBER 16
12.3 N
ot Just one, 3 Ways to bring down the
simulation turnaround time for SoC level
assertion qualification
Sachin Scaria - Graphene Semiconductor
Sreenu Yerabolu - Intel Corp.
12.1 D
emocratizing FPV: Arbiters and FSM FV
- An Intel Graphics Experience
Achutha Kiran Kumar V. Madhunapantula, Aarti
Gupta, Bindumadhava S. Singanamalli - Intel Corp.
Abhijith A. Bharadwaj - Intel Technology India Pvt. Ltd
13.2 B
ridging the gap between Ideality and
Actuality in DV
Rupinjeet Singh, Mohammed Arif, Prashantkumar
Sonavane, Rithin A N - Texas Instruments India Pvt. Ltd.
13.3 D
esign for Verification: An essential
ingredient of the Left Shift Paradigm
Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.
Vishal Agarwal - Marvell Semiconductor, Inc.
37
JOIN US
in China
FOR 2017
2017
china
TM
GOLD SPONSORS
SILVER SPONSOR
REGISTRATION
MEDIA SPONSOR
39
DVCON EXPO
Join us for the DVCon 2016 Expo! Location: Pre-Function Area Mezzanine Level.
Doulos.................................................. 309
Magillem-Chipware........................... 406
EXHIBITOR FLOORPLAN
PROMENADE
105
Coffee / Lunch
GRAND
STAIR
106
PROMENADE
DN
WOMEN
S1
LIFT
MEETING ROOM'D'
203
201
UP
MEN
MEETING
S2
LIFT
200
Technical
Sessions
202
TERRACE
MEETING
MEETING ROOM'E'
G1
Technical
Sessions
G2
DN
TERRACE
Technical
Sessions
TO MEETING ROOMS
STAIR CASE
B1
GUEST
LIFT LOBBY
G3
G4
DVCON EXPO
Exhibit Hours:
TRUECHIP............................................ 106
UP
UP
GRAND
STAIR
306
307
308
309
310
403
Technical
Sessions
311
WOMEN
404
402
406
405
400
MEN
DN
UP
UP
PROMENADE
DN
Technical Sessions
Opening Session
Keynote
DN
DVCON EXPO
EXHIBITOR DETAILS
Aceic Design
Technologies
Pvt. Ltd.
Dassault
Systemes-Chipware
Booth: 404
www.3ds.com
Booth: 403
www.aceic.com
Magillem-Chipware
Booth: 406
www.magillem.com
Magillem are leading provider of
IP-Xact xml-based front-end design
and content assembly software,
renown for best-in-class tools to reduce the global cost of complex
semiconductor realization.
Breker Verification
Systems
Booth: 405
www.brekersystems.com
Breker Verification Systems is the
leader in portable stimulus. From a C++ graph-based model, you can
automatically generate test cases to run on your SoC design in every
verification platform, from high-level simulation to actual silicon
in your bring-up lab. Brekers Trek family of products tackles your
toughest verification challenges, including
cache coherency, multi-IP scenarios, and realistic performance
measurements.
Cadence Design
Systems, Inc.
www.cadence.com
Booth: 307
NEC Technologies
Booth: 310
www.nectechnologies.in
Established in 1899, NEC
corporation, is a Japanese multinational provider of information
technology(IT) services and products.
Doulos
Booth: 309
https://www.doulos.com
With over 30 years of research in the EDA area, NEC came up with
High Level Synthesis Tool CyberWorkBench.
42
DVCON EXPO
EXHIBITOR DETAILS
Real Intent, Inc.
Booth: 203
www.realintent.com
Booth: 308
testandverification.com
SeviTech Systems
Pvt. Ltd.
TRUECHIP
Booth: 106
www.truechip.net
Booth: 200
sevitechsystems.com
Verific Design
Automation
SmartDV
Technologies
Booth: 311
www.verific.com
Booth: 306
www.smart-dv.com
Synopsys, Inc.
Booth: 400
www.synopsys.com
Synopsys is the Silicon to Software partner for innovative
companies developing the electronic products and software
applications we rely on every day. Whether youre designing
advanced semiconductors or developing software that requires the
highest quality and security, Synopsys has the EDA, semiconductor
IP and software integrity solutions needed to deliver smarter, more
secure products. Learn more at www.synopsys.com.
43
DVCON EXPO
EXHIBITING COMPANIES
2017
TM
UNITED STATES
join us for
dvcon u.s.
NOTES
NOTES