Digital Communication Lab

EC 5106: DIGITAL COMMUNICATION LABORATORY
LIST OF EXPERIMENTS:
COMPULSORY EXPERIMENTS:
1) Signal sampling and reconstruction using DCL 01 Falcon kit and investigation of
i) The effect of sampling frequency variation
ii) Change of duty cycle
iii) Output at Second Order LP Butterworth filter
iv) Output at Fourth order LP Butterworth filter
2) Investigation of TDM system using DCL02 Falcon kit
3) Investigation of practical PCM system using DCL03 and DCL04 Falcon kit
4) i) Investigation of Delta Modulation system using DCL07 Falcon kit
ii) Investigation of Adaptive Delta modulation system using DCL07 Falcon kit
5) Carrier modulation/demodulation ASK, FSK, PSK.
i) Data conditioning and carrier modulation transmitter using DCL 05 Falcon
kit
ii) Data reconditioning and carrier demodulation transmitter using DCL 05
Falcon kit
6) Investigation of QAM modulation and demodulation using ST 2112 QAM trainer
kit
7) Investigation of QPSK modulation and demodulation using ST 2112 QAM trainer
kit
8) Generation of frame and marker in Time division Multiplexing.
9) i) Calculation of Mean and Variance using Commsim under
a)
Running mode
b)
Sliding window mode
ii) Investigation of autocorrelation using Commsim

10) Design of ASK and FSK modulator/demodulator using Commsim
11) Design of PSK and QPSK modulator/demodulator using Commsim
12) Investigation of Nonlinear quantization of the Sinusoidal signal using -law and
A-law.
OPTIONAL EXPERIMENTS:
1) Design of ASK modulator and demodulator using multisim.
2) Design of FSK modulator and demodulator using multisim.
3) Design of PWM modulator and demodulator using multisim.
4) Design of PPM modulator and demodulator using multisim.
5) Investigation of PWM and PPM system using DCL 08 Falcon kit
6) Use of noise generator: model WG- 722
i) Noise signal source with four kinds of probability density function
(a) Gaussian
(b) Uniform
(c) Binomial
(d) Poisson
ii) Use of external signal source to observe the effect of noise signal
7) Investigation of Eye diagram using Commsim.
8) Investigation of Signal sampling and reconstruction using Commsim.
DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING
DIGITAL COMMUNICATION LABORATORY
LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

ON
SIGNAL SAMPLING AND RECONSTRUCTION
USING DCL 01 FALCON KIT
BIRLA INSTITUTE OF TECHNOLOGY

MESRA, RANCHI
AIM: Signal sampling and reconstruction using DCL 01 Falcon kit and
investigation of
i. The effect of sampling frequency variation
ii. Change of duty cycle
iii. Output at Second Order LP Butterworth filter
iv. Output at Fourth order LP Butterworth filter
THEORY:
The kit is used to study Analog Signal Sampling and its reconstruction. It basically
consists of functional blocks, namely Function generator, Sampling Control Logic,
Clock section, Sampling Circuitry and Filter Section.
FUNCTION GENERATOR:
This Block generates two sine wave signals of 1KHz clock to the shift register. The
serial to parallel shift register with the resistive ladder network at the output generates
1KHz and 2KHz sine waves respectively by the serial shift operation. The R-C active
filter suppresses the ripple and smoothens the sine wave. The unity gain amplifier
buffer takes care of the impedance matching between sine wave generation and
sampling circuit.
SAMPLING CONTROL LOGIC:
This unit generates two main signals used in the study of Sampling theorem, namely
the analog signals (5V pp, frequency 1KHz and 2KHz) & sampling signal of
frequency 2KHz, 4KHz, 8KHz, 16KHz, 32KHz, and 64KHz.
The 6.4 MHz Crystal Oscillator generates the 6.4 MHz clock. The decade counter
divides the frequency by 10 and the ripple counter generates the basic sampling
frequencies from 2KHz to 64KHz and the other control frequencies.
From among the various available sampling frequencies, required sampling frequency
is selected by using the frequency selectable switch. The selected sampling frequency
is indicated by means of corresponding LED.
CLOCK SECTION:
This section facilitates the user to have his choice of external or internal clock feeding
to the sampling section by using a switch (SW4).
SAMPLING CIRCUITRY:
The unit has three parts namely, Natural Sampling Circuit, Flat top Sampling Circuit,
and Sampling and Hold Circuit.
The Natural sampling section takes sine wave as analog input and samples the analog
input at the rate equal to the sampling signal.
For sample and hold circuit, the output is taken across a capacitor, which holds the
level of the samples until the next sample arrives.
For flat top sampling clock used is inverts to that of sample & hold circuit. Output of
flat top sampling circuit is pulses with flat top and top corresponds to the level of
analog signal at the instant of rising edge of the clock signal.
FILTER SECTION:
Two types of Filters are provided on board, viz., 2nd Order and 4th Order Low Pass
Butterworth Filter.
EQUIPMENTS:
Experimenter kit DCL 01.
Connecting Chords.
Power supply.
20 MHz Dual trace Oscilloscope.
NOTE: KEEP ALL THE SWITCH FAULTS (EXCEPT SWITCH 1) IN OFF
POSITION.
1)
NATURAL SAMPLING AND ITS RECONSTRUCTION.
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
Refer to the Block Diagram (Fig. 1.1) & Carry out the following connections
and switch settings.
Connect power supply in proper polarity to the kit DCL-01 & switch it on.
Connect the 1KHz, 5Vpp Sine wave signal, generated onboard, ti the BUF IN
post of the BUFFER and BUF OUT post of the BUFFER to the IN post of the
Natural Sampling block by means of the Connecting chords provided.
Connect the sampling frequency clock in the internal mode INT CLK using
switch (SW4).
Using clock selector switch (S1) select 8KHz sampling frequency.
Using switch (SW2) select 50% duty cycle.
Connect the OUT post of the Natural Sampling blocks to the input IN1 post of
the 2nd Order Low Pass Butterworth Filter and take necessary observation as
mentioned below. (Fig. 1.4)
Repeat the procedure for the 2 KHz sine wave signal as input.
OBSERVATIONS:
Observe the following waveforms in order for every setting and plot it on the paper.
a.
1 KHz analog Input waveform.
b.
Sampling frequency waveform.
c.
Natural Sampling Signal and its corresponding reconstructed output of 2nd
Order Low Pass Butterworth Filter.
SWITCH FAULTS:
Note: Keep the connection as per the procedure. Now switch corresponding fault
switch button in ON condition & observe the different effect on the output. The
faults are normally used one at a time.
1.
2.
3.
2)
Put switch 6 of SF2 in switch fault section to ON position. This will open B1 bit
from the B input 94-bit DIP switch output) of the comparator. This introduces
the faults in duty cycle section. With effect change in duty cycle will not be
observed for (10%, 40%, 50%, 80% and 90% settings).
Put switch 7 of SF2 in switch fault section to ON position. This will open the
bypass capacitor of the 2nd order low pass butterworth filter, which results in the
induction of ripples at the filter output.
Put switch 8 of SF2 in switch fault section to ON position. This removes the
capacitor (c6) used in the generation of 1KHz sine wave. Which makes the sine
wave signal very distorted. The Observation can be made on this signal by
changing the sampling frequencies and the duty cycle.
SAMPLE NAD HOLD AND ITS RECONSTRUCTION.
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
Connect power supply in proper polarity to the kit DCL-01 & switch it ON.
Connect the 1 KHz, 5Vpp sine wave signal, generated onboard, to the BUF IN
post of the BUFFER and the BUF OUT post of the BUFFER to the IN post of
the sample and hold Block by means of the Connecting chords provide.
switch (SW4).
Using clock selector switch select 8 KHz sampling frequency.
Using switch SW2 select 50% duty cycle.
Connect the OUT post of the Sample and Hold block to the input IN 1 post of
the 2nd Order Low Pass Butterworth Filter and take necessary observation as
mentioned below. (Fig. 1.5).
OBSERVATIONS:
a.
1KHz analog Input waveform.
b.
c.
Sample and hold signal and its corresponding reconstructed output of 2nd order
Low Pass Butterworth Filter.
SWITCH FAULTS:
Note: Keep the connections as per the procedure. Now switch corresponding fault
switch button in ON condition & observe the different effect on the output. The
faults are normally used one at a time.
By changing the position of the switch in the SF1 you are changing the Capacitance
value of the Sample and Hold circuit, you can find the variation accordingly at
the output of the S/H circuit.
1.
2.
3.
4.
5.
6.
3)
Put Switch 1 so SF1 in switch fault section to ON position, the capacitor C11
(10nF) is at the output of sample and hold circuit.
Put Switch 2 so SF1 in switch fault section to ON position, the capacitor C10
(1.5pF) is at the output of sample and hold circuit.
Put Switch 3 so SF1 in swicth fault section to ON position, the capacitor C9
(0.22F) is at the output of sample and hold circuit.
Put Switch 6 so SF1 in switch fault section to ON position, this will open B1 bit
from the B input (4-bit DIP switch output) of the comparator. This introduces
the fault in duty cycle section. With effect, change in duty cycle will not be
observed for (10%, 40%, 50%, 80% and 90% settings).
Put Switch 7 so SF1 in switch fault section to ON position. This will open the
bypass capacitor of the 2nd order low pass butterworth filter, which result in the
induction of ripples at the filter output.
Put switch 8 of SF2 in switch Fault section to ON position. This Removes the
capacitor (C6) used in the generation of 1 KHz sine wave. Which makes the sine
wave signal very distorted. The Observed can be made on this signal by
FLAT TOP SAMPLING AND ITS RECONSTRUCTION:
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
and switch settings
Connect the 1 KHz, 5Vpp Sine wave signal, generated onboard to the BUF IN
post of the Buffer and the BUF OUT post of the Buffer to the IN post of the
Flat Top sampling block by means of the Connecting chords provided.
switch (SW4).
Using clock selector switch S1 select 8KHz sampling frequency.
Using switch SW2 select 50% duty cycle.
Connect the OUT post of the Flat top sampling block to the input IN 1 of the 2nd
Order Low Pass Butterworth Filter and take necessary observation as mentioned
below. (Fig. 1.6).
OBSERVATION:
a.
1KHz Analog Input waveform.
b.
c.
Flat Top signal and its corresponding reconstructed output of 2nd order Low
Pass Butterworth Filter.
In this manner we observe all the three types of sampling, which can be compared
with the waveforms at the end of this experiment.
We observe that, during the ON time of Sampling frequency the analog signal is
transmitted. During the OFF time, the sample output signal drops towards zero.
Whereas for sampled and Hold output, the signal maintains the voltage level i.e. the
sample is held at least sampled value until next sample arrives. For flat top sampling
first switching portion from sample & hold signal is dropped and next switching
portion is taken as pulse output, i.e. only hold portion from sample & hold signal is
taken at flat top sampling output.
SWITCH FAULTS:
switch button in ON condition & observe the different effect on the output. The faults
are normally used one at a time.
1.
2.
3.
4.
Put switch 5 of SF2 in switch Fault section to ON position. This will open the
capacitor C12 of the Flat Top Sampling Circuit, which makes the Flat Top
sample output appears to be slant.
Put switch 6 of SF2 in switch Fault section to ON position. This will open B1
bit from the B input (4-bit DIP switch output) of the comparator. This
introduces the fault in duty cycle section. With effect, change in duty cycle
will not be observed for (10%, 40%, 50%, 80% and 90% settings).
Put switch 7 of SF2 in switch Fault section to ON position. This will open the
bypass capacitor of the 2nd order low pass butterworth filter, which results in
the induction of ripples at the filter output.
Put switch 8 of SF2 in switch Fault section to On position. This Removes the
Capacitor (C6) used in the generation of 1KHz sine wave. Which makes the
sine wave signal very distorted. The observation can be made on this signal by
CONCLUSION:
Comparing the reconstruction output of 2nd order Low Pass Butterwirth Filter for all
the three types of sampling, it is observed that the output of the sample and hold is the
best as compared to the output of natural sampling and the output of the flat top
sampling.
DEPARTMENT
OF

ON
INVESTIGATION OF TDM SYSTEM
USING DCL02 FALCON KIT

MESRA, RANCHI
AIM: Investigation of TDM system using DCL02 Falcon kit

.
THEORY:
This module basically consiste of the following sections:
a.
b.
c.
The Onboard Function Generator.

The Transmitter
The Receiver with the associated synchronization circuitry.
ONBOARD FUNCTION GENERATOR:

This basically provides four Amplitude variables each (0 5 V) synchronized sine
waves, each 250Hz, 1KHz, and 2KHz and an amplitude variable DC level (0-5V). For
the generation of sine waves please refer to circuit description manual.
TRANSMITTER:
The Transmitter Section consists of four Analog Input Signals from the Function
generator fed to the four channels of the Multiplexer where the signals fed are Time
Division Multiplexed after undergoing the sampling. The sampling process makes the
signals Pulse Amplitude Modulated. The frequencies for sampling are given from the
decoder.
RECEIVER:
The Receiver Section consists of a Demultiplexer that demultiplexes the four Rime
Division Multiplexed signals, which it receives from the transmitter. This
Demultiplexed signals are then fed to the reconstruction circuit, which is the filter
section.
The receiver timing logic is very similar to the transmitter timing logic. The
demultiplexed based on the control signals C0, C1, C2, C3 assigns the information to
the corresponding channels. The success of the demultiplexer operation is fully
dependent on how exactly, RXCH0, RXCH2, RXCH3 signals match with the
TXCH0, TXCH1, TXCH2, TXCH3 signals. Thus, to ensure the proper
demultiplexing, two dividers are reset by the RXCH0 signal, which corresponds with
the TXCH). The demultiplexed signals are then given to the corresponding
reconstruction units.
The signal reconstruction unit is a 4th order Active Low Pass Butterworth Filter
provided for each receiver channel. They filter out the sampling frequency and their
harmonics from the demultiplexed signal and recover the base band by an integrate
action. The cut-off frequency of the 4th Order Low Pass Butterworth Filter is 3.4KHz.
EQUIPMENTS:
Experimentor kit DCL-02
Connecting Chords
Power supply
20 MHz Dual trace oscilloscope.
NOTE: KEEP ALL THE SWITCH FAULTS IN ON POSITION.
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
Refer to the Block Diagram (Fig. 1) & carry out the following connections and
switch settings.
Connect 250Hz, 500Hz, 1KHz, and 2KHz sine wave signal from the Function
Generator to the multiplexer input channel CH0, CH1, CH2, CH3 by means
of the connecting chords provided.
Connect the multiplexer output TXD of the transmitter section to the
demultiplexer input RXD of the receiver section.
Connect the output of the receiver section CH0, CH1, CH2, CH3 to the IN0,
IN1, IN2, and IN3 of the filter section.
Connect the sampling clock TX CLK and channel Identification Clock
TXSYNC of the transmitter section to the corresponding RX CLK and RX
SYNC of the receiver section respectively.
Set the amplitude of the input sine wave as desired.
Take observations as mentioned below.
OBSERVATIONS:
Observe the following waveforms on oscilloscope and plot it on the paper.
a.
Input Channel Ch0, Ch1, CH2, Ch3..
b.
Channel Selection Signal.
c.
TX CLK and RX CLK.
d.
Channel Identification Signal TX SYNC And RX SYNC.
e.
Multiplexer output TXD.
f.
Demultiplexer input RXD.
g.
Demultiplexer output CH0, CH1, CH2, and CH3.
h.
Reconstruction signal OUT0, OUT1, OUT2, OUT3.
SWITCH FAULTS:
Note: Keep the connection as per the procedure. Now switch corresponding faults
1.
Put switch 1 of SF1 in Switch Fault section to ON position. This will short
circuit 250Hz & 500Hz sine waves. We will get mixing of both the signals.
2.
3.
4.
5.
Put switch 4 of SF1 in switch Fault section to ON position. This will short
MSB of ladder network used for 500Hz sine wave generation. Shape of this
sine wave changes.
Put switch 5 of SF2 in switch Fault section to ON position. This will remove
TXCH0 signal. This will remove all receiver-decoding pulses. Receiver
outputs are disturbed.
control signal of first channel in demultiplexer section. Output for channel
Zero is mixing of all signals.
bypass capacitor from filter of third channel. Distorted output at channel three.
CONCLUSION:
In this experiment, the transmitter clock and the channel identification clock (sync)
are directly linked to the receiver section. Hence transmitter and receiver are
synchronized and proper reconstruction of the signal is achieved.
DEPARTMENT
OF

ON
INVESTIGATION OF PRACTICAL PCM SYSTEM
USING DCL03 AND DCL04 FALCON KIT

MESRA, RANCHI
AIM: Investigation of practical PCM system using DCL03 and DCL04 Falcon kit
THEORY:
The sine waves (analog signal) of frequency 500Hz and 1KHz and DC signal DC1
and DC2 whose amplitude can be varied accordingly are generated onboard on DCL03. These signals are fed to the input of the Sampling logic CH0 & CH1 and their
samples are multiplexed by interleaving them properly in their assigned time slots.
The crystal oscillator generates a clock of 6.4MHz from which all the transmitter data
and timing signals are derived. For fast mode operation the transmitter clock is
240KHz, and Sampling clock is 16KHz. For show mode operation depending on
jumper position the transmitter clock is 1.23Hz or 0.6Hz and sampling clock is
0.088Hz or 0.044Hz i.e. the sampling rate per channel is 11 or 22 seconds and serial
data transmission rate is 813 milliseconds or 1.6 seconds.
The multiplexed data is Pulse Code Modulated before transmission. At the receiver
after the pulse Code Demodulation, The recovered multiplexed data is sent to
Demultiplexing Logic. The two demultiplexed samples are fed to reconstruction unit.
Which consists of 4th order Low Pass Butterworth Filter, where frequency
components are filtered out to recover the original base band signal at the receiver
output CH0 and Ch1.
EQUIPMENTS:
Experimentor kits DCl-03 & DCL-04
Connecting chords.
Power supply
20 MHz Dual Trace Oscilloscopes.
NOTE: KEEP THE SWITCH FAULT IN OFF POSITION.
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Refer to the Block Diagram (Fig. 1.1) & Carry out the following connections.
Connect power supply in proper polarity to the kits DCL-03 and DCL-04 and
switch it on.
Connect sine wave of frequency 500Hz and 1KHz to the input CH0 and CH1
of the sample and hold logic.
Connect OUT 0 to CH0 IN & OUT 1 to CH1 IN.
Set the speed selection switch SW1 to FAST mode.
Select parity selection switch to NONE mode on both the kit DCL-03 and
DCL-04 as shown in switch setting diagram (Fig. A.).
Connect TXDATA, TXCLK and TXSYNC of the transmitter section DCL03 to the corresponding RXDATA, RXCLK, and RXSYSNC of the receiver
section DCL-04.
Connect posts DAC OUT to IN post of demultiplexer section on DCL-04.
Ensure that FAULT SWITCH SF1 as shown in switch setting diagram (Fig.
A) introduces no fault.
10.
11.
12.
take the observations as mentioned below.

Repeat the above experiment with DC signal at the inputs of the Channel CH
0 and CH1.
Connect ground points of both the kits with the help of connecting chord
provided during all the experiments.
OBSERVATION:
Observe the following signal on oscilloscope and plot it on the paper.
ON KIT DCL-03 (Fig. 1.2) & (Fig. 1.3).
1.
Intput signal CH0 and CH1.
2.
Sample and Hold output OUT 0 and OUT 1.
3.
Multiplexer clock CLK 1 and CLk 2
4.
Multiplexed data MUX OUT.
5.
PCM Data TXDATA, TXCLK, TXSYNC.
ON KIT DCL-04 (Fig. 1.4) & (Fig. 1.5)
1.
RXCLK, RXSYNC, RXDATA.
2.
DAC OUT
3.
Demultiplexer Data CLK 1 and CLK 2
4.
Demultiplexed Data CH 0 and CH 1
5.
Received signal OUT 0 and OUT 1.
SWITCH FAULTS:
Note: Keep the connection as per the procedure. Now switch corresponding fault
1.
2.
3.
4.
5.
6.
Put switch 2 of SF2 (DCL-03) in switch Fault section to ON position. This

will remove PRBS sequence from Transmitted Data. Synchronization will be
only possible in case of direct connection of TXSYNC to RXSYNC. In any
other case no synchronization is possible.
Put switch 3 of SF2 (DCL-03) in switch section to ON position. This will
increase the duty cycle (on period) of CH0. Due to which, some portion of
CH1 signals time slot. Hence demultiplexed output fot CH1 is disturbed.
disable data from going to TX Data, only PRBS will be present.
will disable synch signal in Bit Synchronization. Filter output will be
disturbed.
will disable clock signal for Demultiplexer. One channel output is absent and
other channel output is disturbed.
will remove CH0 filter capacitor connection from ground. Filter output will be
distorted.
CONCLUSION:
We conclude that at the transmitter side sampling for 500Hz and 1KHx signals is
done by using 16KHz sampling clock, hereby satisfying the Nyquist criterion.
Similarly the multiplexed output observed in the oscilloscope shows the proper
alignment of samples in their respective time slots.
At the receiver side the 4th order low pass butterworth filter is used as reconstruction
unit, which reproduce the signals (sine wave and DC signal levels) same as that of the
transmitter side. It is observed in this case, that the reconstruction sine wave has good
linearity.
DEPARTMENT
OF

ON
INVESTIGATION OF DELTA MODULATION AND ADAPTIVE
DELTA MODULATION SYSTEM USING DCL07 FALCON KIT

MESRA, RANCHI
AIM: i) Investigation of Delta Modulation system using DCL07 Falcon kit

ii)Investigation of Adaptive Delta modulation system using DCL07 Falcon kit
Objective: i) Study of Delta Modulation and Demodulation.
THEORY:
DELTA MODULATION:
Delta modulation is the differential pulse code modulation scheme in which the
difference signal is encoded into just a single bit. In digital modulation system, the
analog signal is sampled and digitally coded. This code represents the sampled
amplitude of the analog signal. The digital signal is sent to the receiver through any
channel in serial form. At the receiver the digital signal is decoded and filtered to get
reconstructed analog signal. Sufficient numbers of samples are required to allow the
analog signal to be reconstructed accurately. Delta modulation is a process of
converting analog signal into one bit code, means only one bit is sent per samples.
This bit indicates whether the signal is larger or smaller than the previous samples.
The advantage of DM is that than modulator and demodulator circuits are much
simpler than those used in traditional PCM.
Delta modulation is an encoding process where the logic levels of the transmitted
pulses indicate whether the decoded output should rise or fall at each pulse. This is a
true digital encoding process compared to PAM, PWM and PPM.
If signal amplitude has increased in DM then modulated output is a logic level 1. If
the signal amplitude is a series of zeroes and ones to indicate rise and fall of the
waveform from the previous value.
The block diagram (Fig. 1.1) of Delta illustrates the components at the transmitter end
of the channel and the base signal a (t) and its quantised approximation i (t) are
applied as inputs to the comparator. A comparator as its name suggests simply makes
a comparison between inputs. The comparator has one fixed output c (t) when a (t) > i
(t) the comparator output is then latched in to a D-flip-flop which is clocked by the
selected transmitter clock. Thus the output of the D-flip/flop is latched 1 or 0
synchronous with the clock edge. This binary data stream is transmitted to the
receiver and is also fed to unipolar to bipolar converter. This block converts a logic
0 to positive voltage level and a logic 1 to negative voltage level. Then unipolar to
bipolar output is fed to the input of integrator. The integrator output is then connected
to the negative terminal of voltage comparator, thus completing the modulator circuit.
The waveform of the Delta Modulator is as shown in the figure.
DELTA DEMODULATOR:
The Delta Demodulator (Fig. 1.2) consists of a D-flip/flop, unipolar to bipolar
converter followed by an integrator and a 2nd and 4th order low pass butterworth filter.
The Delta Demodulaor receives the data stream from D-flip/flop of Delta Modulator.
It latches this data at every rising edge of receiver clock. This data stream is then fed
to unipolar to bipolar converter, which changes the output from D-flip/flop to either
ve voltage or +ve voltage for logic 1 and 0 respectively. As it gas been seen in case
of modulator when the output from unipolar to bipolar converter is applied to
integrator, its output tries to follow the analog signal in ramp fashion and hence is a
good approximation of the signal itself. The integrator output contains sharp edges,
which is smoothened out by the 2nd order, and 4th order low pass butterworth filter
whose cut-off frequency is just above the audio band.
The practical use of Delta Modulation is limited due to following drawbacks:
i) NOISE: A noise is defined, as any unwanted random waveform accompanying the
information signal. When the signal is received at the receiver irrespective of any
channel it is always accompanied by noise.
ii) DISTORTION: Distortion means that the receiver output is not the true copy of
the analog input signal at the transmitter. In Delta modulation, when than analog
signal is greater than the integrator output the integrator ramps up to meet the analog
signal. The ramping rate of integrator is constant. Therefore if the rate of change of
analog input is faster than the ramping rate, the modulator is unable to catch up with
the input signal. This causes a large disparity between the information signal and its
quantised approximation. This error phenomenon is known as slope over loading and
causes the loss of rapidly changing information. The slope overloading waveform is
as shown in the figure. The problem of slope overload can be solved by increasing the
ramping rate of the integrator. But as it can be seen from the figure the effect of the
large step size is to add large sharp edges at the integrator output and hence it adds to
noise.
iii) Another problem of Delta Modulation is that it is unable to pass DC information.
This is not a serious limitation of the speech communication.
EQUIPMENTS:
Experimentor Kit DCL-07
Connecting Chords
Power Supply
20MHz Dual Trace Oscilloscope.
PROCEDURE:
1.
2.
3.
Refer to the block diagram (Fig. 1.3) and carry out the following connections.
Connect the power supply with the proper polarity to the kit DCL-07 and
switch it ON.
Select sine wave input 250Hz of 0V through pot P8 and fed it to input buffer
section. Then give buffer output to Delta modulator input.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Then select clock rate of 8 KHz by pressing SW1.

Then observe the Delta modulated output and compare it withy the clock rate
selected. These waveforms are as shown in figure. It is half the frequency of
clock rate selected.
Observe the integrator output test point. It can be observe that as the clock rate
is increased amplitude of triangular waveform decrease. This is called
minimum step size. Then increase the amplitude of 250Hz sine wave up to
0.5V. Signal approximating 250 Hz is available at the integrator output. This
signal is obtained by integrating the digital output resulting from Delta
modulation.
Then go on increasing the amplitude of selected signal through the respective
pot from 0 to 1V. It can be observe that the digital high makes the integrator
output to go upward and digital low makes the integrator output to go
downwards. Observe that the integrator output follow the input signal. Adjust
P12 to get a stable waveform if required. The waveforms are as shown in the
figure. Observe the waveforms at various test-points in the Delta modulator
section.
Increase the amplitude of 250Hz sine wave through pot P8 further high and
observe that the integrator output cannot follow the input signal. State the
reason.
Repeat the above mention procedures with different signal sources and
selecting the different clock rates and observe the response of Delta
Modulator.
Connect Delta modulated output to the input of Delta Demodulation section.
Connect output modulated output to the input buffer section. And give buffer
output to the 4th order low pass butterworth filter through 2nd order low pass
butterwerth filter.
Then observed various tests points in Delta Demodulator section and observed
the reconstructed signal through 2nd and 4th order low pass butterworth filter.
Observe the waveforms as shown in figure.
OBSERVATION:
Observe the following signal on oscilloscope and plot it on the paper. (Fig. 1.4 & Fig.
1.5)
Sampling clock.
Integrator output at feedback loop for Delta modulator.
Delta Modulator output.
Delta Demodulator Output.
Filter Output.
Objective: ii) Study of Adaptive Delta Modulation and Demodulation.

THEORY:
As seen in earlier system Delta Modulation system is unable to chase rapidly
changing information of the analog signal, which gives rise to distortion and poor
quantity reception. The problem can be overcome by increasing the integrator gain.
Adaptive Delta Modulation is a variation of Delta Modulation, Which offers relief
from disadvantage of DM by adopting the step size to accommodate changing signal
conditions. If the input signal is large, step is cause to increase, there by reducing
slope overload effects. The block diagram of ADM is as shown in fig. 3.1. It is same
as Delta Modulation except the variable gain circuit and step size controller. The
controller keeps sensing the slope condition of the message conveyed. If the slope is
large the controller output causes the variable gain ckt to have large gain. If the slope
is small, the controller output causes a small gain.
In certain cases Adaptive Delta Modulation do not change step size on a pulse-topulse basis, but changes are made much more slowly, such slow control is referred to
as syllabic. There are varieties of ICs for CVSD encoding and decoding in todays
semiconductor market. The fig shows the functional block diagram of digital CVSD
IC 3418.
The CVSD is the simple alternative to more complex conventional conversion
techniques in system requiring digital communication of analog signals. The CVSD
A/D is well suited for the requirements of digital communications. A Delta Modulator
consists of a comparator in the forward path and an integrator in the feedback path of
a simple control loop. The input to the comparator is the simple analog signal and the
integrator output. The comparator output is the difference between the input voltage
and the integrator output. That sign bit is the digital output and also control the
direction of ramp in the integrator. The output of comparator is fed to the sampler.
Then the sampler output is fed to the slope polarity switch and level detect algorithm.
The level detect algorithm is again fed to the slope magnitude control followed by
slope polarity switch. The output slope polarity switch is fed to the integrator in the
control loop. With no input at the transmitter of contneous 1 and 0 alterations are
transmitted. The outstanding characteristic is its ability to transmit the intelligible
voice out at relatively low data rate. Companded PCM for telephone quality
transmission requires about 64 Kbps data rate per channel. CVSD produces equal
quality at 32Kbit. /sec. In CVSD Decoder CVSD mod output is fed to the input of
comparator. The comparator output is fed to the internal shift register. Then the output
of internal shift register is fed to the digital logic followed by slope polarity switch
and integrator. The output of integrator is fed to the low pass filter for the
reconstruction of original signal.
EQUIPMENT:
Experimentor kit DCL-07
Connecting Chords.
Power Supply.
20MHz Dual Trace Oscilloscope.
PROCEDURE:
ADAPTIVE DELTA MODULATION:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Connect the power supply with the proper polarity to the Kit DCL-07 and
switch it ON.
Select sine wave input 250Hz and 1.8V through pot P8 and fed it to input
buffer section. Then give buffer output to Delta modulator input.
Then select clock rate of 8 KHz by pressing SW1.
Connect Delta modulated output to the input of Delta Demodulator section.
Connect output of Delta demodulator to the input of output buffer section.
And give buffer output to the 4th order low pass butterworth filter through 2nd
order low pass butterworth filter.
If you observe the distorted sine wave at the output of filter due to slope
overload vary the gain of integrators to maximum in both the blocks of Delta
by pot P12 in the circuits till the good recovery of output.
selecting the different clock rates and observe the response of Adaptive delta
modulation.
We will get better recovery of signal as we go on increasing the clock rates
(e.g. 64KHz).
OBSERVATION:
Observe the following signal on oscilloscope and plot it on the paper.
Sampling clock.
Integrator output at feedback loop for Delta modulator.
Delta Modulator Output.
Delta Demodulator Output.
Filter Output.
CVSD:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Connect the power supply with the proper polarity to the Kit DCL-07 and
switch it ON.
Connect the 1 KHz and 2Vp-p sine wave to the input of the buffer section.
Then connect the buffer output to the CVSD modulator input.
Select the clock rate of 32 KHz by pressing the SW1.
Observe the CVSD output and for make it stable vary the pot P6 if required.
Connect the output of CVSD modulator to the input of CVSD Demodulator.
Observe the waveforms of the CVSD as shown in figure.
Connect CVSD Demodulated output to the buffer output section and connect
reconstruct the original signal. Refer to appendix for more details of IC 4318.
selecting the different clock rates and observe the response of CVSD
Modulator and Demodulator.
10.
Observe all signals on dual channel through oscilloscope probes. We will get
clear reception at high clock rates.
OBSERVATION:
Observe the following signal on oscilloscope and plot it on the paper. (Fig. 3.4)
Sampling Clock.
CVSD Modulator Output.
CVSD Demodulator Output.
Filter Output.
DEPARTMENT
OF

ON
CARRIER MODULATION/DEMODULATION ASK, FSK, PSK.
USING DCL 05 FALCON KIT

MESRA, RANCHI
AIM: Carrier modulation/demodulation ASK, FSK, PSK.

i) Data conditioning and carrier modulation transmitter using DCL 05 Falcon
kit
ii) Data reconditioning and carrier demodulation transmitter using DCL 05
Falcon kit
EUIPMENTS:
Experimentor Kits DCl-05 & DCL-06
Connecting chords.
Power Supply
20 MHz Dual Trace Oscilloscope
OBJECTIVE: a) Study of carrier Modulation Techniques by Amplitude Shift keying
method.
THEORY:
Carrier modulation si a technique by which digital data is made to modulate a
continuous wave (sinewave) carrier. For all types of carrier modulation, the carrier
frequency should be atleast 2 times that of modulating frequency. In Amplitude shift
keying, the carrier is transmitted when the modulating data is one and the carrier is
rejected from transmission when the data is zero. In DCL-05 the ASK Modulator
employs an Analog Multiplexer as a modulating switch, Which can switch between
carrier and ground, for every one to zero transitions. The carrier frequency chosen
for ASK modulation is 1 MHz.
ASK DEMODULATOR block on DCl-06 employs an envelope detector to recover
the data from the modulated carrier. The ASK modulated input is fed to the half wave
rectifier. The rectified input is fed to the filter, Where the original data is recovered.
The threshold detector is used to recover the original amplitude levels it as a one and
whenever the carrier is absent, the detector identifies it as a zero.
NOTE: KEEP THE SWITCH FAULTS IN OFF POSITION.

PROCEDURE:
1.
2.
3.
4.
Refer to the block diagram (Fig. 4.1) and carry out the following connections
switch it on.
Connect CLOCK and DATA generated on DCL-05 to CODING CLOCK
IN and DATA INPUT respectively by means of the connecting-chords
provided.
Connect the NRZ-L data input to the CONTROL INPUT of the carrier
Modulator logic.
5.
6.
7.
Connect carrier component SIN2 to INPUT1 and GROUND to INPUT2 of

the Carrier Modulator Logic.
Connect ASK modulated signal MODULATOR OUTPUT on DCL-05 to the
ASK IN of the ASK DEMODULATOR on DCL-06.
Observe various waveforms as mentioned below (Fig. 4.2).
OBSERVATION:
Observe the following waveforms on CRO and plot it on the paper.
ON KIT DCL_05
1. Input NRZ-L Data at CONTROL INPUT.
2. Carrier frequency SIN 2.
3. ASK modulated signal at MODULATOR OUTPUT.
ON KIT DCL-06
1. ASK Modulated signal at ASK IN.
2. ASK Demodulated signal at ASK OUT.
SWITCH FAULTS:
1. Put switch 2 of SF1 (DCL-05) in switch Fault section to ON position. This
will disable channel selection signal going to Modulator IC. Modulator output
contains only single channel (INPUT 1) data.
OBJECTIVE: b) Carrier Modulation Techniques by Frequency Shift Keying

method.
THEORY:
In frequency Shift Keying modulation techniques, the modulated output shifts
between two frequencies for all one (mark) to zero (space) transitions. The carrier
frequency chosen for FSK modulation are 500 KHz and 1 MHz. Note that the above
frequencies are greater than twice the modulating frequency. Note that the FSK may
be thought of as an FM system in which the carrier frequency is midway between the
mark and space frequencies, and modulation is by a square wave.
CARRIER GENERATOR block on DCL-05 generates the carrier waves 500KHz and
1 MHz, Which are available at SIN1 and SIN2 post.
The FSK modulator is also built around the 2 to 1 Analog Multiplexer, Which
switches between the 500 KHz and 1 MHz signals for all one to zero transitions.
PROCEDURE:
1.
2.
switch it on.
3.
provided.
4.
Connect the NRZ-L data input to the CONTROL INPUT of the Carrier
Modulator logic.
5.
Connect carrier component SIN 1 to INPUT1 and SIN 2 to INPUT2 of the
Carrier Modulator Logic.
6.
Connect FSK modulated signal MODULATOR OUTPUT on DCL-05 to the
FSK IN of the FSK DEMODULATOR on DCL-06.
7.
OBSERVATION:
ON KIT DCL-05
1.
Input NRZ-L Data at CONTROL INPUT.
2.
Carrier frequency SIN 1 and SIN 2.
3.
FSK modulated signal at MODULATOR OUTPUT.
ON KIT DCL-06
1.
FSK Modulated signal at FSK IN.
2.
FSK Demodulated signal at FSK OUT.
3.
Observe output of PHASE DETECTOR, LPF, VCO on test points
provided.
NOTE:
In FSK demodulator PLL circuit used is very sensitive to input voltage level, because
of which you may get blurred output signal if input power varies slightly. To get clear
signal at the output tune pot P3 in FSK Demodulator section. To get better results set
the following bit pattern for INPUT DATA.
10101010
10101110
11101010
00111010
1 1 0 0 1 1 0 0 etc..
SWITCH FAULTS:
1.
2.
3.
Put switch 1 of SF1 (DCL-05) in switch fault section to ON position. This will
open capacitor for filtering of SIN 1 signal. Sine wave SIN 1 will be distorted
and its amplitude gets reduced.
Put switch 2 of SF1 (DCL-05) in Switch Fault section to ON position. This
will disable channel selection signal going to Modulator IC. Modulator output
contains only single channel (INPUT 1 ) data.
Put switch 2 of SF1 (DCL-06) in Switch Fault section to On position. This
will remove resistor connected to PLL in FSK demodulator. Center frequency
of PLL changes and output of FSK demodulator gets distorted.
OBJECTIVE: c) Carrier Modulation Techniques by Phase Shift Keying method.

THEORY:
In Phase Shift Keying (PSK) modulation technique, the modulated output switches
between in-phase and out-of phase component of the carrier for every one to zero
transitions of modulating signal. The carrier frequency chosen for PSK modulation
are 1 MHz (0 Degree) and 1 MHz (180 Degree).
CARRIER GENERATOR block on DCL-05 generates the carrier waves 1 MHz (0
Degree) and 1 MHz (180 Degree), Which are available at SIN 2 and SIN 1 post. The
PSK modulator is also built around the 2 to 1 Analog Multiplexer which switches
between the 1 MHz (0 Degree) and 1 MHz (180 Degree) signals for all one to zero
transitions occurring in the transmitted data stream.
The phase detector works in the principle of squaring loops. First step in PSK
detection is the sine to square wave conversion using an Schmitt Trigger. This enables
the PSK detector to be built around digital ICs. the Biphase splitter basically doubles
the frequency component of the modulated data and also ensure that the out of phase
component of the modulation signal dies not reach the PLL. The PLL recovers the
carrier frequency from the output of the phase splitter, but the frequency of the
recovered carrier is twice that of the transmitted carrier. So a Divide by 2 counter is
used to divide the frequency of the PLL output by 2, thus recovering the reference
carrier. The delay flip-flop is used to compare the phase of the incoming data and the
reference carrier thereby recovering the data.
PROCEDURE:
1.
2.
3.
4.
switch it on.
provided.
Connect the NRZ-L data input to the CONTROL INPUT of the Carrier
Modulator logic.
5.
6.
7.
Connect carrier component SIN 2 to INPUT1 and SIN 3 to INPUT2 of the

Carrier Modulator Logic.
Connect PSK modulated signal MODULATOR OUTPUT on DCL-05 to the
PSK IN of the PSK DEMODULATOR on DCL-06.
OBSERVATION:
ON KIT DCL-05
1.
Input NRZ-L Data at CONTROL INPUT.
2.
Carrier frequency SIN 2 and SIN 3.
3.
PSK modulated signal at MODULATOR OUTPUT.
ON KIT DCL-06
1.
PSK Modulated signal at PSK IN.
2.
PSK Demodulated signal at PSK OUT.
3.
Observe output of SINE TO SQUARE CONVERTOR, SQUARING
LOOP, DIVIDE BY 2 on test points provided.
SWITCH FAULTS:
1.
2.
Put switch 2 of SF1 (DCL-05) in Switch Fault section to ON position. This will
disable channel selection signal going to Modulator IC. Modulator output
contains only single channel (INPUT 1) data.
Put switch 1 of SF1 (DCL-06) in Switch Fault section to ON position. This
will remove connection for signal generator for PLL input. PLL input signal
frequency reduces to half. Output of PSK demodulator gets distorted.
DEPARTMENT
OF

ON
INVESTIGATION OF QAM MODULATION AND
DEMODULATION USING ST 2112 QAM TRAINER KIT

MESRA, RANCHI
AIM: Investigation of QAM modulation and demodulation using ST 2112 QAM

trainer kit
THEORY:
Quadrature Amplitude Modulation (QAM)
The QAM is a digital modulation where the information is contained into the phase as
well as the amplitude of the transmitted carrier.
8-QAM :
In the 8-QAM the data are divided into groups of 3 bits (Tribit), one of which varies
the amplitude of the carrier, the last two the phase. The modulated signal can take 4
different phases and 2 different amplitudes, for a total of 8 different states.
16-QAM :
In the 16-QAM the data are divided into groups of 4 bits (Quadbit). The 16 possible
combinations change amplitude and phase of the carrier, which can take 16 different
states.
N-QAM :
At the moment we reach to a data subdivision into groups of 9 bits, obtaining

constellations with 512 modulation points.
Main aspects
The main aspects characterizing the QAM are :
Applications in modems for high speed data transmission (ITU-TV22bis, V29,

V32, V32bis, V33, V34, V43bis, BELL 209) and digital radio transmission. It
needs circuits of high complexity.
Possibility of error higher than the PSK called Fb the bit transmission speed and
n the number of bits. Considered for the modulation, the minimum spectrum Bw
of the modulated signal is equal to Ft/n.
The transmission efficiency, defined as the ratio between Fb and Bw, is equal to
n.
Modulator QAM :
The functional diagram of a 8-QAM modulator is shown in fig. 983.2, While the
block diagram of the modulator mounted on the module is shown in fig. 28.
The 8-Qam signal can be seen as 4-PSK signal whose amplitude can take 2 different
values. In this way, each modulation interval depends on the state of 3 data bits
(I, Q, C): the first 2 (I and Q) determine the phase of the output signal, the
third (C) the amplitude.
In the example on the module the amplitude of the 4-PSK signal, generated as shown
in experiment of QPSK modulation, is reduced to half by an output attenuator,
activated when the bit C is 1. The carrier, as in case of the 4-PSK, is 1 KHz.
8-QAM Demodulator :
The 8-Qam demodulator on the module uses the 4-PSK demodulator to detect the
signals I and Q, while the signal C is obtained detecting the amplitude of the
positive values of the signal I. This amplitude can take 2 positive and two negative
values, as function of the value of the signal C in transmission. The demodulator
C detects which of the two levels is present in the coming signal. If the level is the
highest you obtain the value 1, if the value is the lowest you obtain the value 0.
The block diagram of the 8-QAM demodulator is shown in fig.983.4. The
demodulator includes the following circuits :
The regenerator of the carriers at 00 and 900 (the same of the 4-PSK demodulator)
Two 2-PSk demodulators (indicated on the diagram as I-DEM and Q Dem two
low pass filters.
A circuit discriminating the amplitude of the signal I. This enables to obtain the
signal C.
A data clock extraction circuit and three data re-timing circuits. The signals I,
Q and C are supplied across the outputs TP20, Tp21 and TP22.
Demodulator QAM :
PROCEDURE:
1.
Ensure the following initial conditions on ST2112 trainer:

A. SW3, SW5, SW6, SW7, SW9 should be in the OFF mode.
B. Power supply should be OFF.
2.
Switch on the power supply.
3.
Connect Test Point TP6 on Channel 1 & TP7 on Channel 2 of Oscilloscope;

you will observe 1 KHz sine and cosine wave.
4.
Set I, Q & C Channel data with the help of DIPswitch SW5, SW6, and SW7.
As there are 24 bits of data available on the trainer so, first bit is I bit then
second bit is Q bit then third bit is C bit. In this experiment you have to use I
bit & Q bit & C bit so you can select combination according to your
requirement.
5.
For example:
SW5 = 11000110
SW6 = 01011000
SW7 = 01100010
Switch ON all the DIP switches on SW3.
6.
Now press SW8, which is reset switch then press SW4 that is start.
7.
Now Connect Channel 1 of Oscilloscope to TP2 & Channel 2 to TP1, you can
observe Clock & Data, which you have set. (If you are using logic analyzer
then you are able to see all 24 bits).
8.
Now to observe QAM modulated signal with respect to data, connect Channel
1 to TP1 & Channel 2 to TP9.
9.
You can add noise by using SW9 (001/010/111).
10.
To observe the demodulator sections connect Channel 1 of the Oscilloscope to

the test point TP12 you will observe squarer frequency.
11.
To observe I switch and Q switch in the demodulator section, Connect channel

1 of oscilloscope to TP16 & channel 2 of the oscilloscope to TP17.
12.
To observe I, Q & C demodulated signal connect oscilloscope to TP20, TP21,

TP22 (If you have logic analyzer you can observe I, Q, & C simultaneously).
13.
To observe input data, output data, encoded data & decoded data you have to
connect logic analyzer to test points TP1, TP2, TP3, TP4, TP5, TP20, TP21,
TP22, TP23, TP24 etc.
14.
Turn OFF the power.
Waveforms:
DEPARTMENT
OF

ON
INVESTIGATION OF QPSK MODULATION AND
DEMODULATION USING ST 2112 QAM TRAINER KIT

MESRA, RANCHI
AIM: Investigation of QPSK modulation and demodulation using ST 2112 QAM

trainer kit
THEORY:
PHASE SHIFT KEY (PSK):
In this kind of modulation, the sine carrier takes 2 or more phase values,
directly determined by the binary data signal (2-phase modulation) or by the
combination of a certain number of bits of the same data signal (N-phase modulation).
In this experiment we examine 2-phase PSK modulation. In 2-phase PSK modulation,
called 2-PSK, or Binary PSK (BPSK), or Phase Reversal Keying (PSK), the sine
carrier takes 2 phase values, determined by the binary data signal (fig. a). A
modulation technique is one using a balanced modulator is the direct or inverted (i.e.
shifted of 1800) input carrier, as function of the data signal.
DATA
PSK
Fig.10
1
CONSTELLATION
Fig. 11
The modulation states of the PSK Modulator are represented with points in a vectorial
diagram. Each point is a modulation state, characterized by a phase and amplitude.
This representation is called constellation diagram, or more simply constellation.
The main aspects of characterizing the BPSK are:
Use of digital radio transmission.
It requires circuits of average-high complexity.
High possibility of error but lower than FSK.
If Fb is the bit transmission speed, the minimum spectrum Bw of the

modulated signal is higher than Fb.
The block diagram of the BPSK modulator in QAM Trainer is shown in the Fig
12. The sine carrier is applied to an input of the balanced modulator 1;a data
signal (indicated with I) is applied to the other input. The circuit operates as
balanced inputs.
Across the output, the sine carrier is direct when the data signal is to low level (bit
0), inverted when the bit is 1.
4 PHASE PSK MODULATION.

In this modulation, called 4-PSk, or Quadrature PSK (QPSK), the sine carrier takes 4
phase values, separated of 900 and determined by the combinations of bit pairs (Dibit)
of the binary data signal. Fig a shows an example of correspondence between Dibit
and phase. The data are coded into Dibit by a circuit generating:
A data signal I (In phase) consisting in voltage levels corresponding to the value
of the first bit of the considered pair, for a duration equal. To 2 bit intervals.
A data Q (Quadrature) consisting in voltage levels corresponding to the value of

the second bit of the pair, for duration equal to 2 bit intervals.
Q
1
I
1
Q I
0 1
Q I
1 1
0 0
Q
1
I
0
Q I
1 1
Q
0
I
0
Q
0
I
1
Main aspects :
The main factors characterizing the QPSK are :
Application in data transmission modems (ITU- T V22N26, BELL 20 I) and

digital radio transmission.
It needs circuits of high complexity.
Possibility of error lowers than FSK but higher than 2-PSK.
Called Fb the bit transmission speed, the minimum spectrum Bw of the modulated
signal is equal to F t/2
The transmission efficiency, defined as the ratio between Fb and Bw, is equal to 2.
4-PSK MODULATOR :
The 4 phases of the sine carrier can be obtained via the sum of 2 sine waves with the
same frequency and shifted of 900 between them. We can call the sine waves
respectively <1>0 and <1>90 :
<1>0 = sin (wc.t)

<1>90 = cos (wc.t)
By adding respectively ,1> 0 and <1> 90 direct or inverted :

0 + 90
-0 + 90
0 - 90
-0 - 90
90
0
0
- 90
90
-0
-0
- 90
we obtain the 4 phases for the QPSK signal. The modulator is carried out with two
multipliers used as 2-PSK modulators, which supply the modulated PSK1 and PSKQ
signals. The sum of the Two generates the PSK signal with the 4 possible phases.
The block diagram of the modulator used on the trainer in shown in fig. Two 1 KHz
sine carriers, shifted between them of 900, are separately applied to 2 balanced
modulators. The data (signals I and Q) reach the two modulators from the Dibit
generator. Each modulator provides the direct sine-wave when the data signal is to
low level 9bit 0), the inverted sine-wave (shifted of 1800) when the bit is 1. By
adding the two outputs you get a 1 KHz sine signal, which phase can take 4 different
values separated of 900 between them.
PROCEDURE:
1.
Ensure the following initial conditions on ST2112 trainer:

a. SW3, SW5, SW6, SW7, SW9 should be in the OFF mode.
b. Power supply should be OFF.
2.
Switch on the power supply.
3.
Connect Test point TP6 on channel 1 & TP7 on channel 2 of Oscilloscope;

you will observe 1 KHz sine & cosine wave.
4.
Set I & Q Channel data with the help of DIP switch SW5, SW6, SW7. As
there are 24 bits data available on the trainer so. First bit is I bit then
second bit is Q bit then third bit is C bit. But in this experiment you have
to use I bit & Q bit so you can select combination according to your
requirement.
For example :
SW5 = 11000010
SW6 = 01001010
SW7 = 00100010
5.
Switch ON all the DIP switches on SW3.
6.
Now press SW8 which is reset switch then press SW4 which is start.
7.
Now connect Channel 1 of Oscilloscope to TP2 & Channel 2 to TP1, you

can observe clock & Data which you have set.
8.
Now to observe QPSK modulated signal with respect to data connect

Channel 1 to TP1 & Channel 2 to TP8. You can observe QPSK modulated
signal with respect to data.
9.
Turn OFF the power
DEPARTMENT
OF

ON
GENERATION OF FRAME AND MARKER IN
TIME DIVISION MULTIPLEXING.

MESRA, RANCHI
AIM:- Generation of frame and marker in Time division Multiplexing.

EQUIPMENTS:
1. Experimenter Kit DCL-09
2. Power Supply
3. Connecting Chords
4. 20MHz Dual Trace Oscilloscope
5. Noise and Audio Amplifier (Optional)
6. Audio Amplifier Kit (Optional)
7. Microphone (Optional)
(i) OBJECTIVE: Generation of Time division multiplexed signal

To study simultaneously transmission of signals using synchronous Eight Channel
Time Division Multiplexing.
THEORY:
In case of communication systems, signals that are transmitted usually carry
audio or video information with them and are interpreted by human eye or ears. Need
in increase in speed and bandwidth has formed the base for the concept of time
division multiplexing. In time division multiplexing various signals are sampled and
transmitted for a fixed duration of time one after the other. At the receiving end these
signals are extracted in the same order and form of transmission.
To implement this scheme we have used 8 channels multiplexer at
transmitter end with clock generator for timing of signals. One channel is reserved for
marker transmission, one for voice transmission; six channels take their inputs from
six data switches. Each channel has a data rate of 64 Kbits/sec.
This data is passed through buffers towards receiver. At the receiver end
this data is the demultiplexed, giving out each signal separately in its original form
and shape.
PROCEDURE:
1. Refer to the block diagram (Fig 1.1) and carry out the following connections
and switching settings.
2. Connect the Power Supply with proper polarity to the kit DCL-09 and switch
it on.
3. Set MARKER TX & MARKER RX each for a bit pattern as shown in the
block diagram (Fig. 1.1) using SW7 & SW8.
4. Connect SINE OUT post to ANALOG/AUDIO IN post.
5. Keep the sine wave signal amplitude at 2 Vpp (P1 completely clockwise) are
frequency at 1 KHz (P2 completely anticlockwise).
6. Observe the timedevision-multiplexed data at test point TDM TX on

oscilloscope.
7. Carefully observe the time duration for which each channel is selected,
observe and measure the frame period.
8. Connect the POST TX to post TDM RX.
9. Make one of the switches from the given switches from the given six (CH2
toCH4, CH6 to CH8) ON and observe how data is corresponding time slot.
(Fig.1.2).
10. Observe the data transmission by switching ON the switches for data
channel and observe the corresponding LEDs light up at receivers section.
11. Observe the position of the voice channel from marker. Marker is at the start
of the frame. Voice channel is at fifth position. At fifth position we will get
digitized output corresponding to applied analog signal. Observe this at test
point TDM TX.
12. Observe the post AUDIO OUT for demultiplexed and decoded analog signal.
13. For voice channel observation we have to connect external audio interfacing
kits to DCL-09.
SWITCH FAULTS:
NOTE: Keep the connections as per the procedure. Now switch corresponding faults
1. Put switch 2 of SW1 in Switch Fault section to ON position. This will short
CH2 to CH3. This will reflect at the output as LED glow for both CH2 and
CH3 even if any of the Channel Switch is put ON.
2. Put switch 3 of SW1 in Switch Fault section to ON position. This will short
capacitor, which will disturb voice channel.
3. Put switch 4 of SF1 in Switch Fault section to ON position. This will short
first two bits of transmitter marker. This will change first two markers. Bit as
per setting of any one of the two bits. Therefore for synchronization first two
bits of MARKER RX should be adjusted accordingly to MARKER TX first
two bits. (For e.g. High for any bit high from first two bit of MARKER TX).
4. Put switch 5 of SW2 in Switch Fault section to ON position. This disables the
clock for Transmitter Marker; hence there is no Marker insertion in TDM TX
output.
5. Put switch 6 of SW2 in Switch Fault section to ON position. This will remove
input from CH6 and output LED for CH6 at receiver remains permanently
ON.
6. Put switch 7 of SW2 in Switch Fault section to ON position. This will open
connections for voice CODEC chip, which will disable voice channel.
7. Put switch 8 of SF2 in switch Fault section to ON position. This opens the
connection for CH4 Output LED in receiver section. CH4 is disabled at
receiver section.
(ii)
OBJECTIVE: Generation of Framing in Time Division Multiplexing
THEORY:
This is an advanced experiment on time division multiplexing. This
experiment examines the method of synchronous multiplexing. A FRAME plays a
vital role in synchronous time division multiplexing, which repeats after every T
seconds. The frame has n bits and frame rate is 1/T frames per second. The total data
rate is n/T bits per second. Asynchronous multiplexing can occupy one or more bits
in every frame. A signal occupying one bit per frame will have a data rate of m/T bit
per second.
The repetition rate of the frame depends on the channel sampling
frequency. Since we are transmitting audio signals on these channels we should
sample at least twice the highest frequency component in audio signal, which is
4KHz. This determines frame frequency of 8 KHz, within the period of 125 microsec. We transmit 8 channels; each channel On period comes to about 125/8 micro-sec.
This corresponds to the frequency of 8KHz. Lastly we transmit 8 bit per channels,
data rate can be derived as 15.625 micro-sec/8 = 1.953125 micro-sec and 1/1.953125
micro-sec = 512 KHz.
PROCEDURE:
1. Refer the block diagram (Fig.2.1) and carry out the following connections and
switch setting.
it on.
OBJECTIVE: Generation and importance of Marker in Time Division Multiplexing.
PROCEDURE:
1. Refer the block diagram (Fig.3.1) and carry out the following connections and
switch setting.
it on.
3. Set both marker with the help of DIP switches SW7 & SW8 as shown in the
diagram.
4. Connect SINE OUT post to ANALOG/AUDIO IN post.
5. Keep the sine wave signal amplitude at 2 Vpp (P1 completely clockwise) and
frequency at 1 KHz (P2 completely anticlockwise).
6. Connect the post TDM TX to post TDM RX.
7. Observe the signal at TDM TX on oscilloscope. Clearly observe the marker
data transmitted in the first slot of each frame. Marker SW7 is individually
available at MARKER OUT and marker DETECTION PULSE at receiver
only. If marker settings for transmitter and receiver matches.
8. The marker is demultiplexed and detected at the receiver side.

9. Change the setting of the corresponding marker at transmitter or receiver
section switch SW7 or SW8 and carefully observe what effect marker have on
received data (channel indication LED), received marker bits and analog
output at AUDIO OUT post.
10. Marker bits at MARKER TX and MARKER RX can be changed as shown
in the marker-setting diagram (Fig3.3).
SWITCH FAULTS:
NOTE: Keep the connections as per the procedure. Now switch corresponding
fault switch button in ON condition & observe the different effect on the output.
The faults are normally used one at a time.
1. Put switch 4 of SF1 in Switch Fault section to ON position. This will short
first two bits of transmitter Marker. This will change first two marker bit as
per setting of any one of the first two bits. Therefore for synchronization first
two bits of MARKER RX should be adjusted accordingly to MARKER TX
First two bits. (For e.g. High for any bit high from first two bit of MARKER
TX)
2. Put switch 5 of SF2 in Switch Fault section to ON position. This disables the
clock for Transmitter Marker; hence there is no Marker insertion in TDm TX
output.
DEPARTMENT
OF

ON
CALCULATION OF MEAN AND VARIANCE AND
INVESTIGATION OF AUTOCORRELATION USING COMMSIM

MESRA, RANCHI
AIM: i)
ii)
Calculation of Mean and Variance using Commsim under

a)
Running mode
b)
Sliding window mode
Investigation of autocorrelation using Commsim
THEORY:
Mean Value
Finding the average value of a set of random signals or random variables is probably
the most fundamental concepts we use in evaluating random processes through any
sort of statistical method. The mean of a random process is the average of all
realizations of that process. In order to find this average, we must look at a random
signal over a range of time (possible values) and determine our average from this set
of values. The mean, or average, of a random process, x (t), is given by the following
equation:
mx (t) = x (t)
= E [X]
= xf ( x)dx
If we have two random signals or variables, their averages can reveal how the two
signals
interact. If the product of the two individual averages of both signals do not equal the
average of the product of the two signals, then the two signals are said to be linearly
independent, also referred to as uncorrelated.
In the case where we have a random process in which only one sample can be viewed
at
a time, then we will often not have all the information available to calculate the mean
using the density function as shown above. In this case we must estimate the mean
through the time-average mean.
Mean-Square Value
If we look at the second moment of the term (we now look at x2 in the integral), then
we will have the mean-square value of our random process. As you would expect, this
is
written as
E [X ] =
f ( x)dx
This equation is also often referred to as the average power of a process or signal.
Variance
Now that we have an idea about the average value or values that a random process
takes,
we are often interested in seeing just how spread out the different random values
might be. To do this, we look at the variance which is a measure of this spread. The
variance, often denoted by 2, is written as follows:
2 = Var (X)
= E [(X E [X]) 2]
= (X - E [X]) 2 f ( x )dx
Using the rules for the expected value, we can rewrite this formula as the following
form,
which is commonly seen:
2 = E [X2 (E [X])2 ]
Standard Deviation
Another common statistical tool is the standard deviation. Once you know how to
calculate the variance, the standard deviation is simply the square root of the variance,
or
Autocorrelation:
Autocorrelation is a mathematical tool used frequently in signal processing for
analysing functions or series of values, such as time domain signals. Informally, it is a
measure of how well a signal matches a time-shifted version of itself, as a function of
the amount of time shift. More precisely, it is the cross-correlation of a signal with
itself. Autocorrelation is useful for finding repeating patterns in a signal, such as
determining the presence of a periodic signal which has been buried under noise, or
identifying the missing fundamental frequency in a signal implied by its harmonic
frequencies.
The autocorrelation function is simply the expected value of a product. Assume we
have a pair of random variables from the same process,
X1 = X (t1)
and
X2 = X (t2),
then the autocorrelation is often written as
Rxx (t1, t2) = E [X1X2]
= x 1 x 2 f (x 1 , x 2 ) dx 2 dx 1
The above equation is valid for stationary and nonstationary random processes. For
stationary processes, we can generalize this expression a little further. Given a widesense
stationary processes, it can be proven that the expected values from our random
process
will be independent of the origin of our time function. Therefore, we can say that our
auto-correlation function will depend on the time difference and not some absolute
time. For this discussion, we will let = t2 t1, and thus we generalize our
autocorrelation expression as
Rxx (t, t + ) =Rxx ( )
= E [X (t)X (t + )]
PROCEDURE :
Refer to commsim example and help file
DEPARTMENT
OF

ON
DESIGN OF ASK AND FSK MODULATOR/DEMODULATOR
USING COMMSIM

MESRA, RANCHI
AIM: Design of ASK and FSK modulator/demodulator using Commsim
(i)
ASK modulator/demodulator
THEORY:
Carrier modulation si a technique by which digital data is made to modulate a
continuous wave (sinewave) carrier. For all types of carrier modulation, the carrier
frequency should be atleast 2 times that of modulating frequency. In Amplitude shift
keying, the carrier is transmitted when the modulating data is one and the carrier is
rejected from transmission when the data is zero. ASK Modulator employs an
Analog Multiplexer as a modulating switch, Which can switch between carrier and
ground, for every one to zero transitions.
ASK DEMODULATOR employs an envelope detector to recover the data from the
modulated carrier. The detected signal is fed to the filter, Where the original data is
recovered. The threshold detector is used to recover the original amplitude levels it as
a one and whenever the carrier is absent, the detector identifies it as a zero.
ASK Modulation:
b(t)
Product
Modulator
ASK
Wave
Carrier Wave
ASK Demodulation:
ASK
Wave
Envelop
detector
Filter
Decision
device
Threshold
0
Or
1
(ii)
FSK modulator/demodulator
THEORY: In frequency Shift Keying modulation techniques, the modulated

output shifts between two frequencies for all one (mark) to zero (space)
transitions. The carrier frequency chosen should be greater than twice the modulating
frequency. Note that the FSK may be thought of as an FM system in which the carrier
frequency is midway between the mark and space frequencies, and modulation is by a
square wave.
FSK Modulator:
Frequency
Modulator
b(t)
FSK
Wave
Carrier Wave
FSK Demodulator:
BPF f1
Envelope
Detector
Comparator
FSK
BPF f2
Envelope
Detector
Binary
Signal
DEPARTMENT
OF

ON
DESIGN OF PSK AND QPSK MODULATOR/DEMODULATOR
USING COMMSIM

MESRA, RANCHI
AIM: Design of PSK and QPSK modulator/demodulator using Commsim

THEORY:
PHASE SHIFT KEY (PSK):

In this kind of modulation, the sine carrier takes 2 or more phase values,
directly determined by the binary data signal (2-phase modulation) or by the
combination of a certain number of bits of the same data signal (N-phase modulation).
In this experiment we examine 2-phase PSK modulation. In 2-phase PSK modulation,
called 2-PSK, or Binary PSK (BPSK), or Phase Reversal Keying (PSK), the sine
carrier takes 2 phase values, determined by the binary data signal (fig. a). A
modulation technique is one using a balanced modulator is the direct or inverted (i.e.
shifted of 1800) input carrier, as function of the data signal.
DATA
PSK
Fig.10
1
CONSTELLATION
Fig. 11
The modulation states of the PSK Modulator are represented with points in a vectorial
diagram. Each point is a modulation state, characterized by a phase and amplitude.
This representation is called constellation diagram, or more simply constellation.
The main aspects of characterizing the BPSK are:
Use of digital radio transmission.
It requires circuits of average-high complexity.
High possibility of error but lower than FSK.
If Fb is the bit transmission speed, the minimum spectrum Bw of the
modulated signal is higher than Fb.
4 PHASE PSK MODULATION.

In this modulation, called 4-PSk, or Quadrature PSK (QPSK), the sine carrier takes 4
phase values, separated of 900 and determined by the combinations of bit pairs (Dibit)
of the binary data signal. Fig a shows an example of correspondence between Dibit
and phase. The data are coded into Dibit by a circuit generating:
A data signal I (In phase) consisting in voltage levels corresponding to the value
of the first bit of the considered pair, for a duration equal. To 2 bit intervals.
A data Q (Quadrature) consisting in voltage levels corresponding to the value of

the second bit of the pair, for duration equal to 2 bit intervals.
Q
1
I
1
Q I
0 1
Q I
1 1
0 0
Q
1
I
0
Q
0
I
0
Q
0
I
1
Q I
1 1
Main aspects :
The main factors characterizing the QPSK are :
Application in data transmission modems (ITU- T V22N26, BELL 20 I) and

digital radio transmission.
It needs circuits of high complexity.
Possibility of error lowers than FSK but higher than 2-PSK.
Called Fb the bit transmission speed, the minimum spectrum Bw of the modulated
signal is equal to F t/2
The transmission efficiency, defined as the ratio between Fb and Bw, is equal to 2.
4-PSK MODULATOR :
The 4 phases of the sine carrier can be obtained via the sum of 2 sine waves with the
same frequency and shifted of 900 between them. We can call the sine waves
respectively <1>0 and <1>90 :
<1>0 = sin (wc.t)

<1>90 = cos (wc.t)
By adding respectively ,1> 0 and <1> 90 direct or inverted :

0 + 90
-0 + 90
0 - 90
-0 - 90
90
0
0
- 90
90
-0
-0
- 90
we obtain the 4 phases for the QPSK signal. The modulator is carried out with two
multipliers used as 2-PSK modulators, which supply the modulated PSK1 and PSKQ
signals. The sum of the Two generates the PSK signal with the 4 possible phases.
(i)
PSK modulator/demodulator
PSK modulation
Product
Modulator
b(t)
PSK
Wave
Carrier Wave
PSK demodulation
PSK
Wave
Integrator
Decision
device
Threshold
0
Or
1
(ii) QPSK modulator/demodulator

QPSK modulation:
X
Oscillator
Serial to
parallel
converter
-900 Phase
Shifter
QPSK
Signal
b(t)
X
QPSK demodulation:
Integrator
Oscillator
QPSK
-90 Phase
Shifter
Decision
Device
Threshold
Parallel
to
serial
Threshold
X
Integrator
Decision
Device
Binary
Signal
DEPARTMENT
OF

ON
INVESTIGATION OF NONLINEAR QUANTIZATION OF THE
SINUSOIDAL SIGNAL USING -LAW AND A-LAW

MESRA, RANCHI
AIM: Investigation of Nonlinear quantization of the Sinusoidal signal using -law

and A-law.
THEORY:
Signal Quantization and Compression Overview :
Sampling transforms a continuous-time signal into a discrete-time signal or sequence.
The samples of the sequence can assume arbitrary values. However, in a digital
implementation, real numbers have to be represented using a finite number of bits and
the discrete-time sequence has therefore to be represented as a digital sequence. This
can be achieved via quantization.
Linear Quantization
In this experiment we deal only with linear quantization where the finite set of values
to choose from are uniformly spaced. More specifically, assume we are allowed only
B bits to represent the amplitude of a sample. This means that for each sample, we
should map its amplitude to only one of 2B possible levels. Now if the input signal is
known to have a range R (i.e., the amplitudes of its samples can only lie between -R
/2 and +R /2), then the spacing between these levels is equal to =R/2B.
Once we have identified or defined the finite set of reconstruction levels, we can then
choose a rule that allows us to map an amplitude to a certain reconstruction level.
There are several ways to achieve this mapping and in this experiment we study three
of them.
The optimal way to map from the input value to the reconstruction level is to round
the input value to the closest reconstruction level. Another way is to truncate an input
value to the closest level that is smaller than it. A third way is to apply sign magnitude
truncation, which maps an input value to the closest level whose absolute value is
smaller than its absolute value.
Assume, for example, that the reconstruction levels are {-3,-1,1,3}. The amplitude 2.9
will be mapped to the level 3 if rounding is used, to the level 1 if truncation is used,
and to the level 1 again if sign magnitude truncation is used. On the other hand, the
amplitude -2.9 will be mapped to the level -3 if rounding is used, to the level -3 again
if truncation is used, and to the level -1 if sign magnitude truncation is used.
Companding Law
Narrowband speech is typically sampled 8000 times per second. Now assume we
employ linear quantization to map the amplitudes of the samples to digital levels. It
has been observed in practice that 12 bits per sample (i.e., B=12) are needed for very
good quality speech, thus resulting in a bit rate of about 96 Kbits/s. We would like to
lower the bit rate (since at this rate one minute of speech would require 6 MB of
storage).
Assume the speech signal is normalized to the range R=1 (i.e., its samples lie between
-1 and 1). If we examine a typical speech signal and its histogram, we shall see that
we rarely use the extreme values +1 and -1 (see the figure below). Nonetheless, in a
linear quantization scheme, we assign as many reconstruction levels for larger
amplitudes as for smaller amplitudes, which are more probable to occur.
A-law and u-law (pronounced mu-law) are so-called companding (COMPression expANDING) schemes that are used in telephone networks (see figure below). They
expand small values and compress large values. In other words, when a signal goes
through a compander, small amplitudes are mapped into a larger interval and larger
amplitudes are mapped into a smaller interval. In this way, more quantization levels
are used for the values that originated from small amplitudes. This scheme is
equivalent to applying non-uniform quantization to the original signal, where smaller
quantization levels are used for smaller values and larger quantization levels are used
for larger values.
.
The above figures shows that the range of input values (horizontal line) contained in
the interval [-0.2,0.2] is mapped to the wider output interval [-0.6,0.6] (vertical line).
On the other hand, the input intervals [-1,-0.6] and [0.6,1] are compressed to the
outputs intervals [-0.9,-1] and [0.9,1]. The purpose of the mu-law companding
function is therefore to equalize the histogram of the speech signal so that the
reconstruction levels tend to be equally used. The figure below shows the histogram
of the same speech signal after mu-law companding.
In this experiment, you can select among different sound signals and plot both the
original signal and
Procedure :
Refer to commsim example and help file

Digital Communication Lab

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital Communication Lab

Uploaded by

Copyright:

Available Formats

EC 5106: DIGITAL COMMUNICATION LABORATORY

Sliding window mode

ii) Investigation of autocorrelation using Commsim

DIGITAL COMMUNICATION LABORATORY

LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

BIRLA INSTITUTE OF TECHNOLOGY

NATURAL SAMPLING AND ITS RECONSTRUCTION.

DIGITAL COMMUNICATION LABORATORY

LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

BIRLA INSTITUTE OF TECHNOLOGY

AIM: Investigation of TDM system using DCL02 Falcon kit

The Onboard Function Generator.

ONBOARD FUNCTION GENERATOR:

DIGITAL COMMUNICATION LABORATORY

LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

BIRLA INSTITUTE OF TECHNOLOGY

take the observations as mentioned below.

Put switch 2 of SF2 (DCL-03) in switch Fault section to ON position. This

DIGITAL COMMUNICATION LABORATORY

LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

BIRLA INSTITUTE OF TECHNOLOGY

AIM: i) Investigation of Delta Modulation system using DCL07 Falcon kit

Then select clock rate of 8 KHz by pressing SW1.

Objective: ii) Study of Adaptive Delta Modulation and Demodulation.

DIGITAL COMMUNICATION LABORATORY

LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

BIRLA INSTITUTE OF TECHNOLOGY

AIM: Carrier modulation/demodulation ASK, FSK, PSK.

NOTE: KEEP THE SWITCH FAULTS IN OFF POSITION.

Connect carrier component SIN2 to INPUT1 and GROUND to INPUT2 of

OBJECTIVE: b) Carrier Modulation Techniques by Frequency Shift Keying

NOTE: KEEP THE SWITCH FAULTS IN OFF POSITION.

OBJECTIVE: c) Carrier Modulation Techniques by Phase Shift Keying method.

Connect carrier component SIN 2 to INPUT1 and SIN 3 to INPUT2 of the

DIGITAL COMMUNICATION LABORATORY

LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

BIRLA INSTITUTE OF TECHNOLOGY

AIM: Investigation of QAM modulation and demodulation using ST 2112 QAM

At the moment we reach to a data subdivision into groups of 9 bits, obtaining

The main aspects characterizing the QAM are :

Applications in modems for high speed data transmission (ITU-TV22bis, V29,

Ensure the following initial conditions on ST2112 trainer:

Switch on the power supply.

Connect Test Point TP6 on Channel 1 & TP7 on Channel 2 of Oscilloscope;

You can add noise by using SW9 (001/010/111).

To observe the demodulator sections connect Channel 1 of the Oscilloscope to

To observe I switch and Q switch in the demodulator section, Connect channel

To observe I, Q & C demodulated signal connect oscilloscope to TP20, TP21,

Turn OFF the power.

DIGITAL COMMUNICATION LABORATORY

LAB INSTRUCTIONS FOR CARRYING OUT PRACTICAL

BIRLA INSTITUTE OF TECHNOLOGY

AIM: Investigation of QPSK modulation and demodulation using ST 2112 QAM

If Fb is the bit transmission speed, the minimum spectrum Bw of the

4 PHASE PSK MODULATION.

A data Q (Quadrature) consisting in voltage levels corresponding to the value of

Application in data transmission modems (ITU- T V22N26, BELL 20 I) and

It needs circuits of high complexity.

Possibility of error lowers than FSK but higher than 2-PSK.

<1>0 = sin (wc.t)

By adding respectively ,1> 0 and <1> 90 direct or inverted :

Ensure the following initial conditions on ST2112 trainer:

Switch on the power supply.

Connect Test point TP6 on channel 1 & TP7 on channel 2 of Oscilloscope;