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(axi_master_lite) (v2.00a)
DS836 June 22, 2011
Product Specification
Introduction
Core Specifics
Supported
Device
Family (1)
Virtex-6, Spartan-6
Supported
User Interfaces
Resources
DSP Block
LUTs FFs Slices RAMs Frequency
Features
Product Specification
Design Files
VHDL
Example
Design
Not Provided
Test Bench
Not Provided
Constraints
File
Not Provided
Simulation
Model
Not Provided
Synthesis
Tools
XST
Support
Provided by Xilinx, Inc.
1. For a complete listing of supported devices, see the release notes
for this core.
2. For the supported versions of the tools, see the ISE Design Suite 13:
Release Notes Guide.
Copyright 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in
the United States and other countries. All other trademarks are the property of their respective owners. ARM is a registered trademark of ARM in the EU and other
countries. The AMBA trademark is a registered trademark of ARM Limited. All other trademarks are the property of their respective owners.
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Applications
The AXI Master Lite provides a AXI4-Lite mastering capability that has the legacy IPIC User interface suitable for
updating to AXI4 those legacy plbv46 designs that used the plbv46_master_single module.
The backend IPIC interface connects directly to the legacy User IPIC interface of the plbv46_master_single without
modification. However, the plbv46 signal set has been replaced with AXI4-Lite master signal set. To migrate from a
plbv46_master_single core:
HDL Changes
Add AXI Interconnect related parameters. See DS768, LogiCORE AXI Interconnect IP Data Sheet, for more
information.
Functional Description
'The AXI Master Lite provides a quick way to implement a light-weight mastering interface between user logic and
an AXI4-Lite interface. Figure 1 is a block diagram of the AXI Master Lite. The port references and groupings are
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detailed in Table 1. The design is natively 32 bits and supports read and write transfers of 1 to 4 bytes. Transfer
request protocol between the AXI4 and the User Logic is provided by the Read and Write Controller block.
X-Ref Target - Figure 1
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www.xilinx.com
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I/O Signals
The AXI Master Lite signals are described in Table 1.
Table 1: AXI Master Lite I/O Signal Description
Signal Name
Signal
Init
Type Status
Interface
Description
System Signals
m_axi_lite_aclk
Clock
m_axi_lite_aresetn
Reset
Discrete Out
M_AXI_LITE
zeros
m_axi_lite_arprot(2:0)
M_AXI_LITE
000b
m_axi_lite_arvalid
m_axi_lite_arready
M_AXI_LITE
M_AXI_LITE
m_axi_lite_rresp(1:0)
m_axi_lite_rvalid
m_axi_lite_rready
M_AXI_LITE
M_AXI_LITE
M_AXI_LITE
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Interface
Signal
Init
Type Status
Description
m_axi_lite_awaddr
(C_M_AXI_LITE_ADDR_
WIDTH-1: 0)
M_AXI_LITE
zeros
m_axi_lite_awprot(2:0)
M_AXI_LITE
000b
m_axi_lite_awvalid
m_axi_lite_awready
M_AXI_LITE
M_AXI_LITE
M_AXI_LITE
zeros
m_axi_lite_wstrb
(C_M_AXI_LITE_DATA_
WIDTH/8 - 1: 0)
M_AXI_LITE
1111b
AXI Master Lite Write Data Channel Write Strobe Bus. All
strobe bytes asserted for SG write address channel
transfer requests.
m_axi_lite_wvalid
m_axi_lite_wready
M_AXI_LITE
M_AXI_LITE
m_axi_lite_bresp(1:0)
m_axi_lite_bvalid
m_axi_lite_bready
M_AXI_LITE
M_AXI_LITE
M_AXI_LITE
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Interface
Signal
Init
Type Status
Description
IPIC
IPIC
IPIC
IP2Bus_Mst_BE(C_M_AXI_L
ITE_DATA_
WIDTH/8 - 1: 0)
IPIC
IP2Bus_Mst_Lock
IPIC
IP2Bus_Mst_Reset
IPIC
Bus2IP_Mst_CmdAck
IPIC
Bus2IP_Mst_Cmplt
IPIC
Bus2IP_Mst_Error
IPIC
Bus2IP_Mst_Rearbitrate
IPIC
Bus2IP_Mst_Timeout
IPIC
IPIC
zeros
Bus2IP_MstRd_src_rdy_n
IPIC
Bus2IP_MstWr_dst_rdy_n
IPIC
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Design Parameters
The AXI Master Lite design parameters are described in Table 2.
Table 2: AXI Master Lite Design Parameter Description
Feature/Description
Parameter Name
Allowable
Values
Default
Values
VHDL Type
virtex6
String
32
32
integer
32
32
integer
C_FAMILY
virtex6,
spartan6
C_M_AXI_LITE_ADDR_WIDTH
Affects Signal
Depends on
Parameter
Relationship Description
C_M_AXI_LITE_DATA_
WIDTH
m_axi_lite_rdata
m_axi_lite_wdata
m_axi_lite_wstrb
IP2Bus_Mst_BE
Bus2IP_MstRd_d
IP2Bus_MstWr_d
C_M_AXI_LITE_ADDR_
WIDTH
m_axi_lite_awaddr
m_axi_lite_araddr
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Parameter Descriptions
C_FAMILY
Type: String
Definition: Indicates the target FPGA device family for the design
Description: This parameter is set by the EDK tools to a value reflecting the FPGA device family selected for
the EDK project.
C_M_AXI_LITE_ADDR_WIDTH
Type: Integer
Definition: Address bus width of attached AXI on the AXI AXI Master Lite interface
Description: This integer parameter is used to size the Read Address and Write Address Channels of the AXI
Master Lite AXI4 Interface. The EDK tool suite will assign this parameter a fixed value of 32.
C_M_AXI_LITE_DATA_WIDTH
Type: Integer
Definition: Read Data bus width of attached AXI4 on the AXI Master Lite interface
Description: This integer parameter is used to size the Read Data and Write Data Channels of the AXI Master
Lite interface. The EDK tool suite will assign this parameter a fixed value of 32.
Clocking
AXI Master Lite uses a single clock for logic synchronization. This clock is input on the m_axi_lite_aclk input
port. All interfaces for the core are required to be synchronized to this clock. The AXI Master Lite has been
simulation tested with an m_axi_lite_aclk frequency range of 10 MHz to 200 MHz. Actual Fmax achieved in a
hardware implementation may vary. See Performance for more details.
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Resets
An active low reset assertion on the AXI Master Lite m_axi_lite_aresetn input will reset the entire AXI Master
Lite core. This is considered a hardware reset, and there are no graceful completions of AXI4 transfers in progress.
A hardware reset initializes all AXI Master Lite internal logic to power on conditions. It is required that the
m_axi_lite_aresetn input is synchronous to the m_axi_lite_aclk master clock input and is asserted for the
minimum number of clocks stated in Table 4. Table 4 also indicates the stabilization time for AXI Master Lite
outputs reacting to a reset condition.
Table 4: Reset Assertion/Deassertion Stabilization Times
Description
Value
Applicable Signal
8 clocks
(m_axi_lite_aclk)
axi_resetn input
3 clocks
(m_axi_lite_aclk)
3 clocks
(m_axi_lite_aclk)
Performance
The targeted design clock frequencies of AXI Master Lite for the Spartan-6 and Virtex-6 FPGA families are shown
below. The maximum achievable clock frequency and resource utilization estimates may be different from those
shown due to tool options, FPGA speed and logic utilization, and other factors.
The target FPGA was filled with logic to drive the LUT and BRAM utilization to approximately 70% and the I/O
utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target FPGA,
the data shown in Table 5 was obtained.
Table 5: System Performance
Target FPGA
XC6SLX45t
AXI4-Lite
MicroBlaze
90
120
80
135
180
135
(1)
XC6VLX240T
(2)
Notes:
1.
2.
Spartan-6 FPGA LUT utilization: 70%; block RAM utilization: 70%; IO utilization: 80%; MicroBlaze processor not AXI4
interconnect; AXI4 interconnect configured with a single clock of 120 MHz.
Virtex-6 FPGA LUT utilization: 70%; block RAM utilization: 70%; IO utilization: 80%.
Throughput
The AXI Master Lite only performs single data beat transfers of 1 to 4 bytes. It is not designed for high throughput
applications. A typical read or write operation should take four m_axi_lite_aclk clock cycles from
IP2Bus_MstRd_Req or IP2Bus_MstWr_Req assertion to Bus2IP_Mst_Cmplt assertion.
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10
0ns
100ns
200ns
300ns
400ns
m_axi_lite_aclk
m_axi_lite_aresetn
m_axi_lite_arvalid
m_axi_lite_arready
m_axi_lite_arprot[2:0]
m_axi_lite_araddr[31:0]
0
10000004
10000002
m_axi_lite_rvalid
m_axi_lite_rready
m_axi_lite_rresp[1:0]
m_axi_lite_rdata[31:0]
76543210
22221111
m_axi_lite_awvalid
m_axi_lite_awready
m_axi_lite_awprot[2:0]
m_axi_lite_awaddr[31:0]
10000004
10000000
m_axi_lite_wvalid
m_axi_lite_wready
m_axi_lite_wstrb[3:0]
m_axi_lite_wdata[31:0]
m_axi_lite_bresp[1:0]
m_axi_lite_bready
m_axi_lite_bvalid
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Addr
10000002
10000004
IP2Bus_Mst_BE
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
Bus2IP_MstRd_d[31:0]
22221111
76543210
Bus2IP_MstRd_src_rdy_n
IP2Bus_MstWr_d
Bus2IP_MstWr_dst_rdy_n
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11
0ns
100ns
200ns
300ns
400ns
500ns
m_axi_lite_aclk
m_axi_lite_aresetn
m_axi_lite_arvalid
m_axi_lite_arready
m_axi_lite_arprot[2:0]
m_axi_lite_araddr[31:0]
0
10000002
10000000
m_axi_lite_rvalid
m_axi_lite_rready
m_axi_lite_rresp[1:0]
m_axi_lite_rdata[31:0]
m_axi_lite_awvalid
m_axi_lite_awready
m_axi_lite_awprot[2:0]
m_axi_lite_awaddr[31:0]
0
10000002
10000000
m_axi_lite_wvalid
m_axi_lite_wready
m_axi_lite_wstrb[3:0]
m_axi_lite_wdata[31:0]
76543210
m_axi_lite_bresp[1:0]
22221111
m_axi_lite_bready
m_axi_lite_bvalid
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Addr
IP2Bus_Mst_BE
10000000
3
10000004
C
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
Bus2IP_MstRd_d[31:0]
Bus2IP_MstRd_src_rdy_n
IP2Bus_MstWr_d
76543210
22221111
Bus2IP_MstWr_dst_rdy_n
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12
0ns
100ns
200ns
300ns
400ns
m_axi_lite_aclk
m_axi_lite_aresetn
md_error
m_axi_lite_arvalid
m_axi_lite_arready
m_axi_lite_arprot[2:0]
m_axi_lite_araddr[31:0]
1
10000002
m_axi_lite_rvalid
m_axi_lite_rready
m_axi_lite_rresp[1:0]
m_axi_lite_rdata[31:0]
76543210
m_axi_lite_awvalid
m_axi_lite_awready
m_axi_lite_awprot[2:0]
m_axi_lite_awaddr[31:0]
10000000
m_axi_lite_wvalid
m_axi_lite_wready
m_axi_lite_wstrb[3:0]
m_axi_lite_wdata[31:0]
m_axi_lite_bresp[1:0]
m_axi_lite_bready
m_axi_lite_bvalid
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Addr
10000002
IP2Bus_Mst_BE
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
Bus2IP_MstRd_d[31:0]
76543210
Bus2IP_MstRd_src_rdy_n
IP2Bus_MstWr_d
Bus2IP_MstWr_dst_rdy_n
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13
0ns
100ns
200ns
300ns
400ns
500ns
m_axi_lite_aclk
m_axi_lite_aresetn
md_error
m_axi_lite_arvalid
m_axi_lite_arready
m_axi_lite_arprot[2:0]
m_axi_lite_araddr[31:0]
0
10000002
m_axi_lite_rvalid
m_axi_lite_rready
m_axi_lite_rresp[1:0]
m_axi_lite_rdata[31:0]
m_axi_lite_awvalid
m_axi_lite_awready
m_axi_lite_awprot[2:0]
m_axi_lite_awaddr[31:0]
0
10000002
m_axi_lite_wvalid
m_axi_lite_wready
m_axi_lite_wstrb[3:0]
m_axi_lite_wdata[31:0]
22221111
m_axi_lite_bresp[1:0]
m_axi_lite_bready
m_axi_lite_bvalid
IP2Bus_MstRd_Req
IP2Bus_MstWr_Req
IP2Bus_Mst_Addr
IP2Bus_Mst_BE
10000002
C
IP2Bus_Mst_Lock
IP2Bus_Mst_Reset
Bus2IP_Mst_CmdAck
Bus2IP_Mst_Cmplt
Bus2IP_Mst_Error
Bus2IP_Mst_Rearbitrate
Bus2IP_Mst_Cmd_Timeout
Bus2IP_MstRd_d[31:0]
Bus2IP_MstRd_src_rdy_n
IP2Bus_MstWr_d
22221111
Bus2IP_MstWr_dst_rdy_n
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Resource Utilization
Resource utilization numbers for the AXI Master Lite core are shown for the Spartan-6 FPGA family in Table 6 and
the Virtex-6 FPGA family in Table 7. These values have been generated using the Xilinx EDK and ISE tools for
version 13.1.
Table 6: Spartan-6 FPGA Resource Estimates
C_M_AXI_DATA_WIDTH
C_M_AXI_ADDR_WIDTH
Slices
Slice Reg
Slice LUTs
Block RAM
32
32
38
127
59
C_M_AXI_ADDR_WIDTH
Slices
Slice Reg
Slice LUTs
Block RAM
32
32
36
125
30
Support
Xilinx provides technical support for this LogiCORE IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE IP modules and software, please contact your
local Xilinx sales representative.
Reference Documents
The following document contains reference information important to understanding the design:
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15
List of Acronyms
Acronym
Spelled Out
AXI
EDK
FF
Flip-Flop
FPGA
I/O
Input/Output
IP
Intellectual Property
LUT
Lookup Table
MHz
Mega Hertz
R/W
Read/Write
RAM
HW
Hardware
SW
Software
VHDL
VHSIC Hardware Description Language (VHSIC an acronym for Very High-Speed Integrated Circuits)
XPS
XST
Revision History
The following table shows the revision history for this document:
Date
Version
Description of Revisions
03/01/11
1.0
06/22/11
2.0
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