Internal Instructions

For high-speed vector operations, a full implementation of the architecture is endowed with a set
of 64 integer ALUs and a set of 64 floating-point ALUs. To permit them to be used for
superscalar processing as well, each ALU is provided with an L1 cache. To build on these
elements with as little additional circuitry as possible to create 64 processors capable of
operating independently, giving each processor its own register file in addition to the L1 cache
was avoided, permitting a very simple and regular instruction format, which is shown below:

The first 128 of the eight-bit opcodes defined for use by the sixty-four small processors which
handle this simple two-address memory-to-memory instruction set are as follows:

00000 00001 00010 00011 00100 00101 00110 00111

MVB IB MVH IH MV I MVL 000
CB UCB CH UCH C UC CL UCL 001
LIB ULB LIH ULH LI UL LIL 010
STIB XB STIH XH STI X STIL XL 011
AB NB AH NH A N AL NL 100
SB OB SH OH S O SL OL 101
MB MEB MH MEH M ME ML MEL 110
DB DEB DH DEH D DE DL DEL 111

01000 01001 01010 01011 01100 01101 01110 01111

LSBU MVF MEU MVD MEUD MVQ MEUQ 000
CF DEU CD DEUD CQ DEUQ 001
LSBSM LIF LID LIQ 010
CCN STIF STID STIQ 011
LDBU AF AU AD AUD AQ AUQ 100
SF SU SD SUD SQ SUQ 101
LDBSM MF MU MD MUQ MQ MUQ 110
CCT DF DU DD DUD DQ DUQ 111

As there are no registers, the swap instructions have been removed; as there
are therefore no index registers, a Load Indirect instruction and a Store
Indirect instruction have been added. These instructions take a half word
value as a source argument, which then points to the value used as the
source argument of the load or store. Also, as the instructions are memory-
to-memory instructions, the regular load and store instructions are replaced
by a Move instruction.

The quadruple-precision floating-point instructions shown here may not

necessarily be provided. While it is useful to have 128-bit floating-point
arithmetic available, this is a luxury feature, not a basic one, that would
likely see only limited use even in the applications that do require it. Thus,
128-bit floating-point may be provided in the main ALU, and in the ALU for
short vector operations, but not in the bank of sixty-four ALUs used to
accelerate long vector operations.

Note, however, that this does not mean that long vector quad-precision
floating point instructions would also be omitted. The original Cray
computers with operations similar to the long vector instructions, although
they had groups of 64 registers, did not have groups of 64 ALUs, they
instead relied on a single pipelined ALU. Of course, this would mean that long
vector operations on quadruple precision values would no longer be
comparable in speed to long vector operations on double precision values.

Other Instructions

The conditional jump instructions are:

C1000xxx JL Jump if Low
C2000xxx JE Jump if Equal
C3000xxx JLE Jump if Low or Equal
C4000xxx JH Jump if High
C5000xxx JNE Jump if Not Equal
C6000xxx JHE Jump if High or Equal
C7000xxx JNV Jump if No Overflow
C8000xxx JV Jump if Overflow

CA000xxx JC Jump if Carry

CB000xxx JNC Jump if No Carry

CF000xxx JMP Jump

here noted in hexadecimal form rather than octal form, due to the arrangement of the internal
instructions.

As well, a subroutine jump instruction, and a jump indirect instruction, useful for returning from
a subroutine, are provided:

C0rrrxxx JSB Jump to Subroutine

CE000xxx JI Jump Indirect

The Jump to Subroutine instruction transfers control to the location which is its source operand,
and stores the return address in the halfword which is its destination operand. The Jump Indirect
instruction finds the address to which to transfer control in the halfword that is its source
operand.
The shift instructions are:
E00nnxxx SHLB Shift Left Byte
E10nnxxx SHRB Shift Right Byte

E30nnxxx ASRB Arithmetic Shift Right Byte

E40nnxxx ROLB Rotate Left Byte
E50nnxxx RORB Rotate Right Byte
E60nnxxx RLCB Rotate Left through Carry Byte
E70nnxxx RRCB Rotate Right through Carry Byte

E80nnxxx SHLH Shift Left Halfword

E90nnxxx SHRH Shift Right Halfword

EB0nnxxx ASRH Arithmetic Shift Right Halfword

EC0nnxxx ROLH Rotate Left Halfword
ED0nnxxx RORH Rotate Right Halfword
EE0nnxxx RLCH Rotate Left through Carry Halfword
EF0nnxxx RRCH Rotate Right through Carry Halfword
F00nnxxx SHL Shift Left
F10nnxxx SHR Shift Right

F30nnxxx ASR Arithmetic Shift Right

F40nnxxx ROL Rotate Left
F50nnxxx ROR Rotate Right
F60nnxxx RLC Rotate Left through Carry
F70nnxxx RRC Rotate Right through Carry
F80nnxxx SHLL Shift Left Long
F90nnxxx SHRL Shift Right Long

FB0nnxxx ASRL Arithmetic Shift Right Long

FC0nnxxx ROLL Rotate Left Long
FD0nnxxx RORL Rotate Right Long
FE0nnxxx RLCL Rotate Left through Carry Long
FF0nnxxx RRCL Rotate Right through Carry Long

The shift count is placed in the source address field, the memory location
whose contents are to be shifted is identified in the destination address field.
 Reported By: Erwin and
Rolando