.include "nominal.

jsim"
.include "stdcell.jsim"
.include "lab3checkoff_10.jsim"
.subckt FA a b ci s co
Xxor1 a b 1 xor2
Xxor2 1 ci s xor2
Xnand21 a b 2 nand2
Xnand22 a ci 3 nand2
Xnand23 b ci 4 nand2
Xnand3 2 3 4 co nand3
.ends
.subckt adder30 a[29:0] b[29:0] cin s[29:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:29] b[1:29] c[0:28] s[1:29] c[1:29] FA
.ends
.subckt adder29 a[28:0] b[28:0] cin s[28:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:28] b[1:28] c[0:27] s[1:28] c[1:28] FA
.ends
.subckt adder28 a[27:0] b[27:0] cin s[27:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:27] b[1:27] c[0:26] s[1:27] c[1:27] FA
.ends
.subckt adder27 a[26:0] b[26:0] cin s[26:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:26] b[1:26] c[0:25] s[1:26] c[1:26] FA
.ends
.subckt adder26 a[25:0] b[25:0] cin s[25:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:25] b[1:25] c[0:24] s[1:25] c[1:25] FA
.ends
.subckt adder25 a[24:0] b[24:0] cin s[24:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:24] b[1:24] c[0:23] s[1:24] c[1:24] FA
.ends
.subckt adder24 a[23:0] b[23:0] cin s[23:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:23] b[1:23] c[0:22] s[1:23] c[1:23] FA
.ends
.subckt adder23 a[22:0] b[22:0] cin s[22:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:22] b[1:22] c[0:21] s[1:22] c[1:22] FA
.ends
.subckt adder22 a[21:0] b[21:0] cin s[21:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:21] b[1:21] c[0:20] s[1:21] c[1:21] FA
.ends
.subckt adder21 a[20:0] b[20:0] cin s[20:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA

Xbit1 a[1:20] b[1:20] c[0:19] s[1:20] c[1:20] FA

.ends
.subckt adder20 a[19:0] b[19:0] cin s[19:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:19] b[1:19] c[0:18] s[1:19] c[1:19] FA
.ends
.subckt adder19 a[18:0] b[18:0] cin s[18:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:18] b[1:18] c[0:17] s[1:18] c[1:18] FA
.ends
.subckt adder18 a[17:0] b[17:0] cin s[17:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:17] b[1:17] c[0:16] s[1:17] c[1:17] FA
.ends
.subckt adder17 a[16:0] b[16:0] cin s[16:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:16] b[1:16] c[0:15] s[1:16] c[1:16] FA
.ends
.subckt adder16 a[15:0] b[15:0] cin s[15:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:15] b[1:15] c[0:14] s[1:15] c[1:15] FA
.ends
.subckt adder15 a[14:0] b[14:0] cin s[14:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:14] b[1:14] c[0:13] s[1:14] c[1:14] FA
.ends
.subckt adder14 a[13:0] b[13:0] cin s[13:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:13] b[1:13] c[0:12] s[1:13] c[1:13] FA
.ends
.subckt adder13 a[12:0] b[12:0] cin s[12:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:12] b[1:12] c[0:11] s[1:12] c[1:12] FA
.ends
.subckt adder12 a[11:0] b[11:0] cin s[11:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:11] b[1:11] c[0:10] s[1:11] c[1:11] FA
.ends
.subckt adder11 a[10:0] b[10:0] cin s[10:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:10] b[1:10] c[0:9] s[1:10] c[1:10] FA
.ends
.subckt adder10 a[9:0] b[9:0] cin s[9:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:9] b[1:9] c[0:8] s[1:9] c[1:9] FA
.ends
.subckt adder9 a[8:0] b[8:0] cin s[8:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA

Xbit1 a[1:8] b[1:8] c[0:7] s[1:8] c[1:8] FA

.ends
.subckt adder8 a[7:0] b[7:0] cin s[7:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:7] b[1:7] c[0:6] s[1:7] c[1:7] FA
.ends
.subckt adder7 a[6:0] b[6:0] cin s[6:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:6] b[1:6] c[0:5] s[1:6] c[1:6] FA
.ends
.subckt adder6 a[5:0] b[5:0] cin s[5:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:5] b[1:5] c[0:4] s[1:5] c[1:5] FA
.ends
.subckt adder5 a[4:0] b[4:0] cin s[4:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:4] b[1:4] c[0:3] s[1:4] c[1:4] FA
.ends
.subckt adder4 a[3:0] b[3:0] cin s[3:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:3] b[1:3] c[0:2] s[1:3] c[1:3] FA
.ends
.subckt adder3 a[2:0] b[2:0] cin s[2:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1:2] b[1:2] c[0:1] s[1:2] c[1:2] FA
.ends
.subckt adder2 a[1:0] b[1:0] cin s[1:0]
Xbit0 a[0] b[0] cin s[0] c[0] FA
Xbit1 a[1] b[1] c[0] s[1] c[1] FA
.ends
.subckt adder32 ALUFN[0] a[31:0] b[31:0] s[31:0] z v n
Xxor b[31:0] ALUFN[0]#32 Xb[31:0] xor2
Xadder0 a[0] Xb[0] ALUFN[0] s[0] c[0] FA
Xadder1 a[31:1] Xb[31:1] c[30:0] s[31:1] c[31:1] FA
Xnor0 s[7:0] s[15:8] s[23:16] s[31:24] f[7:0] nor4
Xand0 f[1:0] f[3:2] f[5:4] f[7:6] w[1:0] and4
Xand1 w[0] w[1] z and2
Xinv s[31] si inverter
Xand2 a[31] Xb[31] si v1 and3
Xnor1 a[31] Xb[31] v2 nor2
Xand3 v2 s[31] v3 and2
Xor v1 v3 v or2
Xbuffer s[31] n buffer
.ends
.subckt compare32 ALUFN[2:1] z v n cmp[31:0]
.connect 0 cmp[31:1]
Xbuffer z 1 buffer
Xxor n v 3 xor2
Xor 3 z 2 or2
Xmux ALUFN[1] ALUFN[2] 0 1 3 2 cmp[0] mux4
.ends

.subckt boole32 ALUFN[3:0] A[31:0] B[31:0] boole[31:0]

Xmux A[31:0] B[31:0] ALUFN[0]#32 ALUFN[1]#32 ALUFN[2]#32 ALUFN[3]#32 boole[31:0]
mux4
.ends
.subckt shift32 ALUFN[1:0] A[31:0] B[4:0] shift[31:0]
* shift left
Xtop4 B[4]#16 A[31:16] A[15:0] W[31:16] mux2
Xbtm4 B[4]#16 A[15:0] 0#16 W[15:0] mux2
Xtop3 B[3]#24 W[31:8] W[23:0] X[31:8] mux2
Xbtm3 B[3]#8 W[7:0] 0#8 X[7:0] mux2
Xtop2 B[2]#28 X[31:4] X[27:0] Y[31:4] mux2
Xbtm2 B[2]#4 X[3:0] 0#4 Y[3:0] mux2
Xtop1 B[1]#30 Y[31:2] Y[29:0] Z[31:2] mux2
Xbtm1 B[1]#2 Y[1:0] 0#2 Z[1:0] mux2
Xtop0 B[0]#31 Z[31:1] Z[30:0] SL[31:1] mux2
Xbtm0 B[0] Z[0] 0 SL[0] mux2
* shift right
* reverse bits inside and reverse bits outside
XtopE B[4]#16 A[0:15] A[16:31] C[31:16] mux2
XbtmE B[4]#16 A[16:31] 0#16 C[15:0] mux2
XtopD B[3]#24 C[31:8] C[23:0] D[31:8] mux2
XbtmD B[3]#8 C[7:0] 0#8 D[7:0] mux2
XtopC B[2]#28 D[31:4] D[27:0] E[31:4] mux2
XbtmC B[2]#4 D[3:0] 0#4 E[3:0] mux2
XtopB B[1]#30 E[31:2] E[29:0] F[31:2] mux2
XbtmB B[1]#2 E[1:0] 0#2 F[1:0] mux2
XtopA B[0]#31 F[31:1] F[30:0] SR[31:1] mux2
XbtmA B[0] F[0] 0 SR[0] mux2
* shift right with sign
Xtop9 B[4]#16 A[0:15] A[16:31] G[31:16] mux2
Xbtm9 B[4]#16 A[16:31] A[31]#16 G[15:0] mux2
Xtop8 B[3]#24 G[31:8] G[23:0] H[31:8] mux2
Xbtm8 B[3]#8 G[7:0] A[31]#8 H[7:0] mux2
Xtop7 B[2]#28 H[31:4] H[27:0] I[31:4] mux2
Xbtm7 B[2]#4 H[3:0] A[31]#4 I[3:0] mux2
Xtop6 B[1]#30 I[31:2] I[29:0] J[31:2] mux2
Xbtm6 B[1]#2 I[1:0] A[31]#2 J[1:0] mux2
Xtop5 B[0]#31 J[31:1] J[30:0] SRA[31:1] mux2
Xbtm5 B[0] J[0] A[31] SRA[0] mux2
* final mux
Xmux ALUFN[0]#32 ALUFN[1]#32 SL[31:0] SR[0:31] 0#32 SRA[0:31] shift[31:0] mux4
.ends
/*
32 levels of AND gates
D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S,T,U,V,W,X,Y,Z,AZ,BY,CX,DW,EV,FU,GT,HS,IR
*/
.subckt mult32 ALUFN[1:0] A[31:0] B[31:0] mult[31:0]
Xand A[0] B[0] mult[0] and2
Xand0 A[31:1] B[0]#31 D[31:1] and2
Xand1 A[30:0] B[1]#31 E[30:0] and2
Xand2 A[29:0] B[2]#30 F[29:0] and2
Xand3 A[28:0] B[3]#29 G[28:0] and2
Xand4 A[27:0] B[4]#28 H[27:0] and2
Xand5 A[26:0] B[5]#27 I[26:0] and2

Xand6 A[25:0] B[6]#26 J[25:0] and2

Xand7 A[24:0] B[7]#25 K[24:0] and2
Xand8 A[23:0] B[8]#24 L[23:0] and2
Xand9 A[22:0] B[9]#23 M[22:0] and2
Xand10 A[21:0] B[10]#22 N[21:0] and2
Xand11 A[20:0] B[11]#21 O[20:0] and2
Xand12 A[19:0] B[12]#20 P[19:0] and2
Xand13 A[18:0] B[13]#19 Q[18:0] and2
Xand14 A[17:0] B[14]#18 R[17:0] and2
Xand15 A[16:0] B[15]#17 S[16:0] and2
Xand16 A[15:0] B[16]#16 T[15:0] and2
Xand17 A[14:0] B[17]#15 U[14:0] and2
Xand18 A[13:0] B[18]#14 V[13:0] and2
Xand19 A[12:0] B[19]#13 W[12:0] and2
Xand20 A[11:0] B[20]#12 X[11:0] and2
Xand21 A[10:0] B[21]#11 Y[10:0] and2
Xand22 A[9:0] B[22]#10 Z[9:0] and2
Xand23 A[8:0] B[23]#9 AZ[8:0] and2
Xand24 A[7:0] B[24]#8 BY[7:0] and2
Xand25 A[6:0] B[25]#7 CX[6:0] and2
Xand26 A[5:0] B[26]#6 DW[5:0] and2
Xand27 A[4:0] B[27]#5 EV[4:0] and2
Xand28 A[3:0] B[28]#4 FU[3:0] and2
Xand29 A[2:0] B[29]#3 GT[2:0] and2
Xand30 A[1:0] B[30]#2 HS[1:0] and2
Xand31 A[0] B[31] IR and2
/*
30 levels of ripple adder-lines
ABC,BCD,CDE,DEF,EFG,FGH,GHI,HIJ,IJK,JKL,KLM,LMN,MNO,NOP,OPQ,PQR,QRS,RST,STU,TUV,
UVW,VWX,WXY,XYZ,YZA,ZAB,ACB,BDC,CED,DFE
*/
Xadd0 D[1] E[0] 0 mult[1] c0 FA
XaddA D[31:2] E[30:1] c0 ABC[30:1] adder30
Xadd1 ABC[1] F[0] 0 mult[2] c1 FA
XaddB ABC[30:2] F[29:1] c1 BCD[29:1] adder29
Xadd2 BCD[1] G[0] 0 mult[3] c2 FA
XaddC BCD[29:2] G[28:1] c2 CDE[28:1] adder28
Xadd3 CDE[1] H[0] 0 mult[4] c3 FA
XaddD CDE[28:2] H[27:1] c3 DEF[27:1] adder27
Xadd4 DEF[1] I[0] 0 mult[5] c4 FA
XaddE DEF[27:2] I[26:1] c4 EFG[26:1] adder26
Xadd5 EFG[1] J[0] 0 mult[6] c5 FA
XaddF EFG[26:2] J[25:1] c5 FGH[25:1] adder25
Xadd6 FGH[1] K[0] 0 mult[7] c6 FA
XaddG FGH[25:2] K[24:1] c6 GHI[24:1] adder24
Xadd7 GHI[1] L[0] 0 mult[8] c7 FA
XaddH GHI[24:2] L[23:1] c7 HIJ[23:1] adder23
Xadd8 HIJ[1] M[0] 0 mult[9] c8 FA
XaddI HIJ[23:2] M[22:1] c8 IJK[22:1] adder22
Xadd9 IJK[1] N[0] 0 mult[10] c9 FA
XaddJ IJK[22:2] N[21:1] c9 JKL[21:1] adder21
Xadd10 JKL[1] O[0] 0 mult[11] c10 FA
XaddK JKL[21:2] O[20:1] c10 KLM[20:1] adder20
Xadd11 KLM[1] P[0] 0 mult[12] c11 FA
XaddL KLM[20:2] P[19:1] c11 LMN[19:1] adder19
Xadd12 LMN[1] Q[0] 0 mult[13] c12 FA
XaddM LMN[19:2] Q[18:1] c12 MNO[18:1] adder18
Xadd13 MNO[1] R[0] 0 mult[14] c13 FA
XaddN MNO[18:2] R[17:1] c13 NOP[17:1] adder17
Xadd14 NOP[1] S[0] 0 mult[15] c14 FA

XaddO NOP[17:2] S[16:1] c14 OPQ[16:1] adder16

Xadd15 OPQ[1] T[0] 0 mult[16] c15 FA
XaddP OPQ[16:2] T[15:1] c15 PQR[15:1] adder15
Xadd16 PQR[1] U[0] 0 mult[17] c16 FA
XaddR PQR[15:2] U[14:1] c16 QRS[14:1] adder14
Xadd17 QRS[1] V[0] 0 mult[18] c17 FA
XaddS QRS[14:2] V[13:1] c17 RST[13:1] adder13
Xadd18 RST[1] W[0] 0 mult[19] c18 FA
XaddT RST[13:2] W[12:1] c18 STU[12:1] adder12
Xadd19 STU[1] X[0] 0 mult[20] c19 FA
XaddU STU[12:2] X[11:1] c19 TUV[11:1] adder11
Xadd20 TUV[1] Y[0] 0 mult[21] c20 FA
XaddV TUV[11:2] Y[10:1] c20 UVW[10:1] adder10
Xadd21 UVW[1] Z[0] 0 mult[22] c21 FA
XaddW UVW[10:2] Z[9:1] c21 VWX[9:1] adder9
Xadd22 VWX[1] AZ[0] 0 mult[23] c22 FA
XaddX VWX[9:2] AZ[8:1] c22 WXY[8:1] adder8
Xadd23 WXY[1] BY[0] 0 mult[24] c23 FA
XaddY WXY[8:2] BY[7:1] c23 XYZ[7:1] adder7
Xadd24 XYZ[1] CX[0] 0 mult[25] c24 FA
XaddZ XYZ[7:2] CX[6:1] c24 YZA[6:1] adder6
Xadd25 YZA[1] DW[0] 0 mult[26] c25 FA
XaddA1 YZA[6:2] DW[5:1] c25 ZAB[5:1] adder5
Xadd26 ZAB[1] EV[0] 0 mult[27] c26 FA
XaddB2 ZAB[5:2] EV[4:1] c26 ACB[4:1] adder4
Xadd27 ACB[1] FU[0] 0 mult[28] c27 FA
XaddC3 ACB[4:2] FU[3:1] c27 BDC[3:1] adder3
Xadd28 BDC[1] GT[0] 0 mult[29] c28 FA
XaddD4 BDC[3:2] GT[2:1] c28 CED[2:1] adder2
Xadd29 CED[1] HS[0] 0 mult[30] c29 FA
XaddE5 CED[2] HS[1] c29 DFE c30 FA
Xadd30 DFE IR 0 mult[31] c31 FA
.ends
.subckt alu ALUFN[5:0] A[31:0] B[31:0] alu[31:0] z v n
Xadder ALUFN[0] A[31:0] B[31:0] S[31:0] z v n adder32
Xmult ALUFN[1:0] A[31:0] B[31:0] mult[31:0] mult32
Xcomp ALUFN[2:1] z v n cmp[31:0] compare32
Xboole ALUFN[3:0] A[31:0] B[31:0] boole[31:0] boole32
Xshift ALUFN[1:0] A[31:0] B[4:0] shift[31:0] shift32
Xmux ALUFN[1]#32 S[31:0] mult[31:0] out[31:0] mux2
Xmux1 ALUFN[4]#32 ALUFN[5]#32 out[31:0] boole[31:0] shift[31:0] cmp[31:0] alu[31
:0] mux4
.ends