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1011
X 1101
1011
0000
1011
1011
10001111
Simplifying Multiplication
1. The processor can keep a
running product rather than
summing at the end.
2. For each 1 in the multiplier
we can apply an add and a
shift.
ALTERNATIVE:
--- BOOTH ALGORITHM
Multiplicand M unchanged
Based upon recoding the multiplier Q
to a recoded value R
Each digit can assume a negative as well as
positive and zero values
Booths Algorithm
1. Multiplier and multiplicand are
placed in Q and M registers.
Performing 7x3
Q-1
M = 0111
0000
1101
initial values
1001
1100
1101
1110
0
1
A A-M
shift
0011
0001
1110
1111
1
0
A
shift
A+M
1010
1101
1111
0111
0
1
A
shift
A-M
1110
1011
shift
Q-1
M = 1001
0000
0011
initial
0111
0011
0011
1001
0
1
A A-M
shift
0001
1100
shift
1010
1101
1100
0110
1
0
A A+M
shift
1110
1011
shift
DIVISION
Dividend/Divisor
Example:
00001101
1011
10010011
1011
001110
1011
001111
1011
0111
Control logic
Block diagram of the implementation
Restoration Method
1.Divisor loaded into Register M
2.Dividend loaded into register Q
3.Initialise register A to Zero
Example: Divide 7 by 3
Dividend : 0111
Divisor : 0011
A
0000
0000
1101
0111
1110
M : 0011
Initial Value
shift left
Sub M
1101
0011
0000
1110
0001
1101
1110
0011
0001
1100
1110
1100
1100
As MSB is 1 set Q0 =0
Add M
Restore A
Shift left
Sub M
As MSB is 1 set Q0= 0
Add M
Restore A
0011
1101
0000
1000
0000
0001
1101
1001
0010
1110
0011
0001
0010
1000
0010
Result Q = 0010
Shift left
Sub M
As MSB 0 set Q0 = 1
Shift left
Sub M
As MSB 1set Q0 = 0
Add M
Restore A
Remainder = 0001
Divide 9 by 3
Dividend = 1001
Divisor = 0011
M = 0011
Non-restoration Method
Eliminates the need for restoring A after the result
of subtraction is negative
7 divided by 3
M 0011
A
0000
0000
1101
1101
1011
0011
1110
Q
0111
1110
1110
1100
1100
initialise
shift left, as MSB is 0
Sub M
as MSB 1, Q0 = 0
shift left, as MSB 1
Add M
as MSB 1 Q0 = 0
1101
0011
1000
0000
0000
0001
1101
1110
0011
1000
1001
0010
as MSB 0
set Q0 =1
shift left as MSB 0
Sub M
as MSB 1
Add to adjust remainder
0010
0001
Q = 0010
R = 0001