Coding Scheme for 3D Vertical Flash Memory

Yongjune Kim , Robert Mateescu, Seung-Hwan Song, Zvonimir Bandic , and B. V. K. Vijaya Kumar

arXiv:1410.8541v2 [cs.IT] 10 Feb 2015

Data

Storage Systems Center (DSSC), Carnegie Mellon University, Pittsburgh, PA, USA
Email: yongjunekim@cmu.edu, kumar@ece.cmu.edu
HGST Research, San Jose, CA, USA
Email: {robert.mateescu, seung-hwan.song, zvonimir.bandic}@hgst.com

AbstractRecently introduced 3D vertical flash memory is

expected to be a disruptive technology since it overcomes scaling
challenges of conventional 2D planar flash memory by stacking
up cells in the vertical direction. However, 3D vertical flash
memory suffers from a new problem known as fast detrapping,
which is a rapid charge loss problem. In this paper, we propose a
scheme to compensate the effect of fast detrapping by intentional
inter-cell interference (ICI). In order to properly control the
intentional ICI, our scheme relies on a coding technique that
incorporates the side information of fast detrapping during
the encoding stage. This technique is closely connected to the
well-known problem of coding in a memory with defective cells.
Numerical results show that the proposed scheme can effectively
address the problem of fast detrapping.

I. I NTRODUCTION
Aggressive scaling down of the device dimension has driven
the continuous growth of flash memory density. However,
the scaling down leads to many challenges such as photolithography limitation, increased inter-cell interference (ICI),
and disturbance [1], [2]. In order to overcome these scaling
challenges, a paradigm shift from the 2-dimensional (2D)
planar structure to the 3D vertical structure is underway. The
change is stacking up cells in the vertical direction instead of
shrinking cells within a 2D plane [2][5].
The recent 3D vertical NAND flash memory with 24 wordline (WL) shows better device characteristics compared to 2D
1x nm planar flash memory [5]. However, 3D vertical flash
memory has a problem of fast detrapping, which is a quick
charge loss phenomenon resulting in larger threshold voltage
variations in programmed cells [5], [6].
The fast detrapping usually occurs in charge trap cells rather
than floating gate cells [5], [6]. Since 3D vertical flash memory
uses charge trap cells such as damascened metal-gate siliconoxide-nitride-oxide-silicon (SONOS) cells for easier 3D integration [3][5], fast detrapping is an important problem of 3D
vertical flash memory. On the other hand, the fast detrapping
does not happen in 2D planar flash memory consisting of
floating gate cells.
In order to cope with fast detrapping, several approaches
have been proposed. These approaches include cell structure
engineering at device level and reprogramming at circuit
level [5], [6]. In this paper, we try to combat the fast detrapping
at coding level. The basic idea is to compensate the charge loss
due to fast detrapping through intentional ICI. Although the
ICI is a well-known adverse effect [7], it can be utilized to
alleviate the effect of the fast detrapping through the proposed

scheme. It is worth mentioning that the proposed scheme at

coding level can cooperate with other approaches at different
levels.
We will formulate the problem of controlling the intentional
ICI into coding in a memory with defective cells model of [8],
which is a notable example of coding with side information
available at the encoder [9]. With this formulation, the additive
encoding schemes in [10], [11] can be applied to control the
intentional ICI.
Recently, coding schemes with the side information available at the encoder have drawn attention for phase change
memories (PCM), write once memories (WOM), and flash
memories [12][14]. In [12], the side information corresponding to the variability of PCM is used at the encoder to reduce
the effect of variability. [13] assumes that the current state
of the memory is known to the encoder for rewriting WOM.
Also, the encoder exploits the side information corresponding
to the ICI of flash memory and reduces the effect of the ICI
in [14]. In this paper, the side information is related to the fast
detrapping of 3D vertical flash memory, and coding with this
side information controls the intentional ICI to compensate the
fast detrapping.
Although the above coding schemes improve the reliability
(i.e., decoding failure probability) by using the side information at the encoder, the write speed performance would be
degraded during the obtaining of the side information and
incorporating this side information into encoding. Note that
soft decision decoding schemes such as low-density parity
check (LDPC) codes in flash memory improve the decoding
failure probability at the expense of decreased read speed due
to multiple read operations needed to obtain soft decision
values. Thus, we can claim that the coding schemes using
side information at the encoder are complementary to the soft
decision decoding schemes.
In memory systems, it is well-known that the read speed
performance is more critical than the write speed performance
since the write operation is typically not on the critical path
because of write buffers in the memory hierarchy and the write
latency can be hidden [12], [15]. Also, the read operations are
required more often than the write operations in many memory
applications. Thus, the coding schemes using side information
at the encoder have an advantage over soft decision decoding
from the perspective of speed performance.
The rest of this paper is organized as follows. Section II
explains the basics of 3D vertical flash memory and the

BL (j)

BL (j+1)

Normalized
cell count

BL (j-1)

S0

S1

WL (i+1) plane

Threshold voltage

SSL (k+1) group

SSL (k) group

WL (i) plane

SSL (k-1) group

(a) Single-level cell (SLC) for B = 1

WL (i-1) plane

Normalized
cell count

(a) Simplified birds eye view of vertical channel type 3D flash memory
cell array

S0

ONO (Oxide-Nitride-Oxide)

S1

S2

S3

Poly-Si channel

Oxide

SSL (k+1) group

Threshold voltage

(b) Multi-level cell (MLC) for B = 2

Fig. 1.

Metal gate

Threshold voltage distribution of flash memory cells.

channel model of 3D vertical flash memory by taking into

account the fast detrapping and the ICI. Section III proposes a
coding scheme that overcomes fast detrapping by controlling
the intentional ICI. After showing the simulation results in
Section IV, we will conclude the paper in Section V.
II. BACKGROUND

AND

C HANNEL M ODEL

A. Basic Operations
In order to store B-bit per cell, each cells threshold voltage
is divided into 2B states, which is similar to pulse amplitude
modulation (PAM). Fig. 1 (a) shows the threshold voltage distribution of 1-bit per cell flash memory, which is traditionally
called single-level cell (SLC). Initially, all memory cells are
erased, so their threshold voltage is in the lowest state S0
(erase state). In order to store data, some of the cells in S0
should be written (programmed) into S1 . For multi-level cell
(MLC) flash memories (i.e., B 2), some of cells in S0 will
be programmed into S1 , . . . , S2B 1 (program states) as shown
in Fig. 1 (b).
The most widely used write operation scheme is the incremental step pulse programming (ISPP) scheme, which was
proposed to maintain a tight threshold voltage distribution for
high reliability [16]. The ISPP is based on repeated program
and verify cycles with the staircase program voltage Vpp . Each
program state associates with a verify level that is used in the
verify operation. During each program and verify cycle, the
cells threshold voltage is boosted by up to the incremental
step voltage Vpp and then compared with the corresponding
verify level. If the threshold voltage of the memory cell
is still lower than the verify level, the program and verify
iteration continues. Otherwise, further programming of this
cell is disabled [16], [17].
The positions of program states are determined by verify
levels and the tightness of each program state depends on
the incremental step voltage Vpp . By reducing Vpp , the
threshold voltage distribution can be made tighter, however
the write time increases [16], [18].
In read operation, the threshold voltages of cells in the
same WL are compared to a given read level. After a read

SSL (k) group

SSL (k-1) group

(b) Cross section diagram along single WL plane

Fig. 2.

3D vertical flash memory cell array in [5].

operation, a page of binary data is transferred to the page

buffer. The binary data shows whether the threshold voltage of
each cell is lower or higher than the given read level. Namely,
the read operation of flash memory is a binary decision.
Conventionally, if a cells threshold voltage is lower than the
given read level, 1 is transferred to the corresponding page
buffer. Otherwise, 0 is transferred to the page buffer.
Hence, multiple read operations are required to obtain a soft
decision value, which lowers the read speed. The degradation
of read speed is an important challenge for soft decision
decoding in flash memories [17].
The threshold voltage of flash memory cell can be reduced
by erase operation. In flash memory, all the memory cells in
the same flash memory block should be erased at the same
time [16]. In addition, the threshold voltage of cell should be
moved into the lowest state S0 by erase operation whereas a
slight increase of threshold voltage is possible by ISPP during
write operation [16].
B. 3D Vertical Flash Memory and ICI
Among various 3D flash memory array architectures, the
vertical channel type architecture having multiple WL planes,
i.e., 3D vertical flash memory has been adopted in [3][5] for
easier 3D integration and better device characteristics. Fig. 2
illustrates the simplified birds eye view of 3D vertical flash
memory cell array in [5] and its cross section diagram along
single WL plane. Note that a string-select-line (SSL) group
in Fig. 2 (a) is equivalent to the 2D planar flash memory cell
array.
In contrast to the 2D planar flash memory where the floating
gate is formed as an electron storage layer upon single crystal
planar silicon channel, the 3D vertical flash memory has a

nitride layer inside oxide-nitride-oxide (ONO) stack which is

grown as a charge trap layer along the circumference of the
thin poly-silicon vertical channel. Note that each charge trap
layer in this 3D vertical flash memory is surrounded by the
metal gates along WL plane.
By taking into account the structure of 3D vertical flash
memories, we will address the ICI of 3D vertical flash memories. In flash memory, the threshold voltage shift of one cell
affects the threshold voltage of its adjacent cell because of
the ICI. The ICI is mainly attributed to parasitic capacitances
coupling effect between adjacent cells [7].
Suppose that V(i,j,k) is the threshold voltage of (i, j, k) cell
which is situated at i-th WL, j-th bit-line (BL), and k-th SSL
as shown in Fig. 2. The threshold voltage shift ICI V(i,j,k) of
the (i, j, k) cell due to the ICI can be given by


ICI V(i,j,k) = WL-to-WL V(i1,j,k) + V(i+1,j,k)


(1)
+ BL-to-BL V(i,j1,k) + V(i,j+1,k)


+ SSL-to-SSL V(i,j,k1) + V(i,j,k+1)
which is an extension of the ICI model of 2D planar flash
memories in [7], [19]. V(i1,j1,k1) in the right hand
side represent the threshold voltage shifts of adjacent cells
after the (i, j, k) cell has been written. Note that WL-to-WL
is coupling ratio between WL plane and adjacent WL plane.
Also, BL-to-BL is coupling ratio between BL and adjacent BL.
Finally, SSL-to-SSL is coupling ratio between SSL group and its
adjacent SSL group. It is worth mentioning that the diagonal
ICIs are neglected since they are very small due to the longer
distance between cells.
Since each charge trap layer in this 3D vertical flash
memory is surrounded by the metal gates along WL plane,
the ICI between adjacent BLs typically found in high density
2D planar flash memory is completely absent in the same WL
plane. Similarly, the ICI between adjacent SSL groups will be
negligible due to the metal gates.
The ICI between adjacent WL planes is also reduced
compared to the conventional 2D planar flash memory since
the charge trap layer in the 3D vertical flash memory is much
thinner than the floating gate layer in the 2D flash memory.
However, the ICI between adjacent WL planes increases as
the distance between WL planes is reduced for the higher cell
density. Thus, it is enough to take into account only the ICI
between adjacent WL planes in the same SSL group and BL.
By setting = WL-to-WL and BL-to-BL = SSL-to-SSL = 0, the
ICI model of (1) will be simplified into


ICI V(i,j,k) = V(i1,j,k) + V(i+1,j,k) .
(2)
C. Fast Detrapping
As mentioned in II-B, nitride charge trap layer is attractive
for integration of the 3D vertical flash memory. However, the
fast detrapping from this trap layer is a critical challenge in
the 3D vertical flash memory [6].
The cause of fast detrapping can be explained by shallowly
trapped electrons in charge trap layers, which immediately

Verify level

S0

Read level

S1

"1"

"0"
Threshold voltage

(a) Threshold voltage distribution of cells in the

i-th WL before fast detrapping
Threshold voltage
distribution after
fast detrapping

Threshold voltage

(b) Threshold voltage distribution of cells in the

i-th WL after fast detrapping
Identify level

Read level

Threshold voltage
Identified cells that suffer
from fast detrapping

(c) Identified cells that suffer from fast detrapping

in the i-th WL
Fig. 3. Fast detrapping and identifying cells that suffer from fast detrapping.

detrap and tunnel out after the programming pulse is terminated [6]. Thus, the charge loss due to fast detrapping
quickly decreases the threshold voltage of corresponding cells
and degrades the threshold voltage distribution, as shown in
Fig. 3 (a) and (b). The fast detrapping occurs immediately
after write operation [6].
The device level approaches such as cell structure and
material could not completely solve this problem [6]. In [5],
a counter-pulse program using self-boosting was proposed
at circuit level, which accelerates fast detrapping before a
verify operation of ISPP such that fast detrapped cells can
be reprogrammed by the subsequent programming pulses.
Nevertheless, fast detrapping can happen again in the later
programming pulses, which requires a different approach at
higher levels such as coding level. Since the approaches at
different levels can coexist, the proposed scheme at coding
level can cooperate with other approaches at lower levels in
combating fast detrapping.
D. Channel Model
A channel model of conventional 2D planar flash memories
can be given by
Y = X + S2D + Z
= X + Zwrite + S2D + Zread
= V + S2D + Zread

(3)
(4)
(5)

where X and Y are the channel input and output. Also, S2D
represents the ICI from adjacent cells in the conventional 2D
planar flash memory. The additive random noise Z is a sum

of Zwrite and Zread where Zwrite is the write noise due to the
initial threshold voltage distribution after erase operation and
the incremental step voltage Vpp of ISPP. Zread is the read
noise due to other noise sources.
Since the write noise Zwrite precedes the ICI S2D , we
consider a random variable V = X + Zwrite . The shifts of V in
adjacent cells determine the ICI S2D . (3) and (4) come from
the flash memory channel model in [14], [20]. The channel
model of (3) was recently validated by experimental results
from the 2x nm 2D planar flash memory in [20].
The 3D vertical flash memory channel model can be extended from the 2D planar flash memory channel model as
follows.
Y = V + S3D + Zread
= V + S3D + Zfast + Zrandom

C(i+1, j) should be "S1"

for intentional ICI
WL (i+1)

C(i+1, j-1)

WL (i)

C(i, j-1)

C(i, j)

C(i, j+1)

Fig. 4. Intentional ICI for compensating fast detrapping. The cell C(i+1,j)
will be regarded as stuck-at 0 (i.e., S1 ) defect for the intentional ICI. (The
index k was omitted for simplicity.)
S

P(S)

P(Y | X, S)

0
0

where Zread = Zfast +Zrandom . Zfast denotes the noise due to fast
detrapping. All the other read noise sources are represented by
Zrandom . In addition, the ICI of the 3D vertical flash memory
is given by S3D . Note that S3D of (i, j, k) cell is the same as
ICI V(i,j,k) of (1) and (2).

0
1
0

1
1

III. P ROPOSED S CHEME

First, the encoder should obtain the side information corresponding to fast detrapping. Fig. 3 (a) shows the threshold voltage distribution before fast detrapping happens. After writing
the i-th WL, some of cells in the i-th WL immediately suffer
from fast detrapping and their threshold voltages decrease as
shown in Fig. 3 (b).
The cells suffering from the fast detrapping can be identified
by two read operations at the read level and the identify
level , as shown in Fig. 3 (c). If a cells threshold voltage is
between and , we can claim that this cell suffers from fast
detrapping and the encoder obtains the location of this cell,
which is the side information about fast detrapping.
If the encoder holds the original data of the i-th WL, we can
obtain this side information of fast detrapping by just one read
operation since we do not need to apply the read operation
at the read level . By combining the original data and the
binary data obtained from the read operation at the identify
level , the encoder can identify the cells suffering from fast
detrapping.
Note that the identify level do not need to be the same
as the verify level . We can change the identify level by

C(i, j) is an identified cell

suffering from fast detrapping

(7)

A. How Does the Encoder Obtain the Side Information?

C(i+1, j+1)

Intentional ICI from C(i+1, j)

(6)

We propose a new scheme at coding level in order to

overcome fast detrapping. Since the proposed scheme will
be explained by the problem of coding with side information
available at the encoder, we should address the following two
questions.
How does the encoder obtain the side information?
How does the encoder use the side information?
We will address these two problems and propose the solutions in the following subsections.

C(i+1, j)

1
1p

1 0 1

p
1

Fig. 5.

1p

Channel model of a memory with defective cells.

taking into account the strength of fast detrapping. The number

of identified cells depend on the identify level .
B. How Does the Encoder Use the Side Information?
Now the encoder knows the side information corresponding
to fast detrapping in cells of the i-th WL. The side information
represents the locations of identified cells, which suffer from
fast detrapping. The next step is to use this side information
during the encoding stage.
The key idea is to compensate the effect of the fast detrapping in the i-th WL by controlling the intentional ICI from
the (i + 1)-th WL. The intentional ICI can compensate the
decrease of threshold voltage due to fast detrapping since the
ICI increases the threshold voltage of the interfered cell. Note
that fast detrapping results in charge loss, which decreases the
corresponding cells threshold voltages.
Assume that a cell C(i,j) in Fig. 4 suffered from fast
detrapping, which has been identified by the read operations
as explained in III-A. If the upper cell C(i+1,j) in the (i + 1)th WL is written into S1 , the ICI from C(i+1,j) will increase
the threshold voltage of C(i,j) during increasing the threshold
voltage of C(i+1,j) from S0 to S1 . If C(i+1,j) is written into
S0 , the threshold voltage of C(i+1,j) remains at the initial erase
state S0 , so the ICI from C(i+1,j) is absent.
Thus, in order to compensate the effect of fast detrapping,
the upper cell C(i+1,j) of the identified cell C(i,j) should be
written into S1 which is mapped into binary data 0 as shown

in Fig. 3 (a). We have to control the intentional ICI to alleviate

the effect of fast detrapping.
We will formulate this problem of controlling the intentional
ICI into coding in a memory with defective cells in [8]. The
problem of coding in a memory with defective cells has been
well studied in literature [8], [10], [11]. A binary memory
cell is called defective if its cell value is stuck-at a particular
value regardless of the channel input. As shown in Fig. 5, this
channel model has the ternary state S {0, 1, }, which will
be the side information of defect. The state S = 0 corresponds
to a stuck-at 0 defect that always outputs a 0 independent of
its input value, the state S = 1 corresponds to a stuck-at 1
defect that always outputs a 1, and the state S = corresponds
to a normal cell that can be modelled by a binary symmetric
channel (BSC) with crossover probability p. The probabilities
of these states are P (S = 0) = 0 , P (S = 1) = 1 , and
P (S = ) = 1 0 1 , respectively. Note that X and Y
represent the channel input and output.
In order to solve the problem of coding in a memory
with defective cells, Tsybakov proposed additive encoding
which masks defects by adding a carefully selected binary
vector [10]. Masking defects is to make a codeword whose
values at the locations of defects match the stuck-at values
at those locations [10], [21], [22]. The additive encoding is a
capacity achieving scheme [11], [23].
Since the cell C(i+1,j) in Fig. 4 should store a binary 0 (i.e.,
S1 ) for the intentional ICI, we will regard this cell C(i+1,j)
as stuck-at 0 defects. Then, the additive encoding tries to
make the codewords element corresponding the cell C(i+1,j)
become 0. After writing the additive encoded codeword into
the (i + 1)-th WL, the ICI from the cell C(i+1,j) increases
the threshold voltage of the cell C(i,j) , which compensates
the threshold voltage decrease of the cell C(i,j) due to fast
detrapping.
In summary, the encoder obtains the locations of identified
cells which are suffering from fast detrapping in the i-th WL
before writing the (i + 1)-th WL. These locations can be
obtained by one or two read operations, which would degrade
the write speed performance. For the intentional ICI, the upper
cells in the (i + 1)-th WL of the identified cell in the i-th
WL will be regarded as stuck-at 0 defects. Note that the side
information of fast detrapping in the i-th WL will be changed
into the side information of defects in the (i + 1)-th WL.
Afterwards, we can harness the intentional ICI by a coding
technique such as additive encoding.
IV. S IMULATION R ESULTS
In this section, the simulation results are presented. The
simulation parameters are summarized in Table. I. The initial
threshold voltage distribution (after erasing a flash memory


block) is assumed to be the Gaussian distribution N 4, 12 .
The ISPP was implemented with the parameters of the verify
level for S1 , i.e., S1 = 1 and the incremental step voltage
Vpp = 1.
The noise due to fast detrapping Z
fast is assumed to be the
2
by taking into account
Gaussian distribution N 0.2, Z
fast

TABLE I
S IMULATION PARAMETERS

Parameters

Values

Bits per cell

Initial threshold voltage
distribution
Verify level for S1
Incremental step voltage
Coupling ratio of (2)
Zfast of (5)
Zrandom of (5)
Read level
Identify level

B = 1 (SLC)


N 4, 12

Additive encoding

S 1 = 1
Vpp = 1
0.1


2
N 0.2, Z
fast


2
N 0, Z
random
=0

[n = 1023, k = 923, l, r]
PBCH codes

TABLE II
A LL P OSSIBLE R EDUNDANCY A LLOCATION C ANDIDATES OF
[n = 1023, k = 923, l, r] PBCH C ODES

Code

Notes

0
1
2
3
4
5
6
7
8
9
10

0
10
20
30
40
50
60
70
80
90
100

100
90
80
70
60
50
40
30
20
10
0

Only correcting random errors

Only masking defects

experimental results in [6]. The random noise due to other

2
.
read noise sources Zrandom is assumed to the N 0, Z
random
For the additive encoding, we use [n = 1023, k = 923, l, r]
partitioned Bose, Chaudhuri, Hocquenghem (PBCH) codes
where n, k, l, and r denote the codeword size, the information
size, the redundancy size for masking defects, and the redundancy size for correcting random errors, respectively. The
PBCH code is a special class of partitioned linear block codes,
which can be designed by a similar method of standard BCH
codes [11]. For the given n = 1023 and k = 923 (i.e., the total
redundancy size is 100), all possible redundancy allocation
candidates of PBCH codes are presented in Table II [24].
Note that l and r are multiples of 10 that is the degree of
Galois field. For the efficient computation complexity, twostep encoding scheme of [22], [24] has been used for encoding
of PBCH codes.
Fig. 6 shows that controlling ICI by additive encoding can
compensate the effect of fast detrapping. After compensating
the fast detrapping by the intentional ICI, the threshold voltage
distribution improves.
Fig. 7 shows that the probability of decoding failure

10

Original threshold voltage distribution

After compensating fast detrapping by ICI

10

10

P (decoding failure)

Normalized cell count

10

10

10

fast

= 0.42

fast

= 0.44

fast

10

10

= 0.40

10

= 0.46

= 0.48

= 0.50

fast

10

fast

fast

10

10

20

Threshold voltage

30

40

50

60

70

80

90

100

Rredundancy for masking defects l

(a) Comparison of P (decoding failure) for different Zfast

Fig. 6.
Comparison of threshold voltage distributions (Zfast = 0.4,
Zrandom = 0.2, = 0.4).

10

10

10

P (decoding failure)

10

P (decoding failure)

10

10

10

10

10

10

10
5

10

= 0.0
= 0.1
= 0.2
= 0.3
= 0.4

10

10

10

20

30

40

50

60

70

80

90

(l, r) = (0, 100)

* *
(l , r )

10

0.4

0.41

0.42

0.43

0.44

0.45

0.46

0.47

Standard deviation of Zfast, Z

0.48

0.49

0.5

fast

100

Rredundancy for masking defects l

Fig. 7. P (decoding failure) for different identify levels (Zfast = 0.4,

Zrandom = 0.2).

P (decoding failure) is improved by the proposed scheme.

If the redundancy for masking l is zero, it means that the
side information of fast detrapping is ignored. Otherwise, the
encoder uses the side information of fast detrapping to improve
P (decoding failure). Note that P (decoding failure) depends
on the identify level since it controls the number of identified
cells, which is equivalent to the number of cells identified
as defects in the upper WL. Also, the optimal redundancy
allocation (l , r ) to minimize P (decoding failure) depends
on the identify level . For larger , the number of cells identified as defects increases, which requires more redundancy
for masking defects during additive encoding. For the given
parameters in Fig. 7, the identify level of = 0.2 minimizes
P (decoding failure).
Fig. 8 shows the improvement of P (decoding failure) by
the proposed scheme for different levels of fast detrapping
Zfast . Note that Zfast changes from 0.4 to 0.5 for the given
Zrandom = 0.2. From Fig. 8 (a), we can obtain the optimal redundancy allocation (l , r ) minimizing P (decoding failure).
It is worth mentioning that the optimal redundancy for masking l increases for larger Zfast . This is because we should allot
more redundancy for masking defects (i.e., compensating the

(b) Comparison of P (decoding failure) for (l = 0, r = 100), (i.e.,

not using any side information) and that for the optimal redundancy
allocation (l , r )
Fig. 8.

P (decoding failure) for different Zfast (Zrandom = 0.2, = 0.2).

fast detrapping) as Zfast increases.

Fig. 8 (b) compares P (decoding failure) for (l, r) =
(0, 100), (i.e., coding without the side information of fast
detrapping) and that for (l , r ) (i.e., coding with the side
information of fast detrapping). By using the side information of fast detrapping, we can significantly improve
P (decoding failure) for different Zfast .
Fig. 9 shows the improvement of P (decoding failure) by the
proposed coding scheme for different random noise Zrandom .
Note that Zrandom changes from 0.2 to 0.3 for the given Zfast =
0.4. From Fig. 9 (a), we can obtain the optimal redundancy
allocation (l , r ) minimizing P (decoding failure). Fig. 9 (b)
compares P (decoding failure) for (l, r) = (0, 100), (i.e.,
coding without the side information of fast detrapping) and
that for (l , r ) (i.e., coding with the side information of fast
detrapping). It is worth mentioning that the improvement of
P (decoding failure) becomes significant as the fast detrapping
Zfast dominates the random noise Zrandom .
V. C ONCLUSION
We proposed a scheme to compensate the effect of fast
detrapping by intentional ICI. The main idea comes from the

10

10

P (decoding failure)

10

10

= 0.20

random

10

= 0.22

random

= 0.24

random

10

= 0.26

= 0.28

= 0.30

random

10

random

random

10

10

20

30

40

50

60

70

80

90

100

Rredundancy for masking defects l

(a) Comparison of P (decoding failure) for different Zrandom

2

10

P (decoding failure)

10

10

10

10

(l, r) = (0, 100)

* *
(l , r )

10

0.2

0.21

0.22

0.23

0.24

0.25

0.26

0.27

Standard deviation of Zrandom, Z

0.28

0.29

0.3

random

(b) Comparison of P (decoding failure) for (l = 0, r = 100), (i.e.,

not using any side information) and that for the optimal redundancy
allocation (l , r )
Fig. 9.

P (decoding failure) for different Zrandom (Zfast = 0.4, = 0.2).

observation that ICI increases the threshold voltage of a cell

whereas fast detrapping decreases the threshold voltage of corresponding cell. Additive encoding can control the intentional
ICI by using the side information of fast detrapping. Although
this paper focused on SLC flash memory, the proposed scheme
can be extended to MLC flash memories.
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