IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 56, NO.

12, DECEMBER 2009

2717

An Analog-Node Model for VHDL-Based

Simulation of RF Integrated Circuits
Martin J. W. Schubert, Member, IEEE

AbstractThis paper describes a very-high-speed integrated-circuit hardware description language (VHDL)-based

analog-node model, an associated driver component for the
mixed-signal event-driven (MixED) simulation technique, and
some primitive device models applied to radio-frequency integrated circuits. With the presented MixED method, analog circuits
are modeled as a composition of controlled sources. Unlike other
VHDL-based analog simulation methods, these MixED sources
compute not only a real number representing an output voltage
but also an output impedance. This allows the outputs of several
MiXED sources to be connected in order to drive the same node
signal . The voltage of this record-type signal is automatically
by resolution functions in compliance
computed at its element
with Kirchhoffs current law. The data structure of the node signal
, its self-defined resolution functions, and an associated driver
component are presented and discussed to meet different simulation requirements, such as speed, versatility, current accuracy,
and adaptive time stepping. Several examples demonstrate how
to behaviorally model mixed-signal components with this method
with an emphasis on the simulation of a heterodyne receiver.
Simulation speeds are compared to VHDL-AMS tools.
Index TermsAnalog, mixed signal, modeling, RF, RF integrated circuit (RFIC), simulation, system on a chip (SoC),
verification, very-high-speed integrated-circuit hardware description language (VHDL).

I. INTRODUCTION
T IS widely accepted that to date, no comprehensive
approach exists for the verification of a complete radio-frequency integrated-circuit (RFIC) design [1][3]. Several
techniques covering time- and frequency-domain methods have
been presented for this purpose (e.g., [1][6]). Muhammad et
al. [1] present a very-high-speed integrated-circuit hardware
description language (VHDL) [7] model and argue that they
do not know a better way to verify, for example, a bit-error
rate (BER) of 2% for an RFIC design, than to simulate a time
span of some billion oscillations of the RF carrier signal with
appropriate noise models. An advantage of simulating VHDL
code is that its synthesizable digital parts can be verified with
respect to functionality, connectivity, and timing of digital control signals applied to analog components, such as switches or
programmable gain stages. VHDL-AMS [8] and Verilog-AMS
[9], the analog and mixed-signal extensions to VHDL and
Verilog [10], respectively, are capable of simulating highly
nonlinear circuits up to some hundred analog nodes [11], [12].

Manuscript received December 08, 2008; revised February 18, 2009. First
published July 14, 2009; current version published January 13, 2010. This paper
was recommended by Associate Editor E. A. M. Klumperink.
The author is with Regensburg University of Applied Sciences, Regensburg
D-93053, Germany (e-mail: martin.schubert@e-technik.fh-regensburg.de).
Digital Object Identifier 10.1109/TCSI.2009.2027799

Fig. 1. Behavioral model of a time-discrete mixed-signal filter usable as multitap direct voltage-sampling mixer (MTDVSM), composed of two networks with
and n .
one free node each, illustrated as thick lines labeled n

The two main reasons for VHDL based or other event-driven

analog and mixed-signal simulation are advantages of cost and
speed as follows.
1) Cost-motivated VHDL analog modeling [13][18].
AMS simulation tools are significantly more expensive
than plain VHDL or Verilog simulators.
Switching to another software environment is laborious,
time consuming, and often accompanied by a loss of
compatibility and/or libraries. Some hardware vendors
(e.g., [19] and [20]) offer special editions of the ModelSim [21] simulator within their software packages.
Large mixed-signal designs are typically developed
by groups that have more VHDL than VHDL-AMS
licenses available. While the latter are inevitable to develop the analog part, behavioral mixed-signal VHDL
models should allow for fast verification of digital
control units, for example, the correct operation of the
switches shown in Fig. 1.
2) Speed advantages are reported by authors using VHDL
[1], [22][27]; other event-driven simulation engines
[28][30]; System-C and MATLAB [31], [32]; or others
[33], [34].
System-level simulation, including sampling and clock
jitter, is a valuable verification of an RFIC [1]. Fig. 1 shows a
behavioral model of a multitap direct voltage-sampling mixer
(MTDVSM) filter. It consists of two independent networks
containing one free analog node each, illustrated as thick lines
and
. Unlike time-continuous mixers [35],
labeled
sampling mixers use a phase-locked loop (PLL) to sample the
input signal under particular phase conditions (e.g., at selected
maxima illustrated as signs in Fig. 2) delivering the envelope for an amplitude-modulated (AM) signal. Data-rate
decimation can be achieved by sampling every th maximum

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Fig. 2. Sampling an AM-modulated signal with mixer effect: o and symbolize samples taken with and without phase noise, respectively.

with
being an integer number. Quadrature AM (QAM) signals require sampling with more sophisticated phase conditions,
detailed, for example, by [36, eq. (10)]. Sampling with several
capacitors as illustrated in Fig. 1 allows the implementation of
a filter function and further decimation [36], [37]. High-quality
track and hold (T&H) circuits [38], [39] are required. Recently,
charge-sampling mixers have attracted much interest. They
are also called windowed integration samplers (WIS) [40]
and are based on a transconductorcapacitor (
-C) structure
[41][44]. The modeling works covered in this paper are
restricted to voltage sampling.
PLL phase noise is a major problem in RF direct sampling and
respective simulation. Recently, much work has been published
concerning design [45] and fabrication [46] of low-noise oscillators, and associated noise models have been presented (e.g.,
[1], [47]). The symbols in Fig. 2 indicate samples taken
at the peaks of the carrier signal and can be used to exactly reconstruct the envelope indicated by the dashed line. However,
in practice, the sampling process is triggered by a PLL which
is subject to phase noise. The o symbols in Fig. 2 represent
samples taken with phase noise. Top-level RFIC simulations
typically replace the RF input signal illustrated in Fig. 2 by its
into
envelope and translate the phase noise information
using appropriate models. The
sampled noise information
envelope mode is simulated without filtering because a lowpass
circuit designed for RFs would behave quasistatic and an RF
bandpass would block the relatively low envelope frequencies.
The top-level VHDL RFIC simulation presented in [1] mentions
neither a capacitor nor an inductor model. Investigations of jitter
impact on PLL-controlled T&H circuits and associated jitter requirements can be found (e.g., in [48] and [49]).
The goal of this paper is to deliver VHDL behavioral models
of analog parts in RFIC designs allowing the verification of the
digital parts using plain VHDL. Using proper noise models, an
insight into more sophisticated properties, such as BER, can be
obtained [1].
The organization of this paper is as follows. Section II
presents the event-driven analog-node model and its implementation in VHDL. Section III defines the modeling scope of
the MixED method. Section IV demonstrates device modeling
with this method. Section V addresses adaptive time stepping. Section VI presents experimental simulation results and
Section VII draws relevant conclusions.

and
Fig. 3. Resistive sources driving a common node n with
the node voltage and node conductance versus ground, respectively.

being

Although the inner schematics of the three illustrated sources

are slightly different, they are identical from a mathematical
point of view. The basic mathematical model for a MixED
source
(1)
is an equation with the two unknowns
and
. The given,
and represent source curindependent input quantities
rent, output conductance, and source voltage, respectively. If
of these MixED sources drive the same node , then they form
equations in the
unknowns
and , which
correspond to (1) from [18]

Kirchhoffs current law (KCL)

(2)
unis not only the last equation required to compute the
and perknowns, it also eliminates all unknown currents
mits the computation of the last remaining unknown . When
all sources attached to node drive their output conductances
, a VHDL resolution function computes the sum
to field
(3)

II. NODE MODEL DERIVATION AND IMPLEMENTATION

A. Model Derivation
MixED devices are modeled as controlled current-voltage
sources with finite output impedance. Fig. 3 illustrates an
assembly of MixED sources driving node with voltage
while sinking the output currents
.

of node with type

acc. to Fig. 4. A resoto field
lution function in the sense of the VHDL LRM [7] computes the
value of a signal having multiple drivers. With this information,
any MixED source can compute its partial voltage
(4)

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B. Model Implementation in VHDL

Fig. 4(a) shows the VHDL source code of package
declaring the resolved data type
, which models an
analog node on the event-driven time axis. Fig. 4(b) shows the
component with input signal and
associated
. Fields
,
driven analog node , both of type
of input signal represent the input parameters
,
and
and , respectively.
in Fig. 4(a) is declared this way, such
The constant
can be computed without numeric overflow
that
and is used to confine the parameter range. The constants
and
are defined as
and
,
, we obtain
respectively. For a real number range of
, and
for
and
, respectively, which is a sufficient parameter range. In case of a
, we obtain
real number range of
and
, which requires exceptions (e.g., to
represent capacitors of a few pF or times in the femto second
in the
range). The statement
component, together with the summing resolution function of
, realizes (3) so that
appears on field
after one
VHDL simulation delta (hereinafter called delta). The driver
, together with
, realizes (4) and (5), so
the summing resolution function of
after one more delta. The
that the node voltage appears on
maximum function in the denominator avoids divide-by-zero
conditions, which might occur (e.g., during initialization). The
computes the output
statement
should
current of the component according to (6). The field
be zero according to Kirchoffs current law (KCL) and allows
for output current correction. Since its computation consumes
CPU time, output current correction is limited to situations
where it is needed. They are identified by function returning
-type input flag
is
a Boolean value. If the
` ',
Z, then current correction is deactivated. If
0 s, which is required
current correction occurs at
for inductors with their infinite output conductance at steady
` ' will cause perpetual current correction.
state.
is the only signal that is driven from node to
Flag
the input signal and is useful for synchronization purposes.
in
allows the user to generate more
The constant
flags if desired. An important field for adaptive time stepping
. Its resolution function returns the largest value of data
is
driven to this field.
type
Fig. 4. VHDL source code. (a) Package pk mixed without package body,
declaring data type t mixed. (b) Code of the mixed driver component.
Fields s:u; s:g; s:i represent the input parameters U ; G ; I , respectively.
(a) Package pk mixed: (b) The mixed driver component.

Due to the law of linear superposition, a summing VHDL

resolution function can compute the node voltage as
(5)
at field

. Knowing

, the computation of

is simple
(6)

III. SCOPE OF THE PRESENTED METHOD

A. Scope of the MixED Simulation Technique
The mixed-signal event-driven (MixED) simulation technique presented here is applicable within any event-driven
simulation environment which allows the declaration of required data types and resolution functions as described in
Fig. 4. This paper presents a realization with standard VHDL.
In this section, we will make some restrictions to encompass
the scope of devices and circuits considered. Exceeding this
range is possible but the results may be inferior compared to
those obtained with AMS tools, presented, for example, in [11]
and [12].

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network can be composed of components which are either available or can be created with reasonable effort.
Fig. 5. (a) Free analog node n of data type t mixed. (b) Scalar input signal,
typically of type real. (c) Input data supplied with type t mixed, (d) Using a
single element of the analog node n, typically its voltage n:u. (e) Transferring
all data from node n to input signal s, both of data type t mixed.

C. Scope of Devices
The two main consequences of postulate (8) are timepointwise linearity and unidirectional devices. Timepoint-wise linearity demands, for example, that the output conductance of a
device model may depend on the node voltage of the last but
not the actual time point during the computation of an analog
solution point (ASP). The latter case would initiate an iterative
process between the devices output conductance and voltage.
Numeric feedback loops can also cause iterative processes.
For example, inductor L in Fig. 6(a) is a bidirectional de. Therefore,
vice. Consequently,
and
. This is contradictory to
axiom (8) and causes iterations. In Fig. 6(b), the problem is
solved by combining R and L to a complex device, so that only
one free node remains in the network.
D. Scope of Circuits

Fig. 6. (a) Contradictory to (8): network with two free, interdependent nodes.
(b) Good: network with a single free node n due to a complex model combining
R and L. (c) Good: concatenation of single-node networks.

Circuits with several interdependent free nodes are excluded

by (8). However, several independent nodes as shown in Fig. 1 or
the concatenation of unidirectional single-node networks complies with axiom (8). This concatenated network is illustrated
drives and
as an inverter chain in Fig. 6(c) where node
drives .

B. Analog Nodes
The VHDL-based analog node as the main issue of this paper
of Fig. 4. It coris modeled using the record data type
responds to an electrical terminal in VHDL-AMS. Fig. 5 illustrates the wiring symbols used in this paper. A thick line symbol. (a) shows the thick line
izes an analog signal of type
with a bold point indicating a multiple driven node . (b) shows
a scalar input signal, typically a voltage or current of type real.
. In (d), the el(c) shows an input signal with data type
is used as a driver for another signal. In (e), the data
ement
of node is passed to input signal . Both and are of type
.
A node within the network is defined to be free if it has a
finite node conductance to ground
(7)
, and
in Fig. 6. The source
Examples are nodes
and
in Fig. 6 are assumed to be ideal voltage
voltages
sources with zero output impedance.
The main restriction made in this paper is expressed by (8)
and called timepoint-wise linearity, that is, the properties of a
free analog node may not be a function of themselves during
the computation of an analog solution point
(8)
This avoids iterations which would slow down the simulation
and create the necessity to consider convergence criteria which
is beyond the scope of this paper.
The free analog node subdivides the particular mixed-signal
network into several more common, reusable MixED sources.
The free analog node is typically chosen so that the modeled

IV. DEVICE MODELING EXAMPLES

The examples that will be presented are intended to demonstrate how to prepare and plug in device models into (1), which
component according to
defines the input to the
Fig. 4(b) which computes the node voltage by means of the respective resolution functions. Several approaches of device and
circuit modeling aiming either at feasibility [13][18] or simulation speed [1], [22][27] within an event-driven environment
have been presented. In particular, the method of integrating
Laplace domain equations, for example, [18], [24], and [25] permits the implementation of higher order models. Several lowand high-order integration algorithms are described in [50], together with error estimations. For this paper, low-order models
are preferred because their numerical behavior is relatively easy
to understand, particularly in the case of stiff differential equations, which is helpful for some very large ratios of time step
to time constant used in this paper. Since all device models are
component of Fig. 4(b), the user
based on the
is free to combine models of different levels of complexity, for
example, two MixED sources modeling a conductor, where one
assumes piecewise constant and the other assumes piecewise
linear voltages, as will be presented.
A. Assumptions for Numerical Integration
Modeling transient devices, such as capacitors and inductors, requires the integration of differential equations. In the following equation, superscript specifies timepoint . Using the
at time point
notation as an approximation to
(9)

SCHUBERT: ANALOG-NODE MODEL FOR VHDL-BASED SIMULATION OF RF INTEGRATED CIRCUITS

Fig. 7. Resistive source with given R; V ; I and unknown

(a) Schematics. (b) Transformed to a resistive MixED source model.

V ;I

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Fig. 8. Resistive switch. (a) Schematics and (b) transformed to a MixEDsource model for sampling voltage from a capacitive load.

delivers
and
. Approximating voltages in
a piecewise linear manner allows them to be modeled as
for
(10)
with
. Consequently, sums and differences of voltages are also piecewise linear. Furthermore, we assume that
Voltages across capacitors are continuous
(11)
Currents through inductors are continuous
(12)
and
are approximations to
when is approached from the left- and right-hand side, respectively.
B. Resistive Source Model

Fig. 9. Capacitive source with given V ; C and unknown V ; I .

(a) Schematics (b) transformed to a resistive source model, (c) test circuit.

paper, we assumed abrupt, discontinuous changes. Their numerical treatment is beyond the scope of this paper and will be considered elsewhere in more detail.
D. Capacitive Source Model
Fig. 9 shows a capacitor model with source voltage
and
node voltage . The integration of its characteristic equation
can be done with the forward or backward
Euler integration method, which is generally defined as [50]

Fig. 7(a) shows a resistive source model with source voltage

and node voltage . Using
delivers
(13)
A comparison of (13) and (1), which is solved by the
component, delivers its input parameters as
(14)
(15)
(16)
Fig. 7(b) illustrates the transformed resistive source model
with its respective input parameters. The output quantities
and
are computed according to (3)(6).
C. Switched Resistive Source Model
The switched resistor model illustrated in Fig. 8 is intended
for sampling purposes, as shown, for example, in Figs. 1 and
17. It uses the constants
and
instead of
and
to allow for
. In this paper,
is used. Charge
. The switched resistor model is
sampling [40] requires
designed to operate within three modes which are distinguished
as follows.
by its input bit of data type
` ': On-mode
.
1)
` ': Off-mode
.
2)
switching to ` 'or to
` ': requires special
3)
treatment.
The situations of switching can be modeled as continuous
and . In this
or abrupt changes of the model parameters

Forward Euler

(17)

Backward Euler

(18)

As we require an implicit expression to match (1), backward Euler integration must be used. It has several advantages
over forward Euler integration, such as a second- instead of
first-order truncation error and better convergence for large
time steps in case of stiffness [50]. Approximating a piecewise
across the capacitor, we can write
linear voltage

(19)
This model corresponds to a piecewise constant current
through the capacitor
(20)
Using

, this equation is transformed to

(21)

A comparison of (21) with (1), required by the

component, delivers its input parameters as
(22)
(23)
(24)

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Fig. 10. Switched capacitor MixED-source model. (a) Schematics. (b) Model.
Fig. 11. Inductive source with given V ; L and unknown V ; I .
(a) Schematics. (b) Transformed to a MixED source model. (c) Test circuit.

Fig. 9(b) illustrates the equivalent resistive source model with

the required input parameters. The output quantities
and
are computed by algorithm (3)(6).
in Fig. 9(c)],
Testing stiff stability [i.e., time steps
this capacitor model was found to demonstrate stable behavior
. For Fig. 9(c), physically reasonable
for ratios
behavior is observed

matching (1), which is the input format for the

component in Fig. 4(b).
Inductor Model i1: The easiest approach of an inductor
model assumes a piecewise linear current obtaining
(28)

when

(25)

E. Switched Capacitor Model

The switched capacitor model illustrated in Fig. 10 is intended for sampling purposes (shown, for example, in Figs. 1
and 17). It is designed to operate within different modes which
of data type
as
are distinguished by the input bit
follows.
` ': normal transient mode, with output conductance
1)
.
` ': quasistatic mode with output conductance
2)
with
computed as shown in Fig. 4.
` ': disconnected mode: output conductance
,
3)
from the last falling edge of sc.
keep memorizing
switches to 0: compute an ASP, memorize
.
4)
switches to H or 1: compute an ASP.
5)
is
. With the tiny capacitance
For this paper,
, time constants of less than
seconds are obtained in the quasistatic mode so that (25) is fulfilled in good
approximation. Using the quasistatic mode, the switched capacitor is suitable to model a near ideal trackand-hold circuit. The
situations of switching were modeled as discontinuous changes
. The exact numerical
of the output conductance
treatment of these discontinuities is beyond the scope of this
paper and will be considered elsewhere in detail.

Comparing (28) with the general form of the MixED source

model, (1) delivers its input parameters for the
module as
(29)
(30)
(31)
Fig. 11(b) illustrates the transformed inductive source model
with the required input parameters. The output quantities
and
are computed by (3)(6).
In the test circuit of Fig. 11(c), this inductor model behaves
numerically stable for large time steps . It was observed that
when
The assumption of piecewise linear currents corresponds to
piecewise constant voltages. Consequently, the voltage error is
of first order. Visweswariah [28] simply precluded inductors
from his circuit simulation approach, but precluding inductors
eliminates an easy way to obtain oscillations.
Inductor Model i2: To comply with the assumption (10) of
piecewise linear voltages, we assume
(32)
to be the voltage across the inductor and compute

F. Inductive Source Model

Fig. 11(a) shows an inductor model with given
and
. The integration of its characteristic equation
unknown
can be achieved using the forward or backward Euler methods [50]
Forward Euler
Backward Euler

(26)
(27)

For the MixED method, the implicit formulation of (27) is required to deliver an equation with unknown current and voltage

(33)
Using

and

delivers
(34)

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2723

Fig. 12. Second-order lowpass circuit assembled from MixED sources.

Fig. 14. Multiple driven analog node n within a dynamic element matching
DAC. Averaging is performed with the capacitor drawn dashed in (a). (a) Resistive network. (b) Average levels 0, 1, 2, 3.
Fig. 13. VHDL source code (a) compuqting the last time step at node n and
(b) triggering ASPs using field n:t (e.g., within the testbench). (a) Computing
the width of the last time step (b) triggering analog solution points (ASPs).

The comparison of (34) to (1) delivers the input parameters

component as
for the
(35)
(36)
(37)
Inductor model i2, assuming piecewise linear voltages, produces a second-order voltage error. For small time steps, the
voltage accuracy is significantly improved compared to inductor
model i1. However, the test circuit shown in Fig. 11(c) proved
poor stiff stability for inductor model i2 as it oscillates when
.
G. Higher Order Models and Integration Methods
Problems, such as the RLC lowpass circuit shown in Fig. 12
or a buffer amplifier [51], can also be developed as a single
model. The MixED method presented before is open to incorporate higher order device models and integration algorithms. For
these purposes, one may write (1) with Laplace domain equations in the frequency domain, as demonstrated (e.g., in [18],
[24], and [25])
(38)
After replacing the Laplace variable by
, the resulting
differential equation can be integrated by using one of the implicit numerical methods (e.g., presented in [50]).
V. ADAPTIVE TIME STEPPING
A decision for an ASP at node is taken by increasing its field
to
, where
is a VHDL function returning the
actual simulation time. For transient devices, such as capacitors
and inductors, the width of the last time step , represented in
Fig. 13(a) as variable must be known. Its corresponding real
/sec in Fig. 13(a) by means of
value is computed from
, which computes the real-type value from
function
the time-type value .

In Fig. 13(b), ASPs are triggered by updating field

(e.g., within the testbench). Signals and
are flags of type
and
, respectively, which control the
switched resistor and switched capacitors shown in Figs. 1 and
causes an update of
and an actual17. Any event on or
,
ization of the input voltage
the actual simuwith being the actual frequency and
lation time. If additional time stepping is desired, it is defined
declared with the VHDL data type
.
with signal
can be modeled adaptively to the situation. Setting
Signal
to a large value, deactivates this kind of self-triggering
so that ASPs are computed only in response to events on ,
, or
in the example of Fig. 13(b).
VI. SIMULATION RESULTS
The author had access to several VHDL-AMS simulators
(evaluation versions and full versions [52], [53]), ModelSim AE
[19] and the faster ModelSim SE [21], to compare simulation
speeds. Accurate benchmarking was difficult since few AMS
tools could compile the data structures of the MixED model
shown in Fig. 4 and license terms prohibit the publication of
accurate and detailed speed comparisons. Simulation times
listed in the tables below were all measured with the graphical
output suppressed. This is because the graphical postprocessors
of the different tools consumed unequal CPU power and caused
different amounts of disc input/output (I/O).
A. DAC Using Dynamic Element Matching
Fig. 14(a) illustrates an example of a resistive network. The
are either at low or high poinput voltages
, so-called thermometric code is suftential. If
ficient to define the four output levels 000, 100, 110, and
, the thermometric code delivers a
111. If
nonlinear digital-to-analog converter (DAC). Dynamic element
matching (DEM) [54], [55] scrambles the high drivers. The state
100 is then translated, for example, to 100, 010, 001,
100, . An additional capacitor smoothes the result shown
in Fig. 14(b). DEM is particularly useful in combination with
oversampling devices, such as delta-sigma DACs [54], which
are frequently used in RF transceivers.
The situation illustrated in Fig. 14 using DEM without the
smoothing capacitor was simulated with the MixED VHDL
library and the testcode shown in Fig. 15. Architecture version
v1 computes a solution with VHDL real numbers, version v2

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TABLE I
RELATIVE SIMULATION RUNTIMES FOR 1-ms SIMULATION TIME OF THE
CIRCUIT IN FIG. 14 ON A 3-GHZ WINDOWS/INTEL WORKSTATION. IS THE
STANDARD DEVIATION OF THE GAUSSIAN-DISTRIBUTED CLOCK JITTER
CAUSING NONUNIFORM TIME STEPS

TABLE II
SIMULATED MINIMUM VOLTAGE AND ITS TIME POINT IN FIG. 16(a) MIXED
500 ps TIME STEP COMPARED TO SPICE WITH
1 ps
MODELS WITH

T =

T =

B. Second-Order RLC Lowpass

Fig. 16(a) shows a simulated step response of the RLC
lowpass in Fig. 12. Table II compares particular voltage/time
results for a MixED and an accurate SPICE [56] simulation.
Fig. 16(b) shows the frequency response. The MixED simulation of Fig. 16(b) with inductor model i1 was 7% faster than
faster than different
with inductor model i2 and
500 ps.
VHDL-AMS tools using the same time step,
2.065 at 14.9 MHz.
The maximum amplification is
MixED models using inductor model i2 acc. to (34) computed
1.98 (i.e., 4.1%). Inductor model i1 acc. to (28)
1.9 (i.e., 8%).
and the average AMS tool delivered
Using default time stepping, some AMS tools behaved poorly
with errors up to 35% of the peak, while a SPICE tool
2.04 (i.e., 1.2%).
delivered
C. Simulation of an MTDVSM Circuit
Fig. 15. VHDL testcode of Fig. 14. (a) Entity dacdem: DAC with dynamic
element matching. (b) Architecture v1: computation without resolution function. (c) Architecture v2: Computation with
. (d) Architecture
v3: Computation with
within
.

mixed driver

uses the

mixed driver
ms R

component and version v3 packs the

component into the component
according
0.
to (14)(16) with source current
Table I compares different simulation runtimes obtained
with the MixED software on ModelSim SE [21] and different
VHDL-AMS tools. MixED versions v1, v2, and v3 correspond
to the architectures Fig. 15(b)(d), respectively. AMS v1
does mean that an AMS tool uses architecture v1 as shown
in Fig. 15(b). AMS v4 uses VHDL-AMS terminals and
quantities. The speed of AMS tools slows down significantly
when random jitter with fs resolution is added to the time steps.
The simulated time span was 1 ms. Both hierarchical depth
(compare, for example, MixED v1, v2, v3) and clock jitter slow
down the MixED simulation. Jitter causes events on time steps
and consequently on the conductance terms
.

Fig. 17 illustrates the functionality of a multitap direct

voltage-sampling mixer using T&H voltage sampling with
K
47 fF,
m. The capacitors are
with nonoverlapping
charged one after the other at
0, all switches are open
onphases of the switches. At
` '. At
` ', all capacitors are connected
when
to one unified capacitor while the resistor remains disconnected
` ' , as illustrated in Fig. 17(b). The voltage of this
to signal
. The
unified capacitor is then sampled from
clock jitters standard deviation used to operate the switches in
the simulation of Fig. 18 is 2 ps with femto seconds resolution.
For the VHDL-based MixED models, the time-step trigger
updates to
) is detailed in
mechanism (i.e., field
Fig. 13(b).
Fig. 18 illustrates the sampling process with the three possible
simulation modes of this capacitive VHDL model.
ns. Tansient mode
Mode 1 is illustrated in Fig. 18 at
10 ps. The phase and amwith a maximum time step
versus input voltage
can
plitude shift of the node voltage
be observed as well as the interferences between the switching
.
capacitors and

SCHUBERT: ANALOG-NODE MODEL FOR VHDL-BASED SIMULATION OF RF INTEGRATED CIRCUITS

2725

Fig. 16. MixED simulation of the RLC lowpass circuit illustrated in Fig. 12
2K
; L = 10 H, C = 10 pF, time step T =
with inductor model i2, R
500 ps. (a) Response to a voltage step from 1 to 0 V with the RLC lowpass in
Fig. 12. (b) Amplitude characteristic V =V using V = 1 V 1 sin(2f 1 t)
with f being increased by 100 kHz every 10 s. Frequency information was
written under the screen shot by the author. Top down: analytically exact amplification, simulated amplification from the fast oscillating thick curve in the
middle, and the relative and absolute error of the amplification, where the peak
is 5% or 9.6 mV.

Fig. 18. A 2.1-GHz input frequency sampled with four capacitors operated by
signal isw , changing its value at a 1-GHz rate. Signals from top to down.: Input
signal V , capacitor-selection switch isw , resistive switch control signal sr
above clock , node voltage n:u, filter output voltage V (0), and capacitor voltages V (4 . . . 1) below their controlling switch signals scv (4. . . 1).

Fig. 17. Schematics of a multitap direct voltage-sampling mixer: (a) Charge

all capacitors C . . . C one after the other. (b) Short circuit all capacitors at
isw = 0 and clock = `0'. At this time, C samples the filter output voltage.

Fig. 19. Amplitude characteristic of an MTDVSM with ten switched capacitors. V = 1 V 1 sin(2f 1 t) with f being increased by 5 MHz every 2 s. Frequency information was written under the screen shot by the author. Top-down:
Exact analytical amplification, simulated amplification from V (delayed due
to the measurement), output voltage V with a sampling rate fs=11. fs =
1 GHz is the rate of the switch-control signal isw . The bottom curve shows an
error of 0.5% for simulated versus analytical amplification.

Mode 2 is illustrated in Fig. 18 at 5 10 ns: Quasistatic mode

10 ps. The capacitors are
with a maximum time step
. Due to these tiny capacitances,
multiplied with
follows the input voltage
exactly.
the node voltage
15 ns: Quasistatic
Mode 3 is illustrated in Fig. 18 at 10
is very large (e.g., 10 sec), so that analog
mode with
solution points are computed only in response to events on
and
controlling the switches. The results for the filter output
sampled at
clock
` ' are the same as
voltage
would be sampled within mode 2.
Fig. 19 illustrates the amplitude characteristic of the MTtaking
DVSM in Fig. 17 with ten switched capacitors

samples at a rate of
1 GHz.
with being increased by 5 MHz every 2 s. The top curve in
Fig. 19 shows the exact analytical amplification computed from
, with
10 being the number
of capacitors, is the filter input frequency, and
. The second curve shows the simulated ampli. It is delayed by
fication computed as
one measurement interval due to the measurement process. Both
top curves are initialized with 1.0 during the first measurement
interval, where the simulated amplification is undefined. The
bottom curve is the computed error between analytical and simulated characteristics. The peak error at 22 s is ca. 5 mV or

2726

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 56, NO. 12, DECEMBER 2009

0.5% using a clock jitter standard deviation of 2 ps with femtoseconds resolution. The filter illustrated in Fig. 1 can easily
be composed of two MTDVSM filters illustrated in Fig. 17.
The simulation time to obtain Fig. 19 with MixED models
using a maximum time step of 10 ps is a few tens of seconds
on a 3-GHz Windows/Intel computer for simulation mode 3 described before. It is 2.5 and 21 faster than for simulation
modes 1 and 2, respectively, and 763 faster than the best CPU
runtime obtained with VHDL-AMS tools and models on the
same computer.
VII. CONCLUSION
A mixed-signal event-driven simulation technique solving
small analog problems using plain VHDL with self-defined
resolution functions has been presented and the feasibility
to simulate linear single-node networks has been clearly
demonstrated. There are few speed advantages compared to
VHDL-AMS tools when a constant time step is enforced.
Advantages become visible when adaptive time stepping becomes necessary and the event-driven nature of VHDL can be
exploited (e.g., when random jitter is added to the time steps). A
behavioral model for a multitap direct voltage-sampling mixer
could obtain significant speed advantages compared to different
AMS tools, particularly when some simplifying assumptions
as tiny sampling capacitors are made. The results obtained with
VHDL are fast and suitable for the detection of errors in the
respective digital control logic.
ACKNOWLEDGMENT
The author would like to thank Prof. H.-J. Siweris for reading
the manuscript and providing valuable discussions and Prof.
G. Monkman for proofreading and correcting the English.
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Martin J. W. Schubert (M00) was born in Dortmund, Germany, in 1957. He received the Dipl.Ing.
degree in electrical engineering from the University of Dortmund, Dortmund, Germany, in 1985
and the Dr.Ing. degree in analytical silicon-on-insulator-metaloxide semiconductor field-effect
transistor modeling from the University of Hamburg-Harburg, Hamburg, Germany, in 1991.
He worked in the field of process and device simulation at the Institute for Microelectronics Stuttgart,
Stuttgart, Germany, from 1985 to 1991. From 1992
to 1994, he was with the Swiss Federal Institute of Technology and developed
high-voltage driver circuits within a standard-complementary metaloxide
semiconductor technology, presented at ISSCC in 1993. Since 1994, he has
taught electronics, circuit design, and electronic design automation at the
University of Applied Sciences of Regensburg, Regensburg, Germany. His
current research interest is mixed-signal and mixed-domain modeling.
Prof. Schubert is a member of the Verband der Elektrotechnik, Elektronik und
Informationstechnik e.V. (VDE).