Mirrored Power Distribution Network Noise Injection for

Soft Failure Root Cause Analysis

Suyu Yang (1), Benjamin Orr (1), David Pommerenke (1), Hideki Shumiya (2), Junji
Maeshima (2), Taketoshi Sekine (2), Yuzo Takita (2), Kenji Araki (2)
(1) Missouri S&T EMC Laboratory, 4000 Enterprise Drive, Rolla, MO 65401 USA
tel.: 573-341-4139, fax: 573-341-4477, e-mail: sydy7@mst.edu
(2) Sony EMCS Corporation, Tokyo Japan

Abstract In this paper a method for separating local soft-failures from distant errors related to noise on the
power distribution network (PDN) is demonstrated. Two approaches are used which duplicate the noise on a
PDN caused by some intentional injection onto a second system where the intentional injection is not present.

I. Introduction
During root-cause analysis of observed soft failures in
systems, it is necessary to understand the chain of
events. This chain usually consists of some ESD event
which somehow travels through the system and upsets
an unknown victim, resulting in a soft failure. In the
context of a system-level ESD issue, the chain of
interest is: entry point coupling path victim IC.
Such a chain is usually sufficient to solve the problem
by making low-cost changes to the system such as
redesigning the PCB or altering cable or connector
geometry.
In this paper, we focus on the victim IC and perform a
more in-depth root-cause analysis to determine where
inside the IC the upset occurs. The goal is therefore to
determine if the victim IC is subject to a local error or
to a distant error [1], possibly caused by a disturbance
on the system power distribution network (PDN).
Because it is often impossible to look inside an IC to
measure voltages and currents at different points
along the resistive IC-level PDN, the following
measurement technique cannot account for errors
caused by disturbances inside the IC package and
therefore focuses on board-level PDN events.
In order to detect whether or not the error condition is
caused by PCB-level PDN fluctuations, two methods
are presented for mirroring the voltage disturbance on
VDD that occurs during an observed soft failure. In
this paper a small microcontroller featuring an
ATMega32u4 is used as the DUT. Several simple
programs are written for this IC which can be used to
activate different functional blocks of the processor
such as the EEPROM, A/D converter, or GPIO pins.

The limitation of the method is that the IC internal

PDN noise is unknown, or differences within the IC
between different Vss or Vdd locations. For lower
frequency content there are good reasons to believe
that the internal and external voltages are similar, but
for higher frequencies this is not certain.

II. Soft Failure Detection

Methodology
In order to search for various soft failure
susceptibilities, the DUT IC was placed into one of
several infinite loops. The program structure is shown
in Figure 1 where the $OPP block performs one of the
following operations: ADC read, EEPROM read, and
an IO pin read.

Figure 1: Stress program structure

This method was chosen as a way to activate specific

functional blocks of the IC while the interference
method remains constant. During the test, a watch dog
timer within the IC is enabled, which is used to detect
system hang up resulting from a soft error. If the
system encounters such a soft error while executing
the $OOP block, a watch dog timer reset will occur

In

Ref

Out

Out

DUT A

In

Ref

DUT B

and an error code will be generated and recorded. The

stress pulse is provided by a transmission line pulsing
system [2] attached to various pins of the DUT. A
photograph of the TLP probe set up for an injection is
shown in Figure 2.

Figure 3: Schematic representation of the image injection method.

Figure 2: TLP Injection probe landed on the DUT

III. Mirrored (Passive)

Perturbation
The first method (mirrored, or passive perturbation)
couples the PDNs of two separate DUTs together,
forcing them to share similar high frequency
disturbances. In this way, an injection on DUT As
I/O pin which results in a soft-failure will mirror any
high frequency PDN disturbances onto DUT B,
placing it in a similar set of conditions. Because each
DUT is supplied by an independent power supply,
affects such as loss of power in DUT A resulting from
events such as latch-up are not mirrored into DUT B.
Conceptually this configuration can be viewed as the
DUTs attached to two separate power supplies
through low pass filter networks and shorted together
near the ICs. A conceptual block diagram is shown in
Figure 3.

This ensures that the low frequency load on each

supply is not significantly different from normal
operation, but that the DUTs both share similar noise
profiles. Before the image injection is performed,
some additional modification is needed for the actual
test. Since the goal is to check if the soft error is
related to PDN disturbance or not, it needs to be
ensured that the other parts of the IC are not disturbed
by the ESD injection. It is first necessary to modify
the ICs reset pin, because if the reset pin somehow
gets disturbed, then the IC will reset automatically,
making it impossible to further identify a soft error
root cause.
The second requirement is to modify the systems
PDN network. This is necessary to isolate the DUTs
PDN with the rest of the PDN, so when performing
the injection, the other parts PDN will not be
disturbed. This isolation is implemented by adding a
ferrite bead across the PDN trace and adding a
capacitor between the PDN trace and ground.
The third requirement and modification is to remove
the decoupling capacitors of the DUTs power pins to
make the soft error easier to trigger.
After the two boards are both modified in the same
way, then the AVCC pins on each board are
connected together, the VCC pins on each board are
connected together, and the grounds, all with
interconnecting wires. In order to reduce the
inductance of these interconnecting wires, the two
boards are placed back-to-back and also the length of
the additional wires are made to be as short as
possible. A photograph of the implementation is
shown in Figure 4.

Vdut 15 V, Idut 3.5A

Watchdog
Reset

A soft error is observed @

Vdut 13 V, Idut 3A

Duplicate
Error

Using this method, the EEPROM read/write and

watchdog reset errors were able to be triggered by the
independent PDN disturbance, indicating that the root
cause of such errors is actually the supply stability and
not the current injected into the IO pin itself. The
ADC and GPIO read errors were not duplicated by
this technique.
Figure 4: Photograph of the joined DUTs

The second method, playback (replaying) via an

arbitrary waveform injection, can be implemented on
only a single DUT by recording the voltage
disturbance (such as on the VDD pin) on the DUTs
PDN during an error condition and then replaying
that disturbance through a high-power amplifier to
recreate the VDD waveform. This replay method
results in a greater disparity between the two DUTs,
but the interference is still very similar. Figure 6
shows a block diagram of the injection system used to
disturb the VDD network. The voltage waveform is
first recorded from the DUT during the IO injection
and then replayed through an amplifier into the same
DUT to duplicate the VDD disturbance at a later time.

|Hf|

Using this configuration, the voltages at both DUTs

were measured independently during injection to
observe the effectiveness of the high frequency
coupling. An example generated VCC disturbance
waveform is shown in Figure 5. The close correlation
of the waveforms in Figure 5 show that the PCB-level
PDN disturbance is nearly exactly duplicated onto
DUT B by injection on DUT A, verifying good
connectivity between the DUTs.

III. Playback via Arbitrary

Waveform Injection

Figure 5: The mirrored voltage disturbance at pin 34 (VCC) on the

two DUTs during GPIO injection on DUT A.

AWG
Playback
Figure 6: AWG Injection flowchart

The DUT pair was then stressed during each program.

The results are recorded in Table 1.
Table 1: Mirrored Perturbation Failure Results

Test

DUT A (I/O)

DUT B
(PDN)

ADC Read

A soft error is observed @

Vdut 15 V, Idut 3.5A

No error

EEPROM
Read/Write

A soft error is observed @

Vdut 13 V, Idut 3A

Duplicate
Error

GPIO Read

A soft error is observed @

No error

The basic idea is to obtain the PDN disturbance when

soft errors occur, and then recreate the PDN
disturbance using a dual-channel injection system.
Since there are two different power domains for this
particular DUT, two injection channels were required
to re-create the disturbance on the DUTs PDN. The
arbitrary waveform generators output power is
limited, necessitating the use of an RF amplifier to recreate the same disturbance on the DUTs PDN. The
playback measurement setup is shown in Figure 7.

Figure 7: Dual injection measurement setup

The whole circuit diagram is shown in Figure 8.

Figure 8: Dual injection block diagram for playback via arbitrary waveform injection.

After the proper hardware configurations were

determined, the software configuration was analyzed
for proper recreation / playback of the original PDN
disturbance. The basic idea is to download a
waveform into an arbitrary waveform generator
(AWG) such that the waveform at the pin matches the
waveform that was measured. In addition, the AWG
output power is limited and sometimes it cannot
recreate the PDN disturbance due to the limited output
power thus an RF amplifier will be needed. In this
injection method some frequency distortions are
possible since the RF amplifiers frequency response
is not always flat, so the input and output waveform
shapes may not match.
Compensation is based on AR100W1000 amplifiers
character and the VCC pin disturbance is
compensated. The idea of compensation is to adjust
the AWG pulse in small steps beginning from the

initial t=0 of the pulse (in one ns increments) to match

the waveform.
Figure 9 shows the resultant played back
disturbance of the injection system after compensation
/ matching. Using this method, the disturbance on
VDD is nearly exactly recreated without the need for
a duplicate DUT or carefully crafted VDD network.
The primary down-side of this method is the increased
time required to perform two sets of tests as well as
the additional equipment required by the method. The
results of the tests are shown in Table 2. Running the
same test cases using the second PDN disturbance
method results in the same failure signature as
revealed by the first method.

can be corrupted because the supply voltage is too low

for the CPU and the EEPROM to operate properly.
These issues are the same as for board level systems
using EEPROM, and the same design solutions should
be applied.

Conclusion

Figure 9: The generated voltage disturbance at pin 34 (VCC) on

the two DUTs during GPIO injection on DUT A.
Table 2: Active PDN Disturbance

Test

Injection B
(PDN)

ADC Read

No error

EEPROM
Read/Write

Duplicate
Error

GPIO Read

No error

Watchdog
Reset

Duplicate
Error

Both the EEPROM and the device watchdog were

disturbed by the intentional PDN disturbances;
however the ADC and GPIO read operations were
not.
In addition, the ATMEGA32U4 datasheet indicates
that a PDN disturbance may cause an EEPROM R/W
error. During periods of low VCC, the EEPROM data

In this paper, two methods are presented to duplicate

the disturbances generating soft errors on the PDN of
a system. Both methods can recreate the voltage
disturbance on the PCB-level PDN with reasonable
accuracy and are used to trigger soft failures which
are also observed when an IO pin is the source of the
disturbance. These tests indicate that the observed
errors may be caused by the secondary effect of a
voltage disturbance on the PCB PDN as a result of
current injected onto the bus by the ESD protection
rather than by the injection into the IO pin itself.

Acknowledgements
This paper is based upon work supported partially by
the National Science Foundation under Grant No. IIP1440110.

References
[1] C. Duvvury, H. Gossner, System Level ESD CoDesign, Wiley 2015
[2] T. Maloney and N. Khurana, Transmission Line
Pulsing for Circuit Modeling of ESD
Phenomena, in Proc. on EOS/ESD Symp., pp.
4954, 1985.