CSE 31L Lecture 4 Notes

I.

Combinational versus sequential logic

a. Combinational output of the circuit depends on the current inputs
b. Sequential output of the circuits depends on previous inputs. Therefore, storage elements are
required (through a feedback loop)
i. D Latch
1. If clock is high, Q = D
2. If clock is low, Q remains in the same state
ii. D Flip Flop
iii. always procedure (always, always_comb, always_latch, always_ff)
iv. initial, always, final
c. Sensitivity list
i. Specified after always or always_ff
ii. The always_ff keyword must be followed by an edge-sensitive event control (@)
iii. A list of signals a process is sensitive to
iv. Model 1
d. Blocking versus non-blocking assignment
i. Blocking is combinational and uses =
ii. Non-blocking is sequential and uses <=
iii. Model 2
e. Storage elements
i. Latch
1. Positive level D latch with asynchronous reset
a. Q mimics D when CLK is 1
b. Model 3
2. Negative level D latch with asynchronous reset
a. Q mimics D when CLK is 0
b. Model 4
ii. Flip-Flop
1. Positive edge D flip-flop with synchronous reset (Model 5)
2. Negative edge D flip-flop with synchronous reset (Model 6)
3. Positive edge D flip-flop with asynchronous reset (Model 7)
4. Negative edge D flip-flop with asynchronous reset (Model 8)
f. Sequential Coding
i. if, case, for
ii. if statements should be executed depending on conditional expressions always_comb
allows the following conditional code to execute in order.
1. Model 9
iii. 1-digit Decimal Counter (Model 10)
iv. Shift Register (Model 11)
v. case statements
1. The programmer provides a set of cases. Depending on the condition, a statement
can be executed. Additionally, a default case can be set if no other case satisfies
the given conditional.
2. Model 12
3. case is the general case statement
4. casez treats high-impedance (z) values as dont cares
5. casex treats high-impedance (z) and unknown (x) values as dont cares
6. use always_comb
7. There is a unique case and priority case
vi. Ripple carry adder example
vii. Barrel Shifter example

CSE 31L Lecture 5 Notes

I.

function, alias, sequential circuit example, memory models

a.
b.
c.
d.
e.
f.

g.
h.

A generic decoder has n inputs and 2^n outputs

i. Truth table Model 13
ii. SystemVerilog Code Model 14 (Active High), Model 15 (Active Low)
1-bit loadable shift register
i. Model 16
4-bit shift register
i. Model 17
n-bit shift register
i. Model 18
function
i. Provides a way to split code into smaller parts that are used in a model
ii. Functions can be declared inside a model
alias
i. Declares multiple names for the same physical net, or bits within a net.
ii. Does not define a new object.
iii. It is just a specific name assigned to some existing object
iv. Model 19
Shift register exercise Model 20
Memory
i. ROM (Read-Only Memory)
ii. RAM (Random Access Memory) (Model 21)
iii. Memory can also be divided into the following two categories
1. Asynchronous/Synchronous
2. Single port/Dual port

CSE 31L Lecture 6 Notes

I.

Finite State Machines (FSM)

a. As we all know, digital circuits can be classified as either combinational or sequential
b. So then, what is a finite state machine (FSM)?

c.

d.
e.

i. FSMs are just a modeling technique for sequential circuits!

The FSM approach is recommended when
i. The construction of a list with all system states is viable
ii. All output values that must be produced by the system are easily enumerable. This means
that the list must be the same in all states
iii. All conditions for the machine to move from one state to another must be easily
enumerable
Practical uses of FSMs involve
i. Traffic-light controller, elevator controller, control unit for microcontroller datapath
FSM Representations
i. State Transition diagram

ii.
iii. Hardware perspective

f.

g.

iv.
There is a five-step design procedure
i. Step 1: Draw the state transition diagram
ii. Step 2: Write truth tables for nx_state and output. Rearrange truth tables, replacing state
names with corresponding binary values
iii. Step 3: Get the boolean expression for nx_state and output
iv. Step 4: Draw the circuit, placing all D flip-flops in the lower section and the combination
logic in the upper section
v. Step 5 (optional): Add D flip-flops at the output to eliminate glitches

Lets design a synchronous 3-to-9 counter

i. Step 1: We should draw the state transition diagram.

ii.
iii. Notice that each block points to the next highest binary number. Nine points to three,
however.
iv. Step 2: We should set up a truth table! A number not on here (such as 1100) can be
represented by a dont care (x)
previous_state
next_state
(q3, q2, q1, q0) (ex. 0011)
(d3, d2, d1, d0) (ex. 0100)
0011
0100
0100
0101
0101
0110
0110
0111
0111
1000
1000
1001
1001
0011
v. Step 3: Requires us to find the boolean expressions. We can do this with a karnaugh map.
However, I omitted the maps to skip to the main point.
1. d3 = (q3)(q0) + (q2)(q1)(q0)
2. d2 = (q2)(q1) + (q2)(q0) + (q2)(q1)
3. d1 = (q1)(q0) + (q1)(q0)
4. d0 = (q3) + (q0)
vi. Step 4: Transfer our Boolean equations into a clear circuit diagram.

h.

1.
Study the FSM template! It is quite useful (Model 22)

i.

i.

j.

k.
l.

We explore some examples of FSMs. The first one will be a BCD counter (Model 23)
i. I usually imagine this as implementing a clock
ii. rst 0000 0001 0010 0011 0100 0101 1001 0000

iii.
Finite State Machine with two state (stateA and stateB) example Model 24
i. Everytime d = 1 is received, the current state changes into the other
ii. The desired output is x = a when machine is in stateA
iii. The desired output is x = b when machine is in stateB
iv. The initial (rst) state is stateA

v.
A third FSM example
i. It is the same as the previous example, except we want the output to be synchronous (to
change only when the clock rises)
A fourth FSM example String Detector Model 25
i. Design a circuit that takes as input a serial bit stream
ii. Outputs 1 when the sequence 111 occurs
iii. Overlaps must be considered. If 0111110 occurs, the output remains active for three clock
cycles.

iv.

II.

Encoding Styles
a. Sequential (*)
b. Gray
c. Johnson
d. One-hot
e. User-defined
f. How many states can be encoded with n=4 flip-flops using:
i. Sequential:
16 = 2**n
ii. Gray:
16 = 2**n
iii. Johnson:
8 = 2*n
iv. One-hot:
4=n
g. When to use which?