Statistical Static Timing Analysis:

How simple can we get?

Chirayu Amin, Noel Menezes*,
Kip Killpack*, Florentin Dartu*,
Umakanta Choudhury*, Nagib Hakim*,
Yehea Ismail
ECE

Department
Northwestern University
Evanston, IL 60208, USA

* Intel

Corporation,
Hillsboro, OR 97124, USA

Outline

Introduction
Process Variation Model

Methodology

Distributions
Cell-library characterization
Path-based
Add/Max Operations

Results
Conclusions
2

Variations and their impact

Sources of Timing Variations

Probability(rank 50)

0.8
0.6

Critical path # 190

will be in top 50 paths
on 10% of the dies!

0.4

Influence

Channel Length
Dopant Atom Count
Oxide Thickness
Dielectric Thickness
Vcc
Temperature

Performance yield prediction

Optimization
Design convergence

Management (traditional)

Corner based analysis

Sub-optimum

0.2
0
0

100
200
300
Path Rank
(from deterministic timing analysis)
90 nm microprocessor block

Recent solutions

Categories

Block-based pdf propagation

Non-incremental
Incremental

Path-based pdf propagation

Bound calculation
Generic path analysis

Complexity

Non-gaussian pdf propagation

Statistical MAX operation
Correlations
Reconvergence
4

Factors influencing solutions

Predicting performance yield or optimizing

circuit?
Underlying process characteristics

How significant are the variation sources?

How significant is each component?

Die-to-die / Within-die
Channel length, Threshold voltage, etc

Architecuture and Layout

Number of stages between flip-flops

Spatial arrangement of gates
5

SSTA targets

Performance yield optimization

Die-to-die effects are more important

Can be handled using a different
methodology

Design convergence

Affected primarily by within-die effects

Gates delay w.r.t. others on the same die

Presented
Presented work
work addresses
addresses design
design convergence
convergence
6

Outline

Introduction
Process Variation Model

Methodology

Distributions
Cell-library characterization
Path-based
Add/Max Operations

Results
Conclusions
7

Modeling variations

Only within-die effects considered

Variations
Channel Length (le)

Threshold Voltage (vt)

Correlated or Systematic (les)

Uncorrelated or Random (ler)
le=lenom+les+ler

Uncorrelated or Random (vtr)

vt=vtnom+vtr

Main
Main variations
variations affecting
affecting delay:
delay: le
le and
and vt
vt
8

Parameter distributions

Gaussian distributions for les, ler, vtr

Characterized by les, ler, vtr

Systematic variation for les

Correlation is a function of distance

* 1

(d)

i
0

*[16] S. Samaan, ICCAD 04

mm

Die
ij = (dij)
9

Cell-library characterization

Simulations similar as for deterministic STA

Plus extra simulations for measuring delay

Gate

CL

tt
delay = delaynom(lenom,tt,CL)

+ delayles(les,tt,CL) + delayler(ler,tt,CL) + delayvtr(vtr,tt,CL)

effects of variations on delay

2delay = 2delay,les( 2les,tt,CL) +

2
delay,ler ( ler,tt,CL)

+ 2delay,vtr (2vtr,tt,CL)

Overall
lerr,, and
and vtvtrr
Overall delay
delay variance
variance is
is the
the sum
sum of
of variances
variances due
due to
to le
less,, le
10

Measuring delay

Characterization of delay,les

Vary le similarly for all transistors in the cell (=1)

Measure delay change for each input to output arc

Characterization of delay,ler and delay,vtr

Sample using Monte Carlo method

Each transistor sampled independently

Measure delay change for each input to output arc

11

Outline

Introduction
Process Variation Model

Methodology

Distributions
Cell-library characterization
Path-based
Add/Max Operations

Results
Conclusions
12

Variation effects on a path

Systematic variations

Additive effect

Spatial effect

(/)path-delay= (/)cell-delay
Paths close together have very similar delay variation

Random variations

Cancellation effect

Variations die out as long as there are enough stages

(/)path-delay= (1/sqrt(n))*(/)cell-delay
ITRS projections: n~12 stages
13

Paths converging on a flip-flop

Distribution of delay for each path known

From simple path-based analysis

Distribution of overall margin at flip-flop?

Statistical MAX operation!

14

Statistical MAX operation

1

Non-overlapping

Highly correlated, overlapping,

different sigmas

P1

P2
P1

P2

MAX is trivial,
and situations observed on circuits

Highly correlated, overlapping,

comparable sigmas
P1

x1

1 x2 2 y2

MAX is non-trivial, but

situations not observed on circuits

Random, overlapping

P2
P1
P2

x1 y1

x2 y2

y1

x1 1 y2 y1 2

x2

Comments about MAX

Path-delays are highly

correlated
Sigmas are similar
Random components
die out due to depth

No
No need
need for
for aa complicated
complicated MAX
MAX operation!!
operation!!
16

Path-based SSTA methodology

Main Idea

Calculate the timing-margin distribution, for each path ending

at a flip-flop or a primary output (PO)
Clock-data path CGD
Typical pathbased
analysis

Generating
Flop

Logic
Cell

Logic
Cell

Sampling
Flop

Clock buffers
clock
grid

Clock sample path CS

17

Calculating margin distribution

margin = tcs + T - t*CGD
2margin= 2CS + 2CGD - 2 cov(tCS,tCGD)
path CGD

clock grid

*includes

tsetup

CS delay sigma for path CS

CGD delay sigma for path CGD
cov(tCS,tCGD) covariance
between delays of CS and CGD

path CS

Above analysis requires calculating delay variances and

covariances for paths Statistical ADD operation

18

Statistical ADD

Path delay variance is the sum of delay

variances due to les, ler, and vtr

2path-delay = 2path-delay,les +
Uncorrelated or Random
Components

2
path-delay,ler

+ 2path-delay,vtr

Correlated or Systematic
Component

2
2
path
=

i,ler
delay ,ler
i =1
n

2
2
path
=

i ,vtr
delay ,vtr
i =1

2
path delay ,les

=
i =1

2
i ,les

ij j ,les
j =1

19

Path-delay covariance

Easy to calculate based on pair-wise

covariances between individual gates
Gate i

ij

Path 1
Path 2

Gate j

p1 , p 2 = cov(celli , cell j ) = ij les ,i les , j

i p1 j p 2

i p1 j p 2

20

Outline

Introduction
Process Variation Model

Methodology

Distributions
Cell-library characterization
Path-based
Add/Max Operations

Results
Conclusions
21

Results

Methodology applied to a large microprocessor block

More than 100K cells

90 nm technology
Fully extracted parasitics

Block-based (BFS) analysis to identify top N critical

end-nodes (flop inputs, POs)
Critical paths identified by back-tracking
Path-based SSTA performed on the critical paths
Comparison with Monte Carlo Analysis

22

Monte Carlo

600 dies (profiles) for

varying les, ler, and vtr

Number depends on
correlation distance,
block size, etc

les

Full block-based
analysis (BFS)

Not just on critical paths

Deterministic STA on
each of the generated
600 dies

ler and vtr

*[16] S. Samaan, ICCAD 04

23

Comparison with Monte Carlo

Path-based Margin Sigma

0.7
0.6

(data for top 492 end-nodes)

0.5
0.4
0.3
0.2
0.1
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Monte Carlo Margin Sigma

Good
Good correlation
correlation with
with Monte
Monte Carlo
Carlo Results!
Results!

24

Analysis

Error in predicting sigma

Maximum: 0.066 FO4 delay

Average: 0.19% of the path delay

Monte Carlo showed that distributions of

margins are Gaussian

No need for more complex distributions

At each end-node

Only one or two paths were clearly showing up as worst

paths on 80% of Monte Carlo samples
Relative ordering of paths ending up at a node does not
change

25

Outline

Introduction
Process Variation Model

Methodology

Distributions
Cell-library characterization
Path-based
Add/Max Operations

Results
Conclusions
26

Conclusions

Statistical timing is important

Simple path-based algorithm is
adequate

Justified based on design, variation profiles

Distributions are Gaussian

Errors in estimating sigma are
acceptable
27

Q&A