OPTIMIZED EXACT AND APPROXIMATE

ALGORITHM BASED FILTER DESIGN

A PROJECT REPORT
Submitted by

JANAKIRAMAN.S (411712106033)
MADHUSUDANAN.A (411712106045)
in partial fulfillment for the award of the degree
of

BACHELOR OF ENGINEERING
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

PRINCE SHRI VENKATESHWARA PADMAVATHY ENGINEERING

COLLEGE, CHENNAI-127

ANNA UNIVERSITY: CHENNAI 600 025

APRIL 2016

ANNA UNIVERSITY: CHENNAI 600 025

BONAFIDE CERTIFICATE
Certified that this project report OPTIMIZED EXACT AND APPROXIMATE
ALGORITHM BASED FILTER DESIGN is the bonafide work of
JANAKIRAMAN.S(4117121060033),MADHUSUDANAN.A(411712106045),
who carried out the project work under my supervision.

SIGNATURE

SIGNATURE

Mr. K. K. SENTHIL KUMAR, M.E.,( Ph.D).,

Mrs. S.R.KAUSALYAA, M.E.,

HEAD OF THE DEPARTMENT

SUPERVISOR
Assistant Professor
Department of Electronics and
Communication Engineering
Prince Shri Venkateshwara
Padmavathy Engineering College,
Chennai-127

Department of Electronics and

Communication Engineering
Prince Shri Venkateshwara
Padmavathy Engineering College,
Chennai-127

Submitted for viva-voice held on

INTERNAL EXAMINER

EXTERNAL EXAMINER

ACKNOWLEDGEMENT
First and foremost we bow our head to the Almighty for being our light and
for his gracious showers of blessing throughout the course of this project.
We would like to express our sincere thanks to our founder and Chairman,
Dr.K.Vasudevan, M.A., B.Ed., PhD for his endeavor in educating us in his
premier institution.
We are grateful to our Vice Chairman, Dr.V.Vishnu Karthik, M.D., for his
keen interest in our studies and the facilities offered in the premier institution.
We would like to express our sincere gratitude to our Administrative Officer
Mr.K.Parthasarathy, BE., for his assistance in all our endeavors.
We thank our Principal, Dr. T. Sounderrajan, M.Tech., PhD, for his
valuable support and encouragement in all our efforts throughout this course.
We would like to express our sincere thanks to our beloved Head of the
Department, Mr.K.K.Senthil Kumar, M.E., (PhD), for his support and providing
us with ample time to complete our project.
We wish to express our great deal of gratitude to our project
Guide,Mrs.S.R.Kausalyaa,M.E., for her cooperation towards us at all times of
need,for her guidance and valuable suggestions in every aspects for completion of
this project.
We are also thankful to all faculty members and non teaching staffs of all
Departments for their support.Finally we are grateful to our family and friends for
their help, encouragement and moral support given to us during our project work.

ABSTRACT
In many digital signal processing systems, the Constant Array Vector
Multiplication(CAVM) operation has significant impact on the complexity and
performance of the design because a large number multiplications are required and
is also a performance bottleneck in many other DSP systems. The realization of a
multiplier in hardware is expensive in terms of area, delay, and power dissipation.
For this purpose many efficient algorithms and architectures such as shift-add and
Approximate Algorithm have been introduced for the design of low complexity
CAVM operations. But the Delay constraint in the Filter increases. Therefore to
overcome this disadvantage and for low complexity CAVM operations we
introduce an digit parallel fir filter whose provides delay pipeline mechanism. Thus
the proposed method reduces the delay. Hence the proposed method simulation
results are shown as less delay compared to existing Approximation method.

TABLE OF CONTENTS
4

CHAPTE

TITLE

R NO.

PAGE

ABSTRACT
LIST OF TABLES
LIST OF FIGURES
LIST OF ABBREVIATIONS

NO.
iv
vii
viii
ix

INTRODUCTION
1.1 Overview
1.2 Optimization techniques

1
1
5

LITERATURE REVIEW

FIR FILTER DESIGN

3.1
FIR Filter
3.1.1
3.2
3.3

9
9

Design of FIR Filter

Description of approximate algorithm

Description of exact algorithm

11
14
16

MATLAB
4.1 Filter Design And Analysis Tool(FDA)

21
22

VLSI
5.1 Introduction
5.2 VLSI Design Flow
5.3 Introduction To FPGA
5.4 XILINX
5.5 Introduction To VHDL
5.6 Feautures Of VHDL
5.7 Advantages Of VHDL

24
24
25
26
27
28
29
29

HARDWARE IMPLEMENTATION

30

7
8

6.1 Spartan 3

30

6.1.1
Features
6.1.2
Spartan 3E Architecture
6.2 Description Of VSK Spartan 3E Starter Kit
RESULTS AND DISCUSSIONS
7.1 Simulated Results
CONCLUSION
REFERENCES

30
31
32
34
34
44

LIST OF TABLES
TABLE

TABLE

PAGE

NO.
3.1
3.2

Frequency Response Of Linear Phase FIR Filter

Frequency Response Of FIR filter based on Exact

NO.
14
20

7.1

Algorithm
Comparison

of

Algorithm Based Design

Techniques

43

LIST OF FIGURES
FIGURE

FIGURE

PAGE

NO.
1.1
1.2
1.3
3.1
3.2
3.3
3.4

IIR Filter
FIR Filter
Method Of Optimization
Direct Form Of N-tap FIR filter
MCM method
CAVM method
4-tap FIR Filter Structure Using Approximate

NO.
3
4
5
10
10
10
15

3.5
3.6
4.1
5.1

Algorithm
Flow Of Exact Algorithm
4-tap FIR Filter Structure Using Exact Algorithm
Flow Chart Of FDA Tool
VLSI Design Flow

18
19
23
26

6.1

Hardware Architecture Of Spartan 3E

32

7.1

RTL Structure Of FIR Filter Design Using

34

7.2
7.3
7.4
7.5
7.6
7.7
FIGURE

Approximate Algorithm
Output Based On Approximate Algorithm
Magnitude Response Based On Exact Algorithm
Phase Response Based On Exact Algorithm
Magnitude Response After Quantization
Quantized Filter Coefficients
HDL Generation
FIGURE

35
35
36
37
38
39
PAGE

NO.
7.8

RTL Structure Of FIR Filter Design Using Exact

NO.
40

7.9
7.10
7.11

Algorithm
Output Based On Exact Algorithm
Delay based On Approximate Algorithm
Delay based On Exact Algorithm

41
42
43

LIST OF ABBREVIATIONS
ABBREVIATION
AMRA
ASIC
BPF
BRF
CSD
CLB
CLD
CAVM
DCM
DDR
FDA
FDO
FIR
FPGA
HDL
HPF
IIR
IOB
ISE
JTAG

EXPANSION
Auto Regressive Moving Average
Application Specific Integrated Circuit
Band Pass Filter
Band Reject Filter
Canonical Signed Digit
Configurable Logic Blocks
Complex Logic Devices
Common Array Vector Multiplication
Digital Clock Manager
Double Data Rate
Filter Design and Analysis Tool
Filter Design Optimization
Finite Impulse Response
Field Programmable Gate Array
Hardware Description Language
High Pass Filter
Infinite Impulse Response
Input Output Block
Integrated Simulated Environment
Joint Test Action Group

ABBREVIATION

EXPANSION
9

LCD
LED
LPF
LUT
MATLAB
MCM
PCB
PLD
PLL
PROM
RAM
RTL
SMPS
SRAM
UCF
VHDL

Liquid Crystal Display

Light Emitting Diode
Low Pass Filter
Look Up Table
Matrix LABoratory
Multiple Constant Multiplication
Printed Circuit Board
Programmable Logic Device
Phase Lock Loop
Programmable Read Only Memory
Random Access Memory
Register Transfer Level
Switched Mode Power Supply
Static Random Access Memory
User Constraint File
Very High Speed Integrated Circuit Hardware Description

VLSI

Language
Very Large Scale Integration

10