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CHAPTER
Array Subsystems
VLSI Design
Chih-Cheng Hsieh
Outline
1.
2.
3.
4.
5.
6.
VLSI Design
8- 2
SRAM
DRAM
Read-Only Memory (ROM)
Serial Access Memory
Content-Addressable Memory
Programmable Logic Array
Chih-Cheng Hsieh
Memory Arrays
8- 3
Memory Arrays
Read/Write Memory
(RAM)
(Volatile)
Static RAM
(SRAM)
Dynamic RAM
(DRAM)
Mask ROM
Programmable
ROM
(PROM)
VLSI Design
Shift Registers
Serial In
Parallel Out
(SIPO)
Erasable
Programmable
ROM
(EPROM)
Queues
Parallel In
Serial Out
(PISO)
Electrically
Erasable
Programmable
ROM
(EEPROM)
First In
First Out
(FIFO)
Last In
First Out
(LIFO)
Flash ROM
Chih-Cheng Hsieh
Array Architecture
8- 4
bitline conditioning
bitlines
row decoder
memory cells:
2n-k rows x
2m+k columns
n-k
column
circuitry
k
n
column
decoder
2m bits
Chih-Cheng Hsieh
SRAM Architecture
8- 5
SRAM Cell
Decoders
Column Circuitry
Multiple Ports
VLSI Design
Chih-Cheng Hsieh
8- 6
VLSI Design
Chih-Cheng Hsieh
6T SRAM Cell
8- 7
6T SRAM Cell
Read:
bit
bit_b
word
Write:
VLSI Design
Chih-Cheng Hsieh
SRAM Read
Precharge both bitlines high
word
Then turn on wordline
One of the two bitlines will
be pulled down by the cell
Ex: A = 0, A_b = 1
bit discharges, bit_b stays high
But A bumps up slightly
Read stability
A must not flip
N1 >> N2
(N1 is stronger than N2)
VLSI Design
8- 8
bit_b
bit
P1 P2
N2
A
N4
A_b
N1 N3
A_b
bit_b
1.5
1.0
bit
word
0.5
A
0.0
0
100
200
300
400
500
600
time (ps)
Chih-Cheng Hsieh
SRAM Write
8- 9
Writability
Must overpower feedback
inverter
N4 >> P2
bit_b
P1 P2
N4
A_b
N1 N3
A_b
A
1.5
bit_b
1.0
0.5
word
0.0
0
100
200
300
400
500
600
700
time (ps)
VLSI Design
Chih-Cheng Hsieh
8- 10
Write
Bitline Conditioning
Bitline Conditioning
More
Cells
More
Cells
word_q1
word_q1
bit_v1f
word_q1
out_b_v1r
VLSI Design
bit_v1f
bit_b_v1f
bit_v1f
SRAM Cell
SRAM Cell
bit_b_v1f
out_v1r
write_q1
H
out_v1r
data_s1
Chih-Cheng Hsieh
SRAM Sizing
8- 11
bit
word
weak
med
med
A
A_b
strong
VLSI Design
Chih-Cheng Hsieh
SRAM Layout
8- 12
GND
VDD
WORD
Cell boundary
VLSI Design
Chih-Cheng Hsieh
Decoders
8- 13
Static CMOS
A1
Pseudo-nMOS
A1
A0
VLSI Design
A1
A0
A0
1/2
word
A0
A1
word0
word0
word1
word1
word2
word2
word3
word3
16
word
Chih-Cheng Hsieh
Decoder Layout
8- 14
A3
A2
A2
A1
A1
A0
A0
VDD
word
GND
NAND gate
VLSI Design
buffer inverter
Chih-Cheng Hsieh
Large Decoders
8- 15
A2
A1
A0
word0
word1
word2
word3
word15
VLSI Design
Chih-Cheng Hsieh
Predecoding
8- 16
A3
A2
A1
A0
predecoders
1 of 4 hot
predecoded lines
word0
word1
word2
word3
word15
VLSI Design
Chih-Cheng Hsieh
Column Circuitry
8- 17
VLSI Design
Chih-Cheng Hsieh
Bitline Conditioning
8- 18
bit
VLSI Design
bit_b
Chih-Cheng Hsieh
Sense Amplifiers
8- 19
tpd (C/I) DV
VLSI Design
Chih-Cheng Hsieh
8- 20
sense_b
bit
P1
N1
P2
N2
sense
bit_b
N3
VLSI Design
Chih-Cheng Hsieh
8- 21
bit_b
isolation
transistors
sense_clk
regenerative
feedback
sense
VLSI Design
sense_b
Chih-Cheng Hsieh
Twisted Bitlines
8- 22
VLSI Design
Chih-Cheng Hsieh
Column Multiplexing
8- 23
VLSI Design
Chih-Cheng Hsieh
8- 24
B2 B3
B4 B5
B6 B7
B0 B1
B2 B3
B4 B5
B6 B7
A0
A0
A1
A1
A2
A2
Y
VLSI Design
Chih-Cheng Hsieh
8- 25
A0
B0 B1
B2 B3
VLSI Design
Chih-Cheng Hsieh
8- 26
2
More
Cells
More
Cells
word_q1
A0
A0
write0_q1
write1_q1
data_v1
VLSI Design
Chih-Cheng Hsieh
Multiple Ports
8- 27
VLSI Design
Chih-Cheng Hsieh
Dual-Ported SRAM
8- 28
bit_b
wordA
wordB
Chih-Cheng Hsieh
Multi-Ported SRAM
8- 29
bD bE bF bG
wordA
wordB
wordC
wordD
wordE
wordF
wordG
write
circuits
read
circuits
VLSI Design
Chih-Cheng Hsieh
SRAM Scaling
VLSI Design
8- 30
Chih-Cheng Hsieh
Outline
1.
2.
3.
4.
5.
6.
VLSI Design
8- 31
SRAM
DRAM
Read-Only Memory (ROM)
Serial Access Memory
Content-Addressable Memory
Programmable Logic Array
Chih-Cheng Hsieh
DRAM
DV
VLSI Design
8- 32
Ccell
VDD
2 Ccell Cbit
Chih-Cheng Hsieh
Subarray Architecture
VLSI Design
8- 33
Chih-Cheng Hsieh
Bitline Architectures
8- 34
Chih-Cheng Hsieh
Bitline Architectures
8- 35
Open bitlines
Folded bitlines
VLSI Design
Chih-Cheng Hsieh
Outline
1.
2.
3.
4.
5.
6.
VLSI Design
8- 36
SRAM
DRAM
Read-Only Memory (ROM)
Serial Access Memory
Content-Addressable Memory
Programmable Logic Array
Chih-Cheng Hsieh
Read-Only Memories
8- 37
VLSI Design
Chih-Cheng Hsieh
ROM Example
8- 38
A1 A0
Word 0: 010101
Word 1: 011001
Word 2: 100101
Word 3: 101010
2:4
DEC
ROM Array
Y5
Y4
Y3
Y2
Y1
Y0
Chih-Cheng Hsieh
8- 39
VLSI Design
Chih-Cheng Hsieh
Row Decoders
8- 40
VLSI Design
Chih-Cheng Hsieh
VLSI Design
8- 41
Chih-Cheng Hsieh
8- 42
Programmable ROMs
Build array with transistors at every site
Burn out fuses to disable unwanted transistors
Gate
Drain
Polysilicon
Floating Gate
Thin Gate Oxide
(SiO2)
n+
n+
p
VLSI Design
bulk Si
Chih-Cheng Hsieh
8- 43
ROM Array
2n wordlines
DEC
inputs
n ROM k
s
outputs
k
s
state
k outputs
VLSI Design
Chih-Cheng Hsieh
Example: RoboAnt
8- 44
Chih-Cheng Hsieh
Lost in space
8- 45
VLSI Design
Chih-Cheng Hsieh
Bonk!!!
8- 46
VLSI Design
Chih-Cheng Hsieh
8- 47
VLSI Design
Chih-Cheng Hsieh
8- 48
VLSI Design
Chih-Cheng Hsieh
Whoops a corner!
8- 49
VLSI Design
Chih-Cheng Hsieh
Simplification
8- 50
VLSI Design
Chih-Cheng Hsieh
Lost
RCCW
Wall1
Wall2
VLSI Design
S1:0
00
00
00
01
01
01
10
10
11
11
11
L
0
1
0
1
0
0
X
X
1
0
0
R
0
X
1
X
1
0
0
1
X
0
1
S1:0
00
01
01
01
01
10
10
11
01
10
11
TR
0
0
0
0
0
0
1
1
0
0
0
TL
0
0
0
1
1
1
0
0
1
1
1
8- 51
F
1
1
1
0
0
0
1
1
1
1
1
Chih-Cheng Hsieh
ROM Implementation
16-word x 5 bit ROM
8- 52
S1 S0 L R
0000
L, R
TL, TR, F
ROM
0001
0010
0100
4:16 DEC
S'1:0
S1:0
0011
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VLSI Design
Chih-Cheng Hsieh
ROM Implementation
16-word x 5 bit ROM
8- 53
S1 S0 L R
0000
L, R
TL, TR, F
ROM
0001
0010
0100
4:16 DEC
S'1:0
S1:0
0011
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VLSI Design
Chih-Cheng Hsieh
Outline
1.
2.
3.
4.
5.
6.
VLSI Design
8- 54
SRAM
DRAM
Read-Only Memory (ROM)
Serial Access Memory
Content-Addressable Memory
Programmable Logic Array
Chih-Cheng Hsieh
8- 55
VLSI Design
Chih-Cheng Hsieh
Shift Register
8- 56
clk
Din
Dout
8
VLSI Design
Chih-Cheng Hsieh
8- 57
clk
11...11
reset
VLSI Design
counter
counter
00...00
readaddr
writeaddr
dual-ported
SRAM
Dout
Chih-Cheng Hsieh
8- 58
delay2
SR1
delay3
SR2
VLSI Design
delay4
SR4
delay5
SR8
SR16
SR32
Din
delay1
Dout
delay0
Chih-Cheng Hsieh
8- 59
clk
Sin
P0
VLSI Design
P1
P2
P3
Chih-Cheng Hsieh
8- 60
P0
P1
P2
P3
shift/load
clk
Sout
VLSI Design
Chih-Cheng Hsieh
Queues
8- 61
VLSI Design
ReadClk
Queue
ReadData
EMPTY
Chih-Cheng Hsieh
8- 62
Chih-Cheng Hsieh
Outline
1.
2.
3.
4.
5.
6.
VLSI Design
8- 63
SRAM
DRAM
Read-Only Memory (ROM)
Serial Access Memory
Content-Addressable Memory
Programmable Logic Array
Chih-Cheng Hsieh
CAMs
8- 64
data/key
read
CAM
match
write
VLSI Design
Chih-Cheng Hsieh
8- 65
bit_b
word
cell_b
cell
match
VLSI Design
Chih-Cheng Hsieh
CAM cell
clk
address
weak
miss
match0
row decoder
8- 66
match1
match2
match3
read/write
column circuitry
Miss line
data
Chih-Cheng Hsieh
Outline
1.
2.
3.
4.
5.
6.
VLSI Design
8- 67
SRAM
DRAM
Read-Only Memory (ROM)
Serial Access Memory
Content-Addressable Memory
Programmable Logic Array
Chih-Cheng Hsieh
PLAs
8- 68
OR Plane
bc
abc
abc
b
Inputs
VLSI Design
cout
Outputs
Chih-Cheng Hsieh
Minterms
ac
ab
abc
abc
NOR-NOR PLAs
8- 69
OR Plane
bc
bc
ac
ab
abc
abc
ac
abc
abc
abc
ab
abc
abc
abc
a
s
VLSI Design
AND Plane
OR Plane
cout
c
s
cout
Chih-Cheng Hsieh
8- 70
OR Plane
bc
ac
ab
abc
abc
abc
abc
c
s
VLSI Design
cout
Chih-Cheng Hsieh
8- 71
VLSI Design
Chih-Cheng Hsieh
8- 72
L
0
1
0
1
0
0
X
X
1
0
0
R
0
X
1
X
1
0
0
1
X
0
1
S1:0
00
01
01
01
01
10
10
11
01
10
11
TR
0
0
0
0
0
0
1
1
0
0
0
TL
0
0
0
1
1
1
0
0
1
1
1
F
1
1
1
0
0
0
1
1
1
1
1
TR S1 S0
TL S0
F S1 S0
VLSI Design
Chih-Cheng Hsieh
8- 73
OR Plane
TR S1 S0
S0
S1
S0
LS 0
TL S0
F S1 S0
LS1
R
LRS 0
LS1
S1 S 0
S1
S0
S1 ' S0 ' TR
VLSI Design
TL F
Chih-Cheng Hsieh
TL, TR, F
ROM
8- 74
S'1:0
S1:0
S1 S0 L R
AND Plane
OR Plane
0000
0001
S0
S1
S0
LS 0
0010
0011
0100
4:16 DEC
0101
LS1
R
LRS 0
LS1
S1 S 0
0110
0111
1000
1001
1010
1011
1100
1101
S1
1110
S0
S1 ' S0 ' TR
1111
TL F
VLSI Design
Chih-Cheng Hsieh
8- 75
Chih-Cheng Hsieh
Alpha Particles
8- 76
-particle
WL
VDD
BL
n+
SiO2
_
_
_
Chih-Cheng Hsieh
8- 78
Fuse bank
Redundant row
Redundant columns
Row
address
Column
address
VLSI Design
Chih-Cheng Hsieh
VLSI Design
8- 79
Chih-Cheng Hsieh