Power Estimation using Synopsys PrimeTime

ECE5745 Tutorial 5 (Version 606ee8a)

January 30, 2016
Derek Lockhart

Contents
1
2
3
4
5

Introduction . . . . . . . . . . . . . . . .
Getting The Tutorial Code . . . . . . .
Manual PrimeTime Build Process . . .
Automated PrimeTime Build Process .
Acknowledgements . . . . . . . . . . . .

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1
1
3
4
5

Introduction

In this tutorial you will gain experience generating power estimates from gate-level simulations using Synopsys PrimeTime. PrimeTime takes a placed and routed design and a simulation waveform as input, then
produces several gate-level static timing analysis reports as output. Figure 1 illustrates the PrimeTime
toolflow and how it fits into the larger ECE5745 flow.
PrimeTime PX is an add-on feature to PrimeTime that analyzes power dissipation of a cell-based design.
PrimeTime PX supports two types of power analysis modes: averaged and time-based. Averaged mode
calculates average power based on toggle rates, while time-based mode provides both peak and average
power using gate-level simulation activity.
Performing power analysis gives us the opportunity to compare our designs with respect to an increasingly
important metric: energy. Combined with the area and execution time results obtained from IC Compiler
and VCS, we can now fully evaluate the tradeoffs offered by competing system architectures.
For this tutorial we will be performing power analysis on the netlist of the synthesized, placed, and routed
greatest common divisor (GCD) circuit, which you should have generated in Tutorial 3. Switching information will be provided by the vcd file generated during gate-level simulation in Tutorial 4.
Note that this tutorial is by no means comprehensive. Synopsys documentation is located on the public
course webpage (http://www.csl.cornell.edu/courses/ece5745/syndocs) and can be accessed using
the username and password distributed in lecture.

Getting The Tutorial Code

All of the ECE5745 tutorials should be run on the BRG compute servers brg-01.ece.cornell.edu and
brg-02.ece.cornell.edu. Before proceeding further, please log into one of these machines.
You should follow along through the tutorial yourself by typing in the commands marked with a % symbol
at the shell prompt. To cut and paste commands from this tutorial into your bash shell (and make sure bash
ignores the % character) use an alias to undefine the % character:
% alias %=""
Once you have logged into a BRG machine you will need to setup the ECE5745 toolflow with the following
commands:
% source setup-ece5745.sh

(Version 606ee8a), Spring 2013

Verilog
Source
(.v)

Verilog
Testbench
(.v)

Standard
Cell Models
(.v)

Standard Cell
Library
(see below)

Constraints
(.tcl)

TLU+ Files
(.tluplus)

Design
Compiler

iverilog

VCS

RTL
Simulator
(a.out)

RTL
Simulator
(simv)

Delay File
(.sdf)

./a.out

./simv

VCS

Test
Results
(.out)

Waveform
(.vpd or
.vcd)

RTL
Simulator
(simv)

GTKWave

./simv

Test
Results
(.out)

Waveform
(.vcd)

IC
Compiler

Gate Level
Netlist
(.v)

Timing &
Area

Constraints
File
(.sdc)

Design
Vision GUI

IC
Compiler

Parasitics
(sbpf.min,
sbpf.max)

Gate Level
Netlist
(.v)

Delay File
(.sdf)

Floor Plan

Constraints
File
(.sdc)

Timing &
Area

Layout

IC
Compiler
GUI

VCS

Post-P&R
Simulator
(simv)
Standard Cell Library:

RTL Simulation

Technology Library (.db)

Milkyway Reference DB (.fr)
Technology File (.tf)
Mapping File (.map)

./simv

GTKWave

Test
Results
(.out)

Waveform
(.vcd)

Synthesis
Place & Route
Gate-Level Simulation

GTKWave

VCD2SAIF

Power Estimation
(Optional Flow Elements)
Activity File
(.saif)

Figure 1: VCS Toolflow

PrimeTime

Power
Estimates

(Version 606ee8a), Spring 2013

For this tutorial you will be using a GCD circuit as your example design. If you dont already have the source
files from the previous tutorials, create an ece5745 folder in your home directory and clone the tutorial files
from the git repository:
%
%
%
%
%

mkdir ${HOME}/ece5745
cd ${HOME}/ece5745
git clone git@github.com:cornell-ece5745/ece5745-tut-asic.git
cd ece5745-tut-asic/tutorial
TUTROOT=$PWD

Before starting, take a look at the subdirectories in the project directory. Note that there are directories for
your RTL source (src) and for generated content (build). The build directory has subdirectories for each
major step in the ECE5745 toolflow, these subdirectories contain scripts and configuration files necessary
for running the tools. For this tutorial you will work primarily in the pt-pwr subdirectory.

Manual PrimeTime Build Process

We will first go through the commands for the tool manually so that you can see all the different steps
required to make the tool work. Since this is extremely tedious, we will only do this once, and later we will
use scripts to automate the steps in this portion of the flow for us.
Before we can generate averaged mode Primetime power reports, we need to create a switching activity file
(saif) from our gate-level vcd waveform:
% cd $TUTROOT/build/vcs-sim-gl-par
% make convert
Now that we have our switching activity file, use the following commands to launch the PrimeTime shell:
% cd $TUTROOT/build/pt-pwr
% pt_shell
You should be left at the PrimeTime shell prompt from which you can can execute various commands to load
your design, analyze the design, print reports, etc. You can get more information about a specific command
by entering man <command> at the pt shell prompt.
Execute the following commands manually in the pt shell> prompt. The first command will create an alias
to undefine the pt shell> string, which will allow you to cut and paste commands from this tutorial into
PrimeTime.
# Create an alias for copy and paste.
pt_shell> alias "pt_shell>" ""
# Setup the environment. Enable the power analysis mode.
pt_shell>
pt_shell>
pt_shell>
pt_shell>
pt_shell>

set
set
set
set
set

stdcells_home /research/brg/install/bare-pkgs/noarch/synopsys-90nm/toolflow
search_path "$stdcells_home"
target_library "cells.db"
link_path "* $target_library"
power_enable_analysis "true"

# Read the post place and route gate-level netlist into PrimeTime PX.
pt_shell> read_verilog "../icc-par/current-icc/results/gcdGCDUnit_rtl.output.v"

(Version 606ee8a), Spring 2013

pt_shell> current_design "gcdGCDUnit_rtl"

pt_shell> link
# Averaged mode power analysis uses the saif format. Read the parasitics
# generated by IC Compiler before you run report_power.
pt_shell> set power_analysis_mode "averaged"
pt_shell> read_saif "../vcs-sim-gl-par/check.saif" \
-strip_path "gcdTestHarness_rtl/gcd"
pt_shell> report_switching_activity -list_not_annotated
pt_shell> read_parasitics -increment \
-format sbpf "../icc-par/current-icc/results/gcdGCDUnit_rtl.output.sbpf.max"
pt_shell> report_power -verbose -hierarchy
# Time-based power analysis takes the vcd format as an input. Read the parasitics
# and run report power. You will see the estimated peak power as well as the
# average power.
pt_shell> set power_analysis_mode "time_based"
pt_shell> read_vcd "../vcs-sim-gl-par/check.vcd" \
-strip_path "gcdTestHarness_rtl/gcd"
pt_shell> report_switching_activity -list_not_annotated
pt_shell> read_parasitics -increment \
-format sbpf "../icc-par/current-icc/results/gcdGCDUnit_rtl.output.sbpf.max"
pt_shell> report_power -verbose -hierarchy
You can now use various commands to perform further analysis on your design and display more reports.
Using the shell directly is useful for finding out more information about a specific command or playing with
various options, but for reproducibility and convenience reasons you will primarily use TCL scripts to control
this tool.
The final step in the Manual process is to exit the PrimeTime shell.
pt_shell> exit

Automated PrimeTime Build Process

Typing each command via the commandline is a tedious and error-prone process, and should typically be
avoided. Instead, we make use of scripts to automate the process of building our tools for us. The following
commands will first delete the simulator you previously built, and then regenerate it using the makefile.
% cd $TUTROOT/build/pt-pwr
% make
PrimeTime will generate several reports, which the build scripts store in pt-pwr/current-pt/reports. The
reports we are most interested in are the power reports. To look at the power reports, execute the following
commands:
% cd $TUTROOT/build/pt-pwr/current-pt/reports
% cat check.power.avg.max.report
% cat check.power.time.max.report

(Version 606ee8a), Spring 2013

There are two different power reports generated by primetime: one for averaged mode analysis and one for
time-based analysis. The time-based analysis provides additional information, such as peak power consumed,
at what time peak power was reached in the simulation, as well as glitching power (which should always be
zero when using the simple-stdcells). Both averaged and time based modes should provide a hierarchical
power breakdown that indicates how much power is consumed by each submodule in the design. Units are
provided in the report above the results table.
Keep in mind that the power reports we are generating for this tutorial are based on the waveforms generated
from the unit tests. In the labs, we will not be using the test harness as the source of our waveforms, instead
we will be using waveforms generated by the simulation harness (run.vcd). This will allow us to more
easily experiment with various input vectors and compare how different workloads influence performance
and energy consumption.

Acknowledgements

Many sources have contributed to the content of this tutorial. The original material for this tutorial was
developed as a lab for the CS250 VLSI Systems Design course at University of California at Berkeley by Yunsup Lee. Contributors include: Krste Asanovic, Christopher Batten, John Lazzaro, and John Wawrzynek.
Versions of that lab have been used in the following courses:
CS250 VLSI Systems Design (2009-2011) - University of California at Berkeley
CSE291 Manycore System Design (2009) - University of California at San Diego