EL302

DIGITAL INTEGRATED CIRCUITS

DESIGN PROJECT#2

NOR2 and NAND2 GATES DESIGN

FINAL REPORT

TOLGA DN
9303

SABANCI UNIVERSITY
SPRING 2008-2009

1. ITRODUCTIO
1.1. Design Specifications: In this project we are assumed to perform the schematic and
layout design of 2 input variables NOR and NAND CMOS logic gates, that can fit into a
layout width, scale of 1.4
m with minimum area so that given static (Vth=1.65V) and
dynamic(   < 500    = 100) characteristics of gates are

obtained, by using AMS 0.35
m CMOS technology in Cadence CAD tool. The designs
should satisfy the following additional specifications:

Cell hight H=19.6 m,

Standard cell layout (i.e., suitable for automated place and route).

MET1 only! No other metal layers can be used for routing within the cell.

Use pmos4 and nmos4 from the parametric cell library.

All cells have an n-well area of same height with inverter designed in previous project.

1.2. Basics of CMOS OR and AD:

Figure1: A two-input CMOS NOR gate (left) and a two-input CMOS NAND gate with corresponding truth
tables

The CMOS NOR gate circuit diagram and corresponding truth table is given in Fig1
and as seen in figure, Boolean OR operation is obtained by the parallel connection of the two
enhancement type of nMOS driver transistors whereas AND function is obtained by the series
connection of the two nMOS driver transistors. Also inversion is provided by the natural
operation of MOS circuit operation (eg. If either one input (A or B) or both inputs are logic
high, the corresponding transistors turns on and output node is pulled down to ground for

NOR gate). Similarly if both inputs A and B are logic high simultaneous, output node is
pulled down to ground as a result of nature of MOS circuit operation. In short, for NAND or
NOR gates, the output is connected to VDD or to ground for any given input combination
which lead to  =  ,  = 0 .

1.3. Design of 2 Inputs OR and AD Gates:

The output voltage of the 2 inputs CMOS NOR and NAND gate will take  =  ,  =

0 as mentioned in previous part. Therefore the matter of CMOS and NAND logic gate design

can be reduced to arranging  ( switching threshold voltage defined as  =  =
$%%

 !  " = # ) to desired voltage value (

/

&

 ') )*+,'). Thus we obtain the

drivers transconductance ratio -. = /0, and by using this ratio and time delay calculation we
1

can decide on the particular transistor dimensions for given specifications.

1.3.1. Design of 2 Inputs CMOS OR gate based on Hand Calculations:
 of the NOR2 gate can be calculating by transforming NOR2 to equivalent inverter as seen
in Fig2.

Figure 2: 2 Inputs CMOS NOR and its equivalent inverter.

As seen in Fig2., the parallel connected nMOS drivers can be modeled by a single nMOS

driver with 234 and series connected pMOS transistors are modelled as a pMOS transistor

with 35 /2 .

Recall: Threshold expression of CMOS inverters is as follow

89: =

8;<,4 =>3 A8BB =8;<,5 C

@

?
?=>3
@

for

3@ = 34
5

By using the threshold expression of CMOS inverter and equivalent inverter transconductance
values (234 D4E 35 /2),

89: (GH@2) =

8;<,4 + J

35
A8 + 8;<,5 C
K34 BB

?+J

35
K34

By using given process parameters;  = 3.3, MN, = 0.55, MN,O = 0.62, thus -.
found as 0.219.

-. =
According to given design parameters
 
U
160 T V W

U
56.7 T V W
O

 

U
TVW

U

O  S T W
V O

S = 160
X/ ,

= 0.219 ,

O 

S = 56.7
X/ ,
2

([)5 ?2. ]^([)4

Since we are given dynamic specification as (   < 500    = 100)

we need to use    expression(eq.1 and eq.2) to find out minimum transistor
dimensions which satisfies given time delays.

Eq.1

Eq.2

If we compare Eq.1 and Eq.2, it is noticed that for MN, _ |MN,O |,, ratio between high-to-low
high
3

and low-to-high
high time delays may roughly determined by the 3@ = 34 ratio. For our case, we
3

had found 3@ = 34 =0.2 and since the time delay is inversely proportional with
5

transconductance ratios, high-to

to-low
low propogation delay will be dominant and it is sufficient to
ensure that  < 500 .. Therefore by using Eq.1 we obtained the minimum width as
Wn=0.2um that is required to satisfy given time delay specification. Since minimum

permitted width is 0.4um in AMS 0.35um process, minimum transistor widths calculated as

([)4 = <.
< Kab

([)5 ?2. ]^([)4 = c. ?ab

1.3.2.. Design of 2 Inputs CMOS AD gate based on Hand Calculations:

Similar
milar to NOR2 calculations,  of the NAND2 gate can be calculating by transforming

NAND2 to equivalent inverter as seen in Fig3.

Figure 3: 2 Inputs CMOS NAND and its equivalent inverter.

As seen in Fig2,, the parallel connected nMOS drivers can be modeled by a single nMOS

driver with 34 /2 and series connected pMOS transistors are modelled as a pMOS transistor
with 235 .

By using the threshold expression of CMOS inverter and equivalent inverter

transconductance values (34 /2

2 D4E 235 ),
89: (GH@2) =

8;<,4 + J

35
A8 + 8;<,5 C
K34 BB

?+J

35
K34

By using given process parameters 35 dea4E Df <. 2]c (3@ = g. <c)

4

According to given design parameters
 

S = 160
X/ ,

U
160 T W
V 
= 3.5 ,
U
56.7 T W
V O
3

O 

S = 56.7
X/ ,
2

([)5 <. ]<c([)4

For our case, we had found 3@ = 34 =3.5 and since the time delay is inversely proportional
5

with transconductance ratios, low-to-high propogation delay will be dominant and it is

sufficient to ensure that  < 500 . Therefore by using Eq.2 we obtained the minimum

pMOS width as Wp=0.5um (in order to decrease time delay maximum available width for
minimal area is used) that is required to satisfy given time delay specification.

1.4. Schematic Design of 2 Inputs OR gate:

Figure 4: Shematic Wiev of 2 Inputs NOR gate.

As seen in Fig4, transistor dimensions for nMOS and pMOS transistors are Wn=0.7um and
Wp=9.6um. In hand calculations we had found the minimum dimensions which satisfly 500ps
propogation delays as 0.4um and 5.1um, but here larger transistor dimensions are used since

as the Wn and Wp increase 34 and 35 increase and this increase in transconductance ratios
lead to smaller time delays.
(Recall:    ) )h,,i  ') j)' 34 klm 35 )

Also according to standart cell layout rules we need to use nwell with same height(13.1um) as
inverter designed in previous lab. The maximum pMOS transistor that fits 13.1um height and
assure 1.65V switching threshold voltage was found 9.6um(Paramatric Anaylsis conducted to
find out dimensions of transistors which satisfies the Vth condition). Another reason to chose
larger transistor dimentions in schematic level design was that we want to increase driving
strength of each nMOS transistor so that high to low propogation delay in worst case is not so
large. Also the ratio of Wp/Wn is 13.7 for the schematic level design and this value is close to
ratio found in hand calculations (12.86).

1.4.1. Schematic Level Simulations of OR2

Figure 5: DC Analysis of NOR2 to detect Vth

As seen in Fig.5, switching threshold voltage of NOR2 is exactly 1.65 in schematic level
design for 9.6um and 0.7um pMOS and nMOS transistor widths respectively. In order to
measure Vth, both inputs of NOR2 is connected together (" = # ) and input voltage is swept
from 0V to 3.3V . Vth is the defined as Vout=Vin=Vth.

Figure 6: Low-to-High Time Delay of NOR2 gate.

 is measured when NOR2 behaves like inverter (inputs connected) and 2 worst cases. As
seen in Fig6,  is 261ps when both inputs are connected, 287ps for one of the worst cases
and 250 for the other.  does not change so much for inverter and worst case circuits since
it is mainly determined by driving strength of pMOS transistors (-O ).

Figure 7: High-to-Low Time Delay of NOR2 gate.

 is measured when NOR2 behaves like inverter (inputs connected) and 2 worst cases. As
seen in Fig6,  is 330ps when both inputs are connected, 792ps for one of the worst cases
and 672ps for the other.There is a big difference between  values for inverter case and
worst cases since effective driving strength is 2kn when both inputs are connected together
while the driving strength is kn when one of the inputs are connected to logic low level.
1.4.2. Layout of CMOS OR2 Gate

Figure 7: Layout of NOR2 gate and parasitic capacitance extraction

As seen in Fig.7, NOR gate covers an aren 5.6um X 19.6um and extracted capacitances are
mainly located around and between POLY1 and MET1 path. All of the parasitic capacitances
are lower than 1fF and largest capacitance is 952aF. We expect a variaton in dynamic

response of NOR2 gate because of these parasitic capacitances but their effects can not be
catastrophic.

Figure 8: Values of Extracted Parasitics Capacitances

1.4.3. Post-Layout Simulation of OR2 Gate

Figure 9: Post-Layout VTC Graph of NOR2 to detect Vth

It can be seen in Fig.9,  becomes in the range 1.65029 to 1.65958 when parasitic
capacitances are considered and given  specification is acquired although there is a tiny
difference between schematic and post-layout simulations.

Figure 10: Symbol of

NOR2 gate

Figure 11: Low-to-High Time Delay for Post Layout of NOR2 gate.

As seen in Fig11,  is 272ps when both inputs are connected(inverter case), 278ps for one
of the worst cases and 256 for the other.As seen there low-to-high time delays are increased in
the post-layout simulation as a result of contribution of parasitic capacitances to Cload. 
does not change so much for inverter and worst cases since it is mainly determined by driving
strength of pMOS transistors (-O ) as stated in schematic level.

Figure 12: High-to-Low Time Delay for Post Layout of NOR2 gate.

As seen in Fig12,  is 342ps when both inputs are connected, 745ps for one of the worst
cases and 635ps for the other.There is a big difference between  values for inverter case
and worst cases since effective driving strength is 2kn when both inputs are connected
together while the driving strength is kn when one of the inputs are connected to logic low
level. High-to-low post-layout time delay when both inputs connected together is larger then
the value found in schematic level by 12ps where as worst case time delays decreased in the
post layout simulations by aproximately 45ps.
1.5.Schematic Design of 2 Inputs AD Gate

Figure 13: Shematic Wiev of 2 Inputs NAND gate.

As seen in Fig4, transistor dimensions for nMOS and pMOS transistors are Wn=3.05um and
Wp=2.7um. Here larger transistor dimensions than calculations are used since as the Wn and
Wp increase 34 and 35 increase and this increase in transconductance ratios lead to smaller
time delays.
Also according to standart cell layout rules we need to use nwell with same height(13.1um) as
inverter designed in previous lab. The maximum nMOS transistor that fits between 13.1um
height nwell and GND MET1 and satisfy 1.65V switching threshold voltage was found
3.05um(Paramatric Anaylsis conducted to find out dimensions of transistors which satisfies
the Vth condition). Another reason to chose larger transistor dimentions in schematic level
design was that we want to increase driving strength of each pMOS transistor so that low to
high propogation delay in worst case is not so large. Also the ratio of Wp/Wn is 0.88 for the
schematic level design and this value is close to ratio found in hand calculations (0.805).

1.5.1.Schematic Level Simulations of AD2

Figure 14: DC Analysis of NAND2 to detect Vth

As seen in Fig.14, switching threshold voltage of NAND2 is exactly 1.65 in schematic level
design for 2.7um and 3.05um pMOS and nMOS transistor widths respectively. In order to
measure Vth, both inputs of NAND2 is connected together (" = # ) and input voltage is
swept from 0V to 3.3V.

Figure 15: Low-to-High Time Delay of NAND2 gate in schematic level.

 is measured when NOR2 behaves like inverter (inputs connected) and 2 worst cases. As

seen in Fig6,  is 200ps when both inputs are connected, 402ps for one of the worst cases
and 374ps for the other. There is a big difference between  values for inverter case and
worst cases since effective driving strength of pMOS network is 2kp when both inputs are

connected together while the driving strength is kp for pMOS network when one of the inputs
are connected to logic high level(thus one of the pMOS transistors is off and driving strength
reduced).

Figure 16: High-to-Low Time Delay of NAND2 gate in schematic level.

As seen in Fig16,  is 223.5ps when both inputs are connected, 211ps for one of the worst
case circuits and 218.9ps for the other.There is no significant difference between  values

for inverter case and worst case circuits since  is determined by driving strength of

nMOS transistors (- ).

Based on simulations of schematic level NAND and NOR, it is obvious that their operating
principles are exactly dual.

1.5.2. Layout of CMOS AD2 Gate

Figure 17: Layout of NAND2 gate and parasitic capacitance extraction

As seen in Fig.17, NAND gate covers an aren 5.6um X 19.6um and extracted capacitances are
mainly located around I/O pads. Most of the parasitic capacitances are lower than 1fF and
largest capacitance is 1.342fF.

1.5.3. Post-Layout Simulation of AD2 Gate

Figure 18: Post-Layout VTC Graph of NAND2 to detect Vth

It can be seen in Fig.18,  becomes 1.648V when parasitic capacitances are considered and

it is good enough according to given  = 1.65 specification. Change in  values between
schematic and layout is larger for NAND than NOR and it is reasonable since we had larger

parasitic capacitances caused by long POLY paths in NAND2.

Figure 19: Symbol of NAND2 gate and circuits used in Post-Layout Simulations

Figure 20: Low-to-High Time Delay for Post Layout of NAND2 gate.

As seen in Fig20,  is 207ps when both inputs are connected(inverter case), 383ps for one
of the worst cases and 385 for the other.As seen there low-to-high time delays are decreased
in the post-layout simulation.

Figure 21: High-to-Low Time Delay for Post Layout of NAND2 gate.

As seen in Fig12,  is 225.9ps when both inputs are connected, 214.4ps for one of the
worst case circuits and 211.4ps for the other. High-to-low post-layout time delay when both
inputs connected together is larger then the value found in schematic level by 2ps where as
worst case time delays decreased in the post layout simulations by aproximately 3-4ps.

1.6. Standart Cell Layout for Mixture of AD2, OR2 and CMOS IVERTER

Figure 22: Combinations of NOR, NAND and CMOS Inverter

The Standart Cell Layout Rules checked by using the combination of gates designed so far as
seen in Fig.22. No DRC Error is occured.Therefore they are available for automated placing
and routing.

1.7.Conclusion
nopq
noqp
Worst Case
1nopq
Worst Case 1
noqp
Worst Case 2
nopq
Worst Case 2
noqp
89:

NAND2

NAND2 (AV EXT)

NOR2

NOR2 (AV EXT)

223.5ps
200ps
211ps

225.9ps
207ps
211.4ps

330ps
261ps
792ps

342ps
272ps
745ps

402ps

385ps

287ps

278ps

218.9ps

214.4ps

672ps

635ps

374ps

383ps

250ps

256ps

1.65V

1.648V

1.65V

1.656V

Layout Areas:

Transistor Widths

NAND2 : 5.6um x 19.6um

Wp=2.7um, Wn=3.05um

NOR2

Wp=9.6um, Wn=0.7um

:5.6um x 19.6um