UNIT-II

Block diagram MSP430x5xx series:

Functional block diagram of MSP430F5438:

Description:
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several
devices featuring different sets of peripherals targeted for various applications. The architecture,
combined with five low-power modes, is optimized to achieve extended battery life in portable
measurement applications.
The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that
contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the
device to wake up from low-power modes to active mode in less than 5 s.
The MSP430F543x and MSP430F541x series are microcontroller configurations with three 16bit timers, a high-performance 12-bit analog-to-digital converter (ADC), up to four universal
serial communication interfaces (USCIs), a hardware multiplier, DMA, a real-time clock (RTC)
module with alarm capabilities, and up to 87 I/O pins.
Typical applications for this device include analog and digital sensor systems, digital motor
control, remote controls, thermostats, digital timers, and hand-held meters.

Bootstrap Loader (BSL):

The BSL enables users to program the flash memory or RAM using a UART serial interface.
Access to the device memory via the BSL is protected by an user-defined password. Usage of the
BSL requires four pins as shown in below table.

BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK
pins.
The BSL enables the user to control the activity of the MSP430 and to exchange data using a
personal computer or other device.
To avoid accidental overwriting of the BSL code, this code is stored in a secure memory location,
either ROM or specially protected flash. To prevent unwanted source readout, any BSL
command that directly or indirectly allows data reading is password protected.
To invoke the bootloader, a BSL entry sequence must be applied to dedicated pins. After that, a
synchronization character, followed by the data frame of a specific command, initiates the
desired function.

JTAG Operation:
The MSP430 family supports in-circuit programming of flash and FRAM memory through the
JTAG port, which is available on all MSP430 devices. All devices support the JTAG 4-wire
interface. Some devices also support the next-generation optimized 2-wire JTAG (Spy-Bi-Wire)
interface. Using these protocols, an interface connection that can access the MSP430 JTAG port
using a PC or other controller can be established.

1. JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for
sending and receiving data. The JTAG signals are shared with general-purpose I/O. The
TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the
RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device
programmers. The JTAG pin requirements are shown below

2. Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-BiWire interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device
programmers. The Spy-Bi-Wire interface pin requirements are shown below

Flash Memory:
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or insystem by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the
flash memory. Features of the flash memory include:

 Flash memory has n segments of main memory and four segments of information
memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually. Segments A to D are also called information
memory.
Segment A can be locked separately.

RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save
leakage, however all data is lost. Features of the RAM memory include:

RAM memory has n sectors. The size of a sector can be found in Memory Organization.
Each sector 0 to n can be complete disabled, however data retention is lost.
Each sector 0 to n automatically enters low power retention mode when possible.
For Devices that contain USB memory, the USB memory can be used as normal RAM if
USB is not required.

Memory organization:

2.1 I/O PORTS PULL UP/DOWN REGISTERS CONCEPTS

2.1.1 Digital I/O Introduction
MSP430 devices have up to ten digital I/O ports implemented, P1 to P10. Each port has
eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each
I/O line can be individually read from or written to. Ports P1 and P2 have interrupt capability.
Each interrupt for the P1 and P2 I/O lines can be individually enabled and configured to provide
an interrupt on a rising edge or falling edge of an input signal. All P1 I/O lines source a single
interrupt vector, and all P2 I/O lines source a different, single interrupt vector. The digital I/O
features include:
_ Independently programmable individual I/Os
_ Any combination of input or output
_ Individually configurable P1 and P2 interrupts
_ Independent input and output data registers
2.1.2 Digital I/O Operation
The digital I/O is configured with user software. The setup and operation of the digital I/O is
described in the following sections. Each port register is an 8-bit register and is accessed with
byte instructions. Registers for P7/P8 and P9/P10 are arranged such that the two ports can be
addressed at once as a 16-bit port. The P7/P8 combination is referred to as PA and the P9/P10
combination is referred to as PB in the standard definitions file. For example, to write to P7SEL
and P8SEL simultaneously, a word write to PASEL would be used. Some examples of accessing
these ports follow:
BIS.B #01h,&P7OUT ; Set LSB of P7OUT.; P8OUT is unchanged
MOV.W #05555h,&PAOUT ; P7OUT and P8OUT written; simultaneously
CLR.B &P9SEL ; Clear P9SEL, P10SEL is unchanged
MOV.W &PBIN,&0200h ; P9IN and P10IN read simultaneously; as 16-bit port.
Input Register PxIN
Each bit in each PxIN register reflects the value of the input signal at the corresponding I/O pin
when the pin is configured as I/O function.
Bit = 0: The input is low
Bit = 1: The input is high
Note: Writing to Read-Only Registers PxIN
Writing to these read-only registers results in increased current consumption while the write
attempt is active.
Output Registers PxOUT

Each bit in each PxOUT register is the value to be output on the corresponding I/O pin when the
pin is configured as I/O function and output direction.
Bit = 0: The output is low
Bit = 1: The output is high
Direction Registers PxDIR
Each bit in each PxDIR register selects the direction of the corresponding I/O pin, regardless of
the selected function for the pin. PxDIR bits for I/O pins that are selected for other module
functions must be set as required by the other function.
Bit = 0: The port pin is switched to input direction
Bit = 1: The port pin is switched to output direction
Pullup/Pulldown Resistor Enable Registers PxREN (MSP430F47x3/4 and MSP430F471xx
only)
In MSP430F47x3/4 and MSP430F471xx devices all port pins have a programmable
pullup/pulldown resistor. Each bit in each PxREN register enables or disables the
pullup/pulldown resistor of the corresponding I/O pin. The corresponding bit in the PxOUT
register selects if the pin is pulled up or pulled down.
Bit = 0: Pullup/pulldown resistor disabled
Bit = 1: Pullup/pulldown resistor enabled
Function Select Registers PxSEL
Port pins are often multiplexed with other peripheral module functions. See the device-specific
data sheet to determine pin functions. Each PxSEL bit is used to select the pin function I/O
port or peripheral module function.
Bit = 0: I/O function is selected for the pin
Bit = 1: Peripheral module function is selected for the pin
Setting PxSELx = 1 does not automatically set the pin direction. Other peripheral module
functions may require the PxDIRx bits to be configured according to the direction needed for the
module function. See the pin schematics in the device-specific data sheet. ;
Output ACLK on P1.5 on MSP430F41x
BIS.B #020h,&P1SEL ; Select ACLK function for pin
BIS.B #020h,&P1DIR ; Set direction to output *Required*
Note: P1 and P2 Interrupts Are Disabled When PxSEL = 1
When any P1SELx or P2SELx bit is set, the corresponding pins interrupt function is disabled.
Therefore, signals on these pins do not generate P1 or P2 interrupts, regardless of the state of the

corresponding P1IE or P2IE bit. When a port pin is selected as an input to a peripheral, the input
signal to the peripheral is a latched representation of the signal at the device pin. While PxSELx
= 1, the internal input signal follows the signal at the pin. However, if the PxSELx = 0, the input
to the peripheral maintains the value of the input signal at the device pin before the PxSELx bit
was reset.
P1 and P2 Interrupts
Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and
PxIES registers. All P1 pins source a single interrupt vector, and all P2 pins source a different
single interrupt vector. The PxIFG register can be tested to determine the source of a P1 or P2
interrupt.
Interrupt Flag Registers P1IFG, P2IFG
Each PxIFGx bit is the interrupt flag for its corresponding I/O pin and is set when the selected
input signal edge occurs at the pin. All PxIFGx interrupt flags request an interrupt when their
corresponding PxIE bit and the GIE bit are set. Each PxIFG flag must be reset with software.
Software can also set each PxIFG flag, providing a way to generate a software-initiated interrupt.
Bit = 0: No interrupt is pending
Bit = 1: An interrupt is pending
Only transitions, not static levels, cause interrupts. If any PxIFGx flag becomes set during a Px
interrupt service routine or is set after the RETI instruction of a Px interrupt service routine is
executed, the set PxIFGx flag generates another interrupt. This ensures that each transition is
acknowledged.
Note: PxIFG Flags When Changing PxOUT or PxDIR
Writing to P1OUT, P1DIR, P2OUT, or P2DIR can result in setting the corresponding P1IFG or
P2IFG flags.
Note: Length of I/O Pin Interrupt Event
Any external interrupt event should be at least 1.5 times MCLK or longer, to ensure that it is
accepted and the corresponding interrupt flag is set.
Interrupt Edge Select Registers P1IES, P2IES
Each PxIES bit selects the interrupt edge for the corresponding I/O pin.
Bit = 0: The PxIFGx flag is set with a low-to-high transition
Bit = 1: The PxIFGx flag is set with a high-to-low transition
Note: Writing to PxIESx
Writing to P1IES or P2IES can result in setting the corresponding interrupt
flags.

Interrupt Enable P1IE, P2IE

Each PxIE bit enables the associated PxIFG interrupt flag.
Bit = 0: The interrupt is disabled
Bit = 1: The interrupt is enabled
11.2.7 Configuring Unused Port Pins
Unused I/O pins should be configured as I/O function, output direction, and left unconnected on
the PC board, to reduce power consumption. The value of the PxOUT bit is dont care, because
the pin is unconnected. See chapter System Resets, Interrupts, and Operating Modes for
termination of unused pins.

2.2 MSP430 INTERRUPTS

Introduction.
Interrupts are a relatively advanced topic in microprocessor programming. They can be very
useful in control applications particularly when the microprocessor must perform two tasks
apparently at the same time, or when critical timing of program execution is required. Ordinary
subroutines are called using the CALL instruction. Interrupts are very much like hardware
generated CALL's. When an interrupt occurs (and certain other conditions are met), the
microprocessor saves the current state of its program counter and status register on the stack and
jumps to a section of the program which is just like a subroutine, written for the purposes of
servicing (responding to) the interrupt. When this interrupt service routine is complete it executes
a Return From Interrupt (RETI) instruction which restores the saved microprocessor registers to
their original state and the interrupted program carries on from where it left off. Interrupts are
typically generated by a transition (logic 0 to 1 or 1 to 0) on a particular pin on the
microprocessor or by a particular level (0 or 1) on a pin. They can also be caused by circuits
within the microprocessor itself. The MSP430 recognises the interrupts from many sources and
of different priorities. Details are quite model specific however, the 430x44x range support the

interrupts shown in Table 1(taken from TI datasheet). When do you use interrupts? Consider the
following scenario: A microprocessor is to be used to maintain a user interface while at the same
time wait for data to arrive from some serially connected device. This could be achieved by
inserting instructions to read the status of some UART register throughout the controlling
program. This is not a great solution however as it requires the programmer to be very
disciplined (one false move and data could be lost). Interrupts provide a more elegant way of
achieving the same effect. Using interrupts, the programmer writes code to handle the user
interface without worrying about the arrival of data over the serial link. Hardware permitting, the
arrival of a byte of data can be used to generate an interrupt. The processor will briefly stop what
it is doing, grab the newly arrived byte (perhaps process it) and then return to the user interface.
Computers do this sort of multitasking all the time. Another useful feature of interrupts,
particularly with the MSP430 is that they can be used to save power (great for battery
applications). The processor spends most of its time in a low power state, only waking upon
receipt of an interrupt when some event takes place.

Example:
Using the basic timer interrupt. The C-Source code that follows implements a simple real time
clock (apologies in advance if the basic time control register setting is a bit off).

The details of the basic timer will be left to a later note. What is at issue here is the way in which
interrupt handling is coded in C. The first step is to enable the specific interrupt involved via the
interrupt enable register. This is followed by an enabling of the global interrupt flag using the
_EINT() function - this is translated to an eint machine instruction. The other part of the
process of using interrupts it to set the interrupt vector. The IAR C-compiler does this work for
you. The interrupt service routine must be declared as returning no values and accepting no
parameters (after all, it is not called in the traditional manner). The declaration of the function
must be modified using the interrupt modifier. This along with an argument has two effects:

1) It replaces the normal subroutine return instruction with a reti (return from interrupt
instruction)
2) It inserts the address of the function at the specified offset within the interrupt vector table.
( BASICTIMER_VECTOR in this case).
When using interrupts care should be taken to avoid collisions between sections of code that
attempt concurrently use a shared resource (e.g. a port or global variable). Figure 1a shows how
problems of this sort might arise arise. Figure 1b illustrates a mechanism for overcoming this
problem.

Figure 1a. The main program loop wants to set b1 of Port

1. It does this by copying the current byte of Port 1, updates the copy, and then writing the copy
back. However, just after copying the Port contents, an interrupt takes place which modifies the
port (sets b0). The main routine knows nothing of this and overwrites it with a stale copy. Port1.0
and Port1.1 should both be 1 after this but only Port1.1 is.

Figure 1b. In this case, the main loop disables interrupts while it is updating the port
contents.
This prevents the local copy of the port contents from becoming stale however it does run the
risk of interrupts being lost. Some texts would describe the section of code that performs the
update as a critical section i.e. it must not be interrupted. It is generally a good idea to keep
critical sections as short as possible. In some cases other techniques such as locking (using a
global/shared variable) may be more appropriate

2.3 LOW POWER MODES

2.4 ON CHIP PERIPHERALS

2.5 The Watchdog Timer

The internal watchdog of the MSP430 family may be used as a simple timer or as a watchdog
that ensures system integrity. The watchdog function is enabled after power-on reset or a system
reset. This means that if there are difficulties after the start-up of the MSP430, the watchdog will
reset the system as often as it is needed for it to start successfully. The watchdog mode is
described in this chapter.
2.5.1 Supervision of One Task With the Watchdog
In Section 5.7.2.2 Power Fail Detection With the Watchdog, an example is given of how to use
the watchdog for the supervision of a power fail task only. This example shows the necessary
hardware and the software needed to detect an impending power failure. As long as ac line
voltage is present, an interrupt occurs for each polarity change of the ac line. These interrupts
reset the watchdog, preventing it from timing out. If the line voltage falls below a certain level or

fails completely, these interrupts disappear and the watchdog is not reset. When the watchdog
times out, it initializes the MSP430 system.
2.5.2 Supervision of Multiple Tasks With the Watchdog
Normally, the watchdog can only supervise one task at a time. If this task does not reset the
watchdog, the MSP430 is initialized by the watchdog. In complex systems, more than one
function needs to be supervised to assure correct system functionality. This is possible with a
small software effort each supervised function sets a bit in a RAM byte if it runs correctly.
The mainloop then resets the watchdog only if all bits are set. This approach can be enlarged to
any number of supervised functions if more than one byte is used.
Example 64. Watchdog Supervision of Three Functions A system running with MCLK = 3 MHz
uses the watchdog for the supervision of three functions.
Power Fail by the checking of the 60 Hz AC line (see section Battery Check and Power
Fail Detection for details)
Function 1 a check is made if the software reaches this background part regularly
Function 3 a check is made if this interrupt handler is called regularly
Each supervised function sets a dedicated bit in RAM byte WDB in intervals less than 10.66 ms
(power-up value of the watchdog with MCLK = 3 MHz) if everything is functioning normally.
The mainloop checks this byte (WDB) and resets the watchdog ONLY if all three bits are set
(07h). If one of the functions fails, the watchdog is not reset and will therefore reset the system.