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ANANTH SHETTY K R
ananthsetty05@gmail.com, 8105010222
Bengaluru-560054, Karnataka
Career Objective
To work in a environment where I can use my knowledge and experience in the field of VLSI
for the betterment of myself and the organization I work for.
Core Competancy
Good understanding of full custom IC design flow, MOS theory.
Good understanding of IC fabrication process/semiconductor manufacturing.
Worked on technology nodes like 180nm, 90nm and 28nm.
Good understanding of second order effects in MOSFET.
Worked on IC studio simulator from Mentor Graphics, Pyxis Editor and Calibre Verification
tool.
Experienced different types of DRC and LVS errors such as shorts, opens, property errors,
device mismatch, soft-check.
Good understanding of analog layout matching techniques such as inter-digitization and
common-centroid layout.
Good understanding of DFM issues such as Latch-Up, Antenna Effect, OPC, Electro Migration
and ESD.
Basic working knowledge of Linux.
Basic understanding of layout proximity effects such as WPE and LOD.
Education Details
PG Diploma in Advanced Diploma in ASIC Design - Full Custom

2016

RV-VLSI Design Center

Master Degree in Industrial Electronics

2015

SJCE, Mysore, with 8.48 CGPA

Bachelor Degree in Electronics and Communication

2012

KLEIT, Hubli, with 70.1 %

PUC / 12th

2008

Fatima Composite PU College, with 78 %

SSLC

2006

Saint Andrew's English Medium High School, with 82.24 %

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Domain Specific Project

RV-VLSI Design Center
Standard Cell Layout Design Engineer

May-2016 to Jun-2016

9-T Standard Cell Library Design in 90nm Process

Description
Designing the library which consists of cells with varied drive strengths. Layouts drawn should
meet DRC, compatibility and LVS rules respectively. Making the layout more effective by well
sharing, diffusion sharing in order to reduce parasitics.
Tools
ICstudio from Mentor Graphics - 1. Pyxis (Schematic and Layout Editor) 2. Calibre (DRC, LVS
Check)
Challenges
Fitting the layout within the given PR-Boundary and maintaining DRC rules.
Analyzing LVS errors such as nets and instances.
Layout optimization techniques for better floor planning by means of diffusion sharing.
To reduce parasitics by avoiding poly routing and routing using only M1 layer was difficult.

RV-VLSI Design Center

Analog Layout Engineer

Jun-2016 to Jun-2016

Two Stage Op-amp Layout Design in 180nm Process

Description
Designing layout of 2 stage op-amp with different floor plans by using various device matching
techniques and implementing one of them. Sitting of guard rings around active transistors to
avoid latch up. Layout should be DRC and LVS free.
Tools
IC studio from Mentor Graphics - 1. Pyxis: Schematic and Layout Editor 2. Calibre : DRC, LVS
Check
Challenges
Effective floor planning using device matching techniques for sensitive transistor pair.
Placement of dummy transistors for minimum mismatch and providing guard ring for
protection.
To reduce parasitics by avoiding poly routing, by adding more number of contacts in the
diffusion and by fingering.
Maintaining the optimum metal spacing to avoid cross talk.

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RV-VLSI Design Center

Standard Cell Layout Design Engineer

Jun-2016 to Jul-2016

Design of Standard Cells for SRAM in 28nm Process

Description
Designing Leaf Cells for combinational circuits : INVERTER: INVx1, INVx2. NAND: NAND2x1,
NAND2x2, NAND2x4. NOR: NOR3x1, NOR3x2, NOR3x4. AND: AND2x1, AND3x1. OR: OR3x1,
OR3x2, OR3x4 and performing verification process of leaf cells by DRC, LVS Check
Tools
ICstudio from Mentor Graphics - 1. Pyxis : Schematic and Layout Editor 2. Calibre: DRC, LVS
Check
Challenges
Placing contacts and polys on grid.
Reducing the parasitics by making use of metal routing and avoiding poly routing.
Fitting the layout within the given PR-Boundary by considering compatibility rules.
Making the layout as optimized as possible by drain sharing, transistor fingering.

RV-VLSI Design Center

Analog Layout Engineer

Jul-2016 to Aug-2016

Leaf Cells Design of 6-T SRAM in 28nm Process

Description
Layout design of Pre-charge block with MUX factor 4, Sense amplifier block using device
matching techniques, and other blocks such as D-in block, D-out block, Decoder block, Control
Block and Scan block by maintaining proper design constraints
Tools
ICstudio from Mentor Graphics - 1. Pyxis: Schematic and Layout Editor 2. Calibre: DRC, LVS
Check.
Challenges
Designing the floor plan of the whole layout within given area.
Placement of poly and contact on grids.
Placement of pins for easy abutting with neighboring blocks.
To meet the layout constraints.

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B.E / B.Tech Academic Project

KLEIT, Hubli
Blind Navigation and Safety with GSM Modem
Description
1. Gas leakage sensing 2. Fire Sensing 3. Door Break Detection 4. Obstacle Detection and 5.
Outdoor navigation system for blind pedestrians.
Tools
ST-TX01 ASK Tx Module, ST-RX01 ASK Rx Module, HT12E Encoder, HT12D Decoder, MAX
232, APR9600 Voice Processor, GSM Modem. Keil uVision 3.2, Embedded C.
Challenges
1. Maintaining the proper range of distance to receive signals 2. Maintaining the proper delay
between the message segments so that the message is received quickly and appropriately
M.E / M.Tech Academic Project
SJCE, Mysore
A Robust Algorithm for Text Detection in Complex Background Images
Description
1. Detects text of varying sizes, different background, different languages and orientation 2.
To perform Edge Box filtering to filter out the non-text regions 3. To binarize the image by
employing connected component analysis
Tools
MATLAB - Version 8.5 and Release R2015a
Challenges
1. Detecting the text which is partially occluded 2. Detecting the text where text components
are stuck together 3. Detecting the text with varying illumination 4. Detecting the text when
the background of the image is textured

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