Data Transfer Mechanisim

HARDWARE INTERFACING WITH INTEL 8085
Methods of Data Transfer and Interrupt Structure in 8085

Data transfer mechanisms
Data transfer in any microprocessor based system is essential.
The data transfer can take place between processor and memory or
between processor and input device or between processor and output
device or between memory and input device or between memory and
output device.
Data can be transferred in many different ways in all these data
transfers.
18-04-2015 21:24
BIT MESRA RANCHI, JHARKHAND, INDIA
DR. MANOJ KUMAR MUKUL
The data transfer mechanism differs from each other based

on issues like
the addressing of the device,
amount of data transferred,
way of data transfer,
interaction among the devices,
The data transfer mechanism is divided into many types as
followed
a) Based on the addressing of the device
i) I/O mapped I/O access
ii) Memory mapped I/O access
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b) Based on the program and hardware involved

i) Programmed data transfer
Polled mode of data transfer
Interrupt driven data transfer
ii) Direct memory access
Burst mode
Cycle stealing mode
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c) Based on the way how data is transferred and accessed

i) Parallel data transfer
Simple Data transfer
Handshake mode data transfer
ii) Serial data transfer
Synchronous data transfer
Asynchronous data transfer
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Programmed data transfer

Programmed data transfer is written and controlled by programmer and
executed by the processor.
The data transfer between processor and I/O devices or vice versa takes
place by executing the corresponding instruction.
Programmed I/O data transfers are identical to read and write operations
for memories or device registers.
An example of programmed I/O is a device driver writing one data byte at
a time directly to the device's memory.
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The execution of programmed data transfer can take place at

predefined period determined by the programmer.
Based the time of execution of the data transfer instruction,
the programmed data transfer is divided into two types
namely
a) Polled mode of data transfer
b) Interrupt driven data transfer
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In polled mode of data transfer, the data is read from an
input device when the processor or CPU is ready and executes
the data transfer instruction.
If the input device is not ready the processor will wait until
the device is ready with data.
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Similarly, the data is written into an output device by the

processor when it executes the data write instruction to the
corresponding output device.
The program is written in such a way that the processor will
wait in a loop until the output device is ready to receive data.
As it can be seen clearly, the processor time is wasted in this
polled mode of data transfer as it waits for the device to be
ready.
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In interrupt driven data transfer, the data is read from the
input device only when the input device is ready with data.
When the device is ready, it will give a signal to interrupt the
processor indicating that the data is ready.
In the interrupt service routine, the program is written to
read the data from the corresponding input device.
Similarly, the output device will also give an interrupt to the
processor when it can accept a data.
The programmers have to write an interrupt service routine
for data transfer to the corresponding output device.
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b) Based on the program and hardware involved

i) Programmed data transfer
ii) Direct memory access
Burst mode
Cycle stealing mode
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10
Direct Memory Access (DMA)

In programmed I/O data transfer, processor is actively
involved in the entire data transfer process. The processor is
tied up and processor time is wasted. So, the data transfer
rate is limited.
To overcome these disadvantages of programmed data
transfer and to increase the speed of data transfer, DMA
method of data transfer is used.
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Peripheral or DMA controller asserts one of the request pins

for holding the processor, e.g., HOLD
The processor completes its current instruction and enters
into a HOLD state.
In hold state, the processor temporarily stops the execution
of the instruction and releases the address and data bus by
making them enter into a high impedance state.
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The processor issues a Hold Acknowledge (HLDA) signal as a

token of releasing of bus control to the peripheral or DMA
controller.
DMA operation starts.
Upon completion of the DMA operation, the peripheral or
DMA controller removes the HOLD signal applied to the
processor and relinquishes bus control.
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DMA Controller
A DMA controller can in general interface several peripherals

that may request DMA with the processor.
The controller decides the priority of simultaneous DMA
requests from many peripherals.
It then communicates with the peripheral and the CPU, and
provides memory addresses for data transfer.
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14
DMA controller commonly used with 8085 and 8088

processors is the 8237 programmable DMA controller device.
The 8237 is a 4-channel device. Each channel is dedicated to a
specific peripheral device and capable of addressing 64 K
bytes section of memory.
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c) Based on the way how data is transferred and accessed

i) Parallel data transfer
Simple Data transfer
Handshake mode data transfer
ii) Serial data transfer
Synchronous data transfer
Asynchronous data transfer
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Parallel data transfer

In parallel mode of data transfer, all the bits in a word are
simultaneously transmitted in parallel.
In 8085, a word is made of 8 bits and 8 bits are transmitted
and received in parallel form.
In some special cases, the number of data bits transferred
will be less in number.
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17
The parallel data transfer is used in general for transfer of data

over short distances such as within a system or within a board etc.
The parallel data transfer can be done either
a) By polled mode
b) By interrupt driven mode.
In polled method, the data is read from the input device by the
processor at a time determined by the processor.
This polled mode of data transfer can be done in two ways
a) synchronous or
b) simple I/O and Handshake I/O.
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In simple or synchronous mode, the data is read from the

input device by the processor irrespective of the status of
the input device.
It is assumed that the input device is ready with the data as
and when the processor reads the data and the input device is
in synchronism with the processor.
Similarly, the data is written into the output device
irrespective of its status assuming that the output device is in
synchronism with the processor.
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Drawback of parallel data transfer:

a) The parallel data transfer has the drawback of many wires
needed to transfer all the bits of data.
b) So, the parallel data transfer can not be effectively used for
long distance transfers.
c) As one wire is used for each bit, byte wise data transfers are
eight times more expensive than a single bit transfer.
Serial data transfer is the solution for data transfers over long
distances.
Also, serial communications are low cost way to send data over long
distances.
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Serial data transfer

In serial data transfer, only one bit is transferred over a data
transfer line.
All the bits in a data word can be transmitted by using a shift
register and transferring the data bit by bit.
So, the important parameter in serial data transfer is the
clock frequency at which the bit data are transmitted into the
serial data line.
The frequency at which the data is transmitted serially is
technically as baud rate.
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Baud rate is the measure of the number of bits transmitted

over a second.
The parallel to serial data conversion is done by a device
called Universal Asynchronous Receiver-Transmitter (UART).
The serial data transfer can be done in two modes
a) the synchronous mode and
b) the asynchronous mode.
In synchronized data transfer, the device which sends the
data and the device which receives the data are synchronized
with the common clock.
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In synchronous mode, the data transfer takes place with a

fixed and known time frame.
In asynchronous data transfer, the data words are
transmitted with a random time frame between them.
Most of the microprocessor and computer related data
communications are based upon the asynchronous mode of
transmissions.
The microprocessor uses interrupts and other software
techniques to synchronize random timing between data words
to receive the data completely.
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Interrupt Structure
Interrupt is a mechanism by which the processor (CPU) is
made to transfer control from its current program execution
to another program of more importance or higher priority.
The interrupt signal may be given to the processor by any
external peripheral device.
Interrupts are in general generated by a variety of sources
either internal or external to the CPU.
Interrupts are the primary means by which Input and Output
devices obtain the services of the CPU.
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The key points in the interrupt structure of any microprocessor

The number and type of interrupt signals available
The address of the memory where ISR is located for a particular
interrupt signal. This address is called as Interrupt Vector
address.
The masking and unmasking facility for the interrupt signals.
This facility allows the programmer to execute the interrupt
service routine only when required.
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The priority of interrupts when more than one interrupt

signals are available.
The timing of interrupt signals.
Handling and storing of information about interrupted
program (status information).
This information must be loaded in to CPU when interrupt
service routine is executed and RETURN from interrupt.
The control is transferred back to the interrupted program.
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Types of Interrupts
Vectored and Non-vectored Interrupts
Maskable and Non-maskable Interrupts

Software and Hardware Interrupt
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Interrupt Handling Procedure

The Processor will have to store the information about the current
program when an interrupt signal is recognized before executing the
ISR.
The processor checks for the Interrupt request signals at the end of
every instruction execution.
If the interrupt is masked, then the interrupt will not be recognized
until interrupts are re-enabled.
The sequence of operations that take place when an interrupt signal is
recognized is as followed.
The CPU responds to an interrupt request by a transfer of control to

another program in a manner similar to a subroutine call.
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Save the PC (Program Counter) contents (address of the next

instruction) and supplementary information about current
state (flags, registers, etc.) to the stack.
Load PC with the beginning address of an Interrupt Service
Routine (ISR) and start to execute it
Finish ISR when return instruction is executed
Return to the interrupted program, exactly to the same point
from which it left.
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Transfer of control from Main memory to ISR
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Interrupts and Stack Memory

Stack is a special memory organization that operates on the
principle Last in First Out (LIFO) principle.
The data stored recently will be retrieved first.
Similarly data stored first in the stack can be read last.
Stack is a temporarily storing memory in the RAM area.
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Stack is basically administered by a special register called Stack Pointer

(SP).
SP register always contains the address of the Top of the Stack (ToS).
Storing a data in stack memory pointed by stack pointer is called PUSH
operation.
Reading a data from the stack is called as POP operation.
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The stack can be accessed by the instructions PUSH and POP.

The interrupt service routines should not disturb the return
address stored by the processor into the stack.
So, the interrupt service routines should have equal number of
PUSH and POP instructions.
This condition will ensure that the return address stored in
the stack is retrieved properly by the processor.
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Interrupt Sources and their Vector

Addresses in 8085
Intel 8085 has the facility for both software and hardware
interrupts.
The software interrupts are in the form of instructions and
the hardware interrupts are applied as signals from the
external devices.
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Hardware Interrupts and Priorities

Intel 8085 has 5 hardware interrupts: INTR, RST 5.5, RST
6.6, RST 7.5, and TRAP.
The details of the five interrupts are given in the table 5.5.
Five pins of 8085 are reserved for the five hardware
interrupts.
All the five interrupts are active high signals.
This means that in order to apply an interrupt, logic 1 or high
level signal should be applied at these pins.
The processor checks the voltage on these pins after the
execution of every instruction.
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If the signal level on any of these 5 pins is at logic 1 and the

corresponding interrupt is not masked, then the processor will
suspend the current program and execute the corresponding
interrupt service routine.
RST 7.5 interrupt alone is edge triggered.
That means a logic 0 to 1 transition will be treated as an
interrupt input on this line.
The rising edge interrupt can be applied at any time and this will
set a flip flop inside the processor.
The processor will check this flip flop while checking the signal
level on other hardware interrupts.
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Masking of Interrupts
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The maskable interrupts are by default masked by the RESET

signal. So, any interrupt will not be recognized by the
hardware reset.
The interrupts can be enabled by the execution of the
instruction, EI Enable interrupts. This is a must after reset
to enable the interrupts.
The three RST interrupts can be selectively masked by having
proper word in Accumulator and executing the SIM (Set
Interrupt Mask) instruction. This is called software masking.
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All the maskable interrupts are disabled whenever an

interrupt is recognized.
So, it is necessary to execute EI instruction every time the
interrupts are recognized and serviced by the processor.
All the maskable interrupts can be disabled by executing an
instruction DI Disable Interrupts. This instruction will reset
an interrupt enable flip flop in the processor and the
interrupts will be disabled.
To enable interrupts, EI instruction has to be executed.
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SIM Instruction
The SIM instruction is used to mask or unmask the restart
RST hardware interrupts.
The SIM instruction when executed will read the contents of
the accumulator and based on that will mask or unmask the
interrupts.
So, SIM instruction must be executed after storing having
proper control word in accumulator.
The format of the control word to be stored in accumulator
before executing SIM instruction
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Accumulator bit pattern for SIM instruction
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RIM Instruction
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Timing of Interrupts
The interrupts are sensed by the processor one cycle before
the end of execution of each instruction.
An interrupt signal must be applied for the proper duration so
that it can be recognized. The longest instruction of 8085
takes 18 clock periods.
So, the interrupt signal must be applied for at least 17.5 clock
periods.
This decides the minimum pulse width for the interrupt
signals.
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Any other interrupt issued to the microprocessor will be

recognized once EI instruction is executed.
If, the programmer has written the EI instruction at the
start of the interrupt service routine, then the
microprocessor can be interrupted once again before the
completion of the interrupt service routine.
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Interfacing of INTR interrupt to 8085
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Data Transfer Mechanisim

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HARDWARE INTERFACING WITH INTEL 8085

Methods of Data Transfer and Interrupt Structure in 8085

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

The data transfer mechanism differs from each other based

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

b) Based on the program and hardware involved

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

c) Based on the way how data is transferred and accessed

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

Programmed data transfer

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

The execution of programmed data transfer can take place at

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

Polled mode of data transfer

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

Similarly, the data is written into an output device by the

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

Interrupt driven data transfer

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

b) Based on the program and hardware involved

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

Direct Memory Access (DMA)

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

Peripheral or DMA controller asserts one of the request pins

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

The processor issues a Hold Acknowledge (HLDA) signal as a

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

A DMA controller can in general interface several peripherals

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

DMA controller commonly used with 8085 and 8088

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

c) Based on the way how data is transferred and accessed

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

Parallel data transfer

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

The parallel data transfer is used in general for transfer of data

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

In simple or synchronous mode, the data is read from the

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

Drawback of parallel data transfer:

BIT MESRA RANCHI, JHARKHAND, INDIA

DR. MANOJ KUMAR MUKUL

Serial data transfer

BIT MESRA RANCHI, JHARKHAND, INDIA