Juntos Todos

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT151
8-input multiplexer
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
8-input multiplexer
74HC/HCT151
FEATURES
True and complement outputs
Multifunction capability
Permits multiplexing from n lines to 1 line
Non-inverting data path
See the 251 for the 3-state version
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT151 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC = 5 V
In to Y, Y
17
19
ns
Sn to Y, Y
19
20
ns
E to Y
12
13
ns
E to Y
14
18
ns
3.5
3.5
pF
40
40
pF
CI
input capacitance
CPD
power dissipation capacitance per package
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL VCC2 fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See 74HC/HCT/HCU/HCMOS Logic Package Information.
December 1990
HCT
8-input multiplexer
74HC/HCT151
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
4, 3, 2, 1, 15, 14, 13, 12
I0 to I7
multiplexer inputs
multiplexer output
complementary multiplexer output
enable input (active LOW)
GND
ground (0 V)
11, 10, 9
S0, S1, S2
select inputs
16
VCC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
8-input multiplexer
74HC/HCT151
FUNCTION TABLE
INPUTS
OUTPUTS
S2
S1
S0
I0
I1
I2
I3
I4
I5
I6
I7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
X
X
X
X
X
X
H
L
H
L
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
H
L
H
L
L
H
L
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = dont care.
Fig.4 Functional diagram.
December 1990
Fig.5 Logic diagram.
8-input multiplexer
74HC/HCT151
DC CHARACTERISTICS FOR 74HC

For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications.
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
+25
min. typ.
40 to +85
max.
min. max.
40 to +125
min.
UNIT
VCC WAVEFORMS
(V)
max.
tPHL/ tPLH
propagation delay
In to Y
52
19
15
170
34
29
215
43
37
255
51
43
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
In to Y
58
21
17
185
37
31
230
46
39
280
56
48
ns
2.0
4.5
6.0
Fig.6
tPHL/ tPLH
propagation delay
Sn to Y
61
22
18
185
37
31
230
46
39
280
56
48
ns
2.0
4.5
6.0
Fig.7
tPHL/ tPLH
propagation delay
Sn to Y
61
22
18
205
41
35
255
51
43
310
62
53
ns
2.0
4.5
6.0
Fig.7
tPHL/ tPLH
propagation delay
E to Y
41
15
12
125
25
21
155
31
26
190
38
32
ns
2.0
4.5
6.0
Fig.7
tPHL/ tPLH
propagation delay
E to Y
47
17
14
145
29
25
180
36
31
220
44
38
ns
2.0
4.5
6.0
Fig.7
tTHL/ tTLH
output transition time
19
7
6
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
Figs 6 and 7
December 1990
8-input multiplexer
74HC/HCT151
DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications.
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications.
To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
In
Sn
E
0.45
1.50
0.30
AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
+25
min.
tPHL/ tPLH
typ.
40 to +85
max. min.
max.
40 to +125
min.
UNIT
VCC
(V)
WAVEFORMS
max.
propagation delay
In to Y
22
38
48
57
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
In to Y
22
38
48
57
ns
4.5
Fig.6
tPHL/ tPLH
propagation delay
Sn to Y
23
41
51
62
ns
4.5
Fig.7
tPHL/ tPLH
propagation delay
Sn to Y
25
43
54
65
ns
4.5
Fig.7
tPHL/ tPLH
propagation delay
E to Y
16
29
36
44
ns
4.5
Fig.7
tPHL/ tPLH
propagation delay
E to Y
21
36
45
54
ns
4.5
Fig.7
tTHL/ tTLH
output transition time
15
19
22
ns
4.5
December 1990
Figs 6 and 7
8-input multiplexer
74HC/HCT151
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.6
Waveforms showing the multiplexer input (In) to outputs (Y and Y) propagation delays and the output
transition times.
(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the select input (Sn) and enable input (E) to outputs (Y and Y) propagation delays
and the output transition times.
PACKAGE OUTLINES
See 74HC/HCT/HCU/HCMOS Logic Package Outlines.
December 1990
Revised March 2000
DM74LS04
Hex Inverting Gates
General Description
This device contains six independent gates each of which
performs the logic INVERT function.
Ordering Code:
Order Number
Package Number
Package Description
DM74LS04M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS04SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS04N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagram
Function Table
Y=A
Input
Output
H = HIGH Logic Level

L = LOW Logic Level
2000 Fairchild Semiconductor Corporation
DS006345
www.fairchildsemi.com
DM74LS04 Hex Inverting Gates
August 1986
DM74LS04
Absolute Maximum Ratings(Note 1)

Supply Voltage
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define the conditions
for actual device operation.
7V
Input Voltage
7V
0C to +70C
Operating Free Air Temperature Range
65C to +150C
Storage Temperature Range
Recommended Operating Conditions

Symbol
Parameter
Min
Nom
Max
Units
4.75
5.25
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
0.8
IOH
HIGH Level Output Current
0.4
mA
IOL
LOW Level Output Current
mA
TA
Free Air Operating Temperature
70
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC = Min, II = 18 mA
VOH
HIGH Level
VCC = Min, IOH = Max,
Output Voltage
VIL = Max
VOL
LOW Level
VCC = Min, IOL = Max,
Output Voltage
VIH = Min
Typ
Min
(Note 2)
2.7
1.5
V
V
0.35
0.5
0.25
0.4
VCC = Max, VI = 7V
Input Current @ Max
Units
3.4
IOL = 4 mA, VCC = Min

II
Max
0.1
V
mA
Input Voltage
IIH
HIGH Level Input Current
VCC = Max, VI = 2.7V
20
IIL
LOW Level Input Current
0.36
mA
IOS
Short Circuit Output Current
VCC = Max (Note 3)
100
mA
ICCH
Supply Current with Outputs HIGH
VCC = Max
1.2
2.4
mA
ICCL
Supply Current with Outputs LOW
VCC = Max
3.6
6.6
mA
20
Note 2: All typicals are at VCC = 5V, TA = 25C.

Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
at VCC = 5V and TA = 25C
RL = 2 k
Symbol
tPLH
Propagation Delay Time

LOW-to-HIGH Level Output
tPHL
CL = 15 pF
Parameter

HIGH-to-LOW Level Output
CL = 50 pF
Units
Min
Max
Min
Max
10
15
ns
10
15
ns
DM74LS04
Physical Dimensions inches (millimeters) unless otherwise noted
Package Number M14A
DM74LS04
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Package Number M14D
DM74LS04 Hex Inverting Gates

Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
Revised March 2000
DM74LS10
Triple 3-Input NAND Gate
General Description
This device contains three independent gates each of
which performs the logic NAND function.
Ordering Code:
Order Number
Package Number
Package Description
DM74LS10M
M14A
DM74LS10N
N14A
Connection Diagram
Function Table
Y = ABC
Inputs
Output

L = LOW Logic Level
X = Either LOW or HIGH Logic Level
DS006349
DM74LS10 Triple 3-Input NAND Gate
August 1986
DM74LS10

Supply Voltage
7V
Input Voltage
7V
0C to +70C
65C to +150C

Symbol
Parameter
Min
Nom
Max
Units
4.75
5.25
0.8
VCC
Supply Voltage
VIH
VIL
IOH
0.4
mA
IOL
mA
TA
70
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VOH
HIGH Level
Output Voltage
VIL = Max
VOL
LOW Level
Output Voltage
VIH = Min
Min
Typ
(Note 2)
2.7
Max
Units
1.5
3.4
0.35
0.5
0.25
0.4
II
Input Current @ Max Input Voltage
VCC = Max, VI = 7V
0.1
IIH
20
IIL
0.36
mA
IOS
VCC = Max (Note 3)
100
mA
ICCH
Supply Current with Outputs High
VCC = Max
0.6
1.2
mA
ICCL
Supply Current with Outputs Low
VCC = Max
1.8
3.3
mA
20
mA

RL = 2 k
Symbol
tPLH
CL = 15 pF
Parameter
tPHL

CL = 50 pF
Units
Min
Max
Min
Max
10
15
ns
10
15
ns
DM74LS10
Package Number M14A
DM74LS10 Triple 3-Input NAND Gate

Package Number N14A
LIFE SUPPORT POLICY

user.
DM74LS48
BCD to 7-Segment Decoder
General Description
The LS48 translates four lines of BCD (8421) input data
into the 7-segment numeral code and provides seven corresponding outputs having pull-up resistors, as opposed to
totem pole pull-ups. These outputs can serve as logic signals, with a HIGH output corresponding to a lighted lamp
segment, or can provide a 1.3 mA base current to npn lamp
driver transistors. Auxiliary inputs provide lamp test, blanking and cascadable zero-suppression functions.
The LS48 decodes the input data in the pattern indicated in
the Truth Table and the segment identification illustration.
Connection Diagram
Dual-In-Line Package
TL/F/10172 1
Order Number DM74LS48M or DM74LS48N

See NS Package Number M16A or N16E
C1995 National Semiconductor Corporation
TL/F/10172
RRD-B30M105/Printed in U. S. A.
DM74LS48 BCD to 7-Segment Decoder
January 1992
Absolute Maximum Ratings (Note)

Supply Voltage
7V
Input Voltage
7V

DM74LS
Note: The Absolute Maximum Ratings are those values

beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the Electrical Characteristics
table are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define
the conditions for actual device operation .
0 C to a 70 C
b 65 C to a 150 C

Symbol
DM74LS48
Parameter
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
Units
Min
Nom
Max
4.75
5.25
V
0.8
High Level Output Current
b 50
mA
IOL
Low Level Output Current
6.0
mA
TA
70
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
b 1.5
VI
Input Clamp Voltage
VCC e Min, II e b18 mA
VOH
High Level Output

Voltage
VCC Min, IOH e Max,

VIL e Max
IOFF
Output High Current

Segment Outputs
VCC e Min, VO e 0.85V
VOL
Low Level Output

Voltage
VCC e Min, IOL e Max,

VIH e Min
0.5
IOL e 2.0 mA, VCC e Min
0.4
VCC e Max, VI e 7V
0.1
2.4
b 1.3
mA
II
Input Current @ Max

Input Voltage
IIH
High Level Input Current
VCC e Max, VI e 2.7V
20
mA
IIL
Low Level Input Current
VCC e Max, VI e 0.4V
b 0.4
mA
IOS
Short Circuit
Output Current
VCC e Max, VO e 0V
at BI/RBO (Note 2)
b2
mA
ICCH
Supply Current
VCC e Max, VIN e 4.5V
38
mA
b 0.3
mA
Note 1: All typicals are at VCC e 5V, TA e 25 C.

Switching Characteristics at VCC e 5V and TA e 25 C

Symbol
CL e 15 pF
Parameter
Min
Units
Max
tPLH
tPHL

An to ag
100
100
ns
tPLH
tPHL

RBI to af
100
100
ns
Note: LT e HIGH, A0 A3 e HIGH.
Numerical DesignationsResultant Displays
TL/F/10172 4
Truth Table
Decimal
Or
Function
Inputs
Outputs
LT
RBI
A3
A2
A1
A0
BI/RBO
0 (Note 1)
1 (Note 1)
2
3
H
H
H
H
H
X
X
X
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
L
L
H
H
4
5
6
7
8
H
H
H
H
H
X
X
X
X
X
L
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
L
H
L
H
H
H
L
L
H
H
H
H
H
H
H
L
H
H
L
H
L
L
H
L
H
H
H
H
L
H
H
H
H
L
H
9
10
11
12
13
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
L
L
L
H
H
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
L
L
L
H
H
L
H
L
H
L
L
L
H
L
L
H
H
H
H
H
H
H
14
15
BI (Note 2)
RBI (Note 3)
LT (Note 4)
H
H
X
H
L
X
X
X
L
X
H
H
X
L
X
H
H
X
L
X
H
H
X
L
X
L
H
X
L
X
H
H
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
H
L
L
L
H
H
L
L
L
H
H
L
L
L
H
H
L
L
L
H
Note 1: BI/RBO is wired-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held at a HIGH level
when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking of a decimal 0 is not desired. X e input
may be HIGH or LOW.
Note 2: When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level, regardless of the state of any other input
condition.
Note 3: When ripple-blanking input (RBI) and inputs A0, A1, A2, and A3 are at LOW level, with the lamp test input at HIGH level, all segment outputs go to a LOW
level and the ripple-blanking output (RBO) goes to a LOW level (response condition).
Note 4: When the blanking input/ripple-blanking output (BI/RBO) is open or held at a HIGH level, and a LOW level is applied to lamp test input, all segment outputs
go to a HIGH level.
Logic Symbol
TL/F/10172 2
VCC e Pin 16
GND e Pin 8
Logic Diagram
TL/F/10172 3
Physical Dimensions inches (millimeters)
16-Lead Small Outline Molded Package (M)

Order Number DM74LS48M
NS Package Number M16A
DM74LS48 BCD to 7-Segment Decoder
Physical Dimensions inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS48N
NS Package Number N16E
LIFE SUPPORT POLICY

NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
2. A critical component is any component of a life

support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
SN54/74LS90
SN54/74LS92
SN54/74LS93
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
Low Power Consumption . . . Typically 45 mW

High Count Rates . . . Typically 42 MHz
Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
14
Binary
Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING (Note a)
HIGH
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
J SUFFIX
CERAMIC
CASE 632-08
Clock (Active LOW going edge) Input to

2 Section
5 Section (LS90), 6 Section (LS92)
8 Section (LS93)
Master Reset (Clear) Inputs
Master Set (Preset-9, LS90) Inputs
Output from 2 Section (Notes b & c)
Outputs from 5 (LS90), 6 (LS92),
8 (LS93) Sections (Note b)
N SUFFIX
PLASTIC
CASE 646-06
LOW
0.5 U.L.
1.5 U.L.
0.5 U.L.
2.0 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
14
1
D SUFFIX
SOIC
CASE 751A-02
14
1
ORDERING INFORMATION
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b. Temperature Ranges.
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
LS90
LS92
LS93
6 7
1 2
14
1
MS
CP0
CP1
MR Q0 Q1 Q2 Q3
14
1
CP0
CP1
MR Q0 Q1 Q2 Q3
14
1
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
1 2
1 2
2 3 12 9 8 11
6 7 12 11 9 8
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PINS 2, 3, 4, 13
VCC = PIN 5
GND = PIN 10
NC = PIN 4, 6, 7, 13
VCC = PIN 5
GND = PIN 10
NC = PINS 4, 13
FAST AND LS TTL DATA

5-90
SN54/74LS90 SN54/74LS92 SN54/74LS93

LOGIC DIAGRAM
CONNECTION DIAGRAM
DIP (TOP VIEW)
LS90
MS1
MS2
6
7
14
CP0
S
J DQ
S
J DQ
S
J DQ
S
R DQ
CP
KC Q
D
CP
CP
CP
KC Q
D
KC Q
D
SC Q
D
CP1
MR1
MR2
2
12
Q0
Q1
11
Q2
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
LOGIC DIAGRAM
CP0
14
CP
KC Q
D
CP
KC Q
D
CP
KC Q
D
CP
KC Q
D
CP1
6
MR1
MR2
12
11
Q0
14 CP0
MR1 2
13 NC
MR2 3
12 Q0
NC 4
11 Q3
VCC 5
10 GND
MS1 6
9 Q1
MS2 7
8 Q2
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM
DIP (TOP VIEW)
LS92
CP1 1
Q1
Q2
CP1 1
14 CP0
NC 2
13 NC
NC 3
12 Q0
NC 4
11 Q1
VCC 5
10 GND
MR1 6
9 Q2
MR2 7
8 Q3
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
LOGIC DIAGRAM
CONNECTION DIAGRAM
DIP (TOP VIEW)
LS93
CP0
14
CP
CP
CP
CP
KC Q
D
KC Q
D
KC Q
D
KC Q
D
CP1
MR1
MR2
2
12
3
Q0
Q1
NOTE:
Q2
14 CP0
MR1 2
13 NC
MR2 3
12 Q0
NC 4
11 Q3
VCC 5
10 GND
NC 6
9 Q1
NC 7
8 Q2
11
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10

5-91
CP1 1
NOTE:
SN54/74LS90 SN54/74LS92 SN54/74LS93

FUNCTIONAL DESCRIPTION
C. Divide-By-Two and Divide-By-Five Counter No external
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function (CP 0 as the
input and Q0 as the output). The CP1 input is used to obtain
binary divide-by-five operation at the Q3 output.
The LS90, LS92, and LS93 are 4-bit ripple type Decade,
Divide-By-Twelve, and Binary Counters respectively. Each
device consists of four master/slave flip-flops which are
internally connected to provide a divide-by-two section and a
divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight
(LS93) section. Each section has a separate clock input which
initiates state changes of the counter on the HIGH-to-LOW
clock transition. State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes. The Q0 output of
each device is designed and specified to drive the rated
fan-out plus the CP1 input of the device.
A gated AND asynchronous Master Reset (MR1 MR2) is
provided on all counters which overrides and clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1 MS2) is provided on the LS90 which
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes.
LS92
A. Modulo 12, Divide-By-Twelve Counter The CP1 input
must be externally connected to the Q0 output. The CP0 input receives the incoming count and Q3 produces a symmetrical divide-by-twelve square wave output.
B. Divide-By-Two and Divide-By-Six Counter No external
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function. The CP1 input is used to obtain divide-by-three operation at the Q1
and Q2 outputs and divide-by-six operation at the Q3 output.
LS93
A. 4-Bit Ripple Counter The output Q0 must be externally
connected to input CP1. The input count pulses are applied
to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are
performed at the Q0, Q1, Q2, and Q3 outputs as shown in
the truth table.
LS90
A. BCD Decade (8421) Counter The CP1 input must be externally connected to the Q0 output. The CP0 input receives
the incoming count and a BCD count sequence is produced.
B. 3-Bit Ripple Counter The input count pulses are applied

to input CP1. Simultaneous frequency divisions of 2, 4, and
8 are available at the Q1, Q2, and Q3 outputs. Independent
use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.
B. Symmetrical Bi-quinary Divide-By-Ten Counter The Q3

output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a divide-byten square wave is obtained at output Q0.

5-92
SN54/74LS90 SN54/74LS92 SN54/74LS93

LS90
MODE SELECTION
RESET / SET INPUTS
MR1 MR2 MS1 MS2
H
H
X
L
X
L
X
H
H
X
X
L
X
L
L
X
H
L
X
X
L
X
L
H
X
L
L
X
LS92 AND LS93

MODE SELECTION
OUTPUTS
Q0
L
L
H
Q1
Q2
L
L
L
L
L
L
Count
Count
Count
Count
RESET
INPUTS
Q3
MR1 MR2
L
L
H
H
L
H
L
0
1
2
3
4
5
6
7
8
9
Q1
LS92
TRUTH TABLE
OUTPUT
COUNT
H
H
L
L
Q0
Q2
L
L
Count
Count
Count
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
NOTE: Output Q0 is connected to Input

CP1 for BCD count.
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
LS93
TRUTH TABLE
OUTPUT
Q0
Q3
H = HIGH Voltage Level

L = LOW Voltage Level
X = Dont Care
H = HIGH Voltage Level

L = LOW Voltage Level
X = Dont Care
LS90
BCD COUNT SEQUENCE
OUTPUTS
OUTPUT
Q0
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
L
L
H
H
H
H
H
H

CP1.
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q0
Q1
Q2
Q3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

CP1.

5-93
SN54/74LS90 SN54/74LS92 SN54/74LS93

GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
IOH
Output Current High
54, 74
0.4
mA
IOL
Output Current Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
Symbol
Min
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current

MS, MR
CP0
CP1 (LS90, LS92)
CP1 (LS93)
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
Typ
Max
2.0
54
0.7
74
0.8
0.65
1.5
Unit
Test Conditions
Guaranteed Input HIGH Voltage for

All Inputs
Guaranteed Input LOW Voltage for

All Inputs
VCC = MIN, IIN = 18 mA
54
2.5
3.5
74
2.7
3.5
VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
IOL = 4.0 mA
74
0.35
0.5
IOL = 8.0 mA
20
VCC = MAX, VIN = 2.7 V
0.1
mA
mA
100
mA
VCC = MAX
15
mA
VCC = MAX
0.4
2.4
3.2
1.6
20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

5-94
SN54/74LS90 SN54/74LS92 SN54/74LS93

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V, CL = 15 pF)
Limits
LS92
LS90
Symbol
Typ
Min
Parameter
Max
Min
Typ
LS93
Max
32
Min
Typ
Max
32
Unit
fMAX
CP0 Input Clock Frequency
32
fMAX
CP1 Input Clock Frequency
16
tPLH
tPHL
Propagation Delay,
CP0 Input to Q0 Output
10
12
16
18
10
12
16
18
10
12
16
18
ns
tPLH
tPHL
32
34
48
50
32
34
48
50
46
46
70
70
ns
tPLH
tPHL
10
14
16
21
10
14
16
21
10
14
16
21
ns
tPLH
tPHL
21
23
32
35
10
14
16
21
21
23
32
35
ns
tPLH
tPHL
21
23
32
35
21
23
32
35
34
34
51
51
ns
tPLH
MS Input to Q0 and Q3 Outputs
20
30
ns
tPHL
MS Input to Q1 and Q2 Outputs
26
40
ns
tPHL
MR Input to Any Output
26
40
16
MHz
16
26
40
MHz
26
40
ns
AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)

Limits
LS90
Symbol
Min
Parameter
LS92
Max
Min
LS93
Max
Min
Max
Unit
tW
CP0 Pulse Width
15
15
15
ns
tW
CP1 Pulse Width
30
30
30
ns
tW
MS Pulse Width
15
tW
MR Pulse Width
15
15
15
ns
trec
Recovery Time MR to CP
25
25
25
ns
ns
RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize
and transfer HIGH data to the Q outputs
AC WAVEFORMS
*CP
1.3 V
1.3 V
tPHL
Q
1.3 V
tW
tPLH
1.3 V
1.3 V
Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
MR & MS
1.3 V
1.3 V
MS
trec
tW
1.3 V
tW
trec
CP
1.3 V
CP
tPHL
Q
1.3 V
Q0 Q3
(LS90)
1.3 V
Figure 2
1.3 V
tPLH
1.3 V
Figure 3

5-95
Revised March 2000
DM74LS138 DM74LS139
Decoder/Demultiplexer
General Description
Features
These Schottky-clamped circuits are designed to be used

in high-performance memory-decoding or data-routing
applications, requiring very short propagation delay times.
In high-performance memory systems these decoders can
be used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of
the memory. This means that the effective system delay
introduced by the decoder is negligible.
Designed specifically for high speed:
The DM74LS138 decodes one-of-eight lines, based upon

the conditions at the three binary select inputs and the
three enable inputs. Two active-low and one active-high
enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder
requires only one inverter. An enable input can be used as
a data input for demultiplexing applications.
Typical propagation delay (3 levels of logic)
Memory decoders
Data transmission systems
DM74LS138 3-to-8-line decoders incorporates 3 enable
inputs to simplify cascading and/or data reception
DM74LS139 contains two fully independent 2-to-4-line
decoders/demultiplexers
Schottky clamped for high performance
DM74LS138
21 ns
DM74LS139
21 ns
Typical power dissipation

DM74LS138
32 mW
DM74LS139
34 mW
The DM74LS139 comprises two separate two-line-to-fourline decoders in a single package. The active-low enable
input can be used as a data line in demultiplexing applications.
All of these decoders/demultiplexers feature fully buffered
inputs, presenting only one normalized load to its driving
circuit. All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify system design.
Ordering Code:
Order Number
Package Number
Package Description
DM74LS138M
M16A
DM74LS138SJ
M16D
DM74LS138N
N16E
DM74LS139M
M16A
DM74LS139SJ
M16D
DM74LS139N
N16E
DS006391
DM74LS138 DM74LS139 Decoder/Demultiplexer
August 1986
DM74LS138 DM74LS139
Connection Diagrams
DM74LS138
DM74LS139
Function Tables
DM74LS138
DM74LS139
Inputs
Enable
Inputs
Outputs
Select
Enable
G1 G2 (Note 1) C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
Outputs
Select
Y0
Y1
Y2
Y3
X X X
X X X
L L L
L L H
L H L
L H H
H L L
H L H
H H L
H H H
H = HIGH Level
L = LOW Level
X = Dont Care
Note 1: G2 = G2A + G2B
Logic Diagrams
DM74LS138
DM74LS139
Supply Voltage
7V
Input Voltage
7V
0C to +70C
65C to +150C
DM74LS138 Recommended Operating Conditions

Symbol
Parameter
Min
Nom
Max
4.75
5.25
Units
VCC
Supply Voltage
VIH
VIL
0.8
IOH
0.4
mA
IOL
mA
TA
70
DM74LS138 Electrical Characteristics

Symbol
Parameter
Conditions
Min
VI
Input Clamp Voltage
VOH
HIGH Level Output Voltage
VCC = Min, IOH = Max, VIL = Max, VIH = Min
Typ
(Note 3)
Max
1.5
2.7
3.4
Units
V
V
LOW Level
VCC = Min, IOL = Max, VIL = Max, VIH = Min
0.35
0.5
Output Voltage
0.25
0.4
II
VCC = Max, VI = 7V
0.1
IIH
20
IIL
0.36
mA
IOS
VCC = Max (Note 4)
ICC
Supply Current
VCC = Max (Note 5)
VOL
20
V
mA
100
mA
10
mA
6.3

Note 5: ICC is measured with all outputs enabled and OPEN.
DM74LS138 Switching Characteristics

Symbol
Parameter
From (Input)
Levels
To (Output)
of Delay
RL = 2 k
CL = 15 pF
Min
tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

Max
CL = 50 pF
Min
Units
Max
Select to Output
18
27
ns
Select to Output
27
40
ns
Select to Output
18
27
ns
Select to Output
27
40
ns
Enable to Output
18
27
ns
Enable to Output
24
40
ns
Enable to Output
18
27
ns
Enable to Output
28
40
ns
DM74LS138 DM74LS139
DM74LS138 DM74LS139
DM74LS139 Recommended Operating Conditions

Symbol
Parameter
Min
Nom
Max
4.75
5.25
Units
VCC
Supply Voltage
VIH
VIL
0.8
IOH
0.4
mA
IOL
mA
TA
70
DM74LS139 Electrical Characteristics

Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VOH
HIGH Level
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
Output Voltage
VIL = Max, VIH = Min
Min
2.7
Typ
(Note 6)
Max
Units
1.5
3.4
0.35
0.5
0.25
0.4
II
VCC = Max, VI = 7V
0.1
IIH
20
IIL
0.36
mA
IOS
VCC = Max (Note 7)
ICC
Supply Current
VCC = Max (Note 8)
20
6.8
mA
100
mA
11
mA

Note 8: ICC is measured with all outputs enabled and OPEN.
DM74LS139 Switching Characteristics

RL = 2 k
From (Input)
Symbol
Parameter
CL = 15 pF
To (Output)
Min
tPLH

tPHL

tPLH

tPHL

Max
CL = 50 pF
Min
Units
Max
Select to Output
18
27
ns
Select to Output
27
40
ns
Enable to Output
18
27
ns
Enable to Output
24
40
ns
DM74LS138 DM74LS139
Package Number M16A
DM74LS138 DM74LS139
Package Number M16D
DM74LS138 DM74LS139 Decoder/Demultiplexer

Package Number N16E
LIFE SUPPORT POLICY

user.
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL
APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMERS RISK.
In order to minimize risks associated with the customers applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TIs publication of information regarding any third
partys products or services does not constitute TIs approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Revised March 2000
DM74LS00
Quad 2-Input NAND Gate
General Description
This device contains four independent gates each of which
performs the logic NAND function.
Ordering Code:
Order Number
Package Number
Package Description
DM74LS00M
M14A
DM74LS00SJ
M14D
DM74LS00N
N14A
Connection Diagram
Function Table
Y = AB
Inputs
Output

L = LOW Logic Level
DS006439
DM74LS00 Quad 2-Input NAND Gate
August 1986
DM74LS00

Supply Voltage
7V
Input Voltage
7V
0C to +70C
65C to +150C

Symbol
Parameter
Min
Nom
Max
4.75
5.25
Units
VCC
Supply Voltage
VIH
VIL
0.8
IOH
0.4
mA
IOL
mA
TA
70
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VOH
HIGH Level
Output Voltage
VIL = Max
VOL
LOW Level
Output Voltage
VIH = Min
Min
Typ
(Note 2)
2.7
Max
Units
1.5
3.4
0.35
0.5
0.25
0.4
II
VCC = Max, VI = 7V
0.1
IIH
20
IIL
0.36
mA
IOS
VCC = Max (Note 3)
100
mA
ICCH
Supply Current with Outputs HIGH
VCC = Max
0.8
1.6
mA
ICCL
Supply Current with Outputs LOW
VCC = Max
2.4
4.4
mA
20
mA

RL = 2 k
Symbol
tPLH
CL = 15 pF
Parameter
tPHL

CL = 50 pF
Units
Min
Max
Min
Max
10
15
ns
10
15
ns
DM74LS00
Package Number M14A
DM74LS00
Package Number M14D
DM74LS00 Quad 2-Input NAND Gate

Package Number N14A
LIFE SUPPORT POLICY

user.
This datasheet has been downloaded from:

www.DatasheetCatalog.com
Datasheets for electronic components.
TIGER ELECTRONIC CO.,LTD

TO-92
2N2222A
Plastic-Encapsulate Transistors
TO-92
TRANSISTOR (NPN )
1. EMITTER
FEATURE
Complementary NPN Type available (MPS2222)
2. BASE
3. COLLECTOR
MAXIMUM RATINGS (TA=25 unless otherwise noted)

Symbol
Parameter
Value
Units
VCBO
Collector-Base Voltage
75
VCEO
Collector-Emitter Voltage
40
VEBO
Emitter-Base Voltage
IC
Collector Current -Continuous
600
mA
PC
Collector Power Dissipation
625
mW
TJ
Junction Temperature
150
Tstg
Storage Temperature
-55-150
1 2 3
ELECTRICAL CHARACTERISTICS (Tamb=25 unless otherwise specified)

Parameter
Symbol
Test
MIN
MAX
UNIT
Collector-base breakdown voltage
V(BR)CBO
IC= 10uA , IE=0
75
Collector-emitter breakdown voltage
V(BR)CEO
IC= 10mA ,
40
Emitter-base breakdown voltage
V(BR)EBO
IE= 10uA, IC=0
Collector cut-off current
ICBO
VCB= 60V, IE=0
10
nA
Collector cut-off current
ICEX
VCE= 60V,VEB(Off)=3V
10
nA
Emitter cut-off current
IEBO
VEB= 3 V, IC=0
100
nA
hFE(1)
VCE=10V,IC= 150mA
100
hFE(2)
VCE=10V,IC= 0.1mA
40
VCE=10V, IC= 500mA
42
DC current gain
*
hFE(3)
Collector-emitter saturation voltage

Base-emitter saturation voltage
conditions
IB=0
300
VCE(sat)(1)
IC= 500mA, IB=50mA
0.6
VCE(sat)(2)
IC= 150mA, IB=15mA
0.3
IC= 500mA, IB= 50mA
1.2
VBE(sat)
Delay time
td
VCC=30V, VEB(Off)=-0.5V,
10
nS
Rise time
tr
IC=150mA,IB1=15mA
25
nS
Storage time
tS
225
nS
Fall time
tf
60
nS
Transition frequency
fT
VCC=30V,Ic=150mA,IB1=IB2=15mA
VCE=20V, IC=20mA, f=100MHz
300
pulse test
CLASSIFICATION OF hFE(1)
Rank
Range
100-200
200-300
MHz
Typical Characteristics
MPS2222A
SN5476, SN54LS76A
SN7476, SN74LS76A
DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR
SDLS121 DECEMBER 1983 REVISED MARCH 1988
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN5476, SN54LS76A
SN7476, SN74LS76A
DALLAS, TEXAS 75265
SN5476, SN54LS76A
SN7476, SN74LS76A
DALLAS, TEXAS 75265
SN5476, SN54LS76A
SN7476, SN74LS76A
DALLAS, TEXAS 75265
SN5476, SN54LS76A
SN7476, SN74LS76A
DALLAS, TEXAS 75265
SN5476, SN54LS76A
SN7476, SN74LS76A
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
5962-9557501QEA
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9557501QE
A
SNJ5476J
5962-9557501QFA
ACTIVE
CFP
16
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9557501QF
A
SNJ5476W
5962-9557501QFA
ACTIVE
CFP
16
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9557501QF
A
SNJ5476W
7601301EA
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
7601301EA
SNJ54LS76AJ
7601301EA
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
7601301EA
SNJ54LS76AJ
JM38510/00204BEA
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
00204BEA
JM38510/00204BEA
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
00204BEA
M38510/00204BEA
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
00204BEA
M38510/00204BEA
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
00204BEA
SN5476J
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
SN5476J
SN5476J
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
SN5476J
SN54LS76AJ
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
SN54LS76AJ
SN54LS76AJ
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
SN54LS76AJ
SN7476N
OBSOLETE
PDIP
16
TBD
Call TI
Call TI
0 to 70
SN7476N
OBSOLETE
PDIP
16
TBD
Call TI
Call TI
0 to 70
SN7476N3
OBSOLETE
PDIP
16
TBD
Call TI
Call TI
0 to 70
SN7476N3
OBSOLETE
PDIP
16
TBD
Call TI
Call TI
0 to 70
SN74LS76AD
OBSOLETE
SOIC
16
TBD
Call TI
Call TI
0 to 70
SN74LS76AD
OBSOLETE
SOIC
16
TBD
Call TI
Call TI
0 to 70
Addendum-Page 1
Samples
www.ti.com
25-Oct-2016
Orderable Device
Status
(1)
Package Type Package Pins Package

Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
SN74LS76ADR
OBSOLETE
SOIC
16
TBD
Call TI
Call TI
0 to 70
SN74LS76ADR
OBSOLETE
SOIC
16
TBD
Call TI
Call TI
0 to 70
SN74LS76AN
OBSOLETE
PDIP
16
TBD
Call TI
Call TI
0 to 70
SN74LS76AN
OBSOLETE
PDIP
16
TBD
Call TI
Call TI
0 to 70
SN74LS76AN3
OBSOLETE
PDIP
16
TBD
Call TI
Call TI
0 to 70
SN74LS76AN3
OBSOLETE
PDIP
16
TBD
Call TI
Call TI
0 to 70
SNJ5476J
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9557501QE
A
SNJ5476J
SNJ5476J
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9557501QE
A
SNJ5476J
SNJ5476W
ACTIVE
CFP
16
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9557501QF
A
SNJ5476W
SNJ5476W
ACTIVE
CFP
16
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9557501QF
A
SNJ5476W
SNJ54LS76AJ
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
7601301EA
SNJ54LS76AJ
SNJ54LS76AJ
ACTIVE
CDIP
16
TBD
A42
N / A for Pkg Type
-55 to 125
7601301EA
SNJ54LS76AJ
(1)
The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 2
Samples
www.ti.com
25-Oct-2016
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5476, SN54LS76A, SN7476, SN74LS76A :
Catalog: SN7476, SN74LS76A

Military: SN5476, SN54LS76A
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

Military - QML certified for Military and Defense Applications
Addendum-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Juntos Todos

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Juntos Todos

Uploaded by

Copyright:

Available Formats

INTEGRATED CIRCUITS

power dissipation capacitance per package

NAME AND FUNCTION

4, 3, 2, 1, 15, 14, 13, 12

complementary multiplexer output

enable input (active LOW)

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

Fig.4 Functional diagram.

Fig.5 Logic diagram.

DC CHARACTERISTICS FOR 74HC

output transition time

DC CHARACTERISTICS FOR 74HCT

UNIT LOAD COEFFICIENT

AC CHARACTERISTICS FOR 74HCT

output transition time

(1) HC : VM = 50%; VI = GND to VCC.

(1) HC : VM = 50%; VI = GND to VCC.

Revised March 2000

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

H = HIGH Logic Level

2000 Fairchild Semiconductor Corporation

DM74LS04 Hex Inverting Gates

Absolute Maximum Ratings(Note 1)

Operating Free Air Temperature Range

Storage Temperature Range

Recommended Operating Conditions

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current

Free Air Operating Temperature

Input Clamp Voltage

VCC = Min, IOH = Max,

VCC = Min, IOL = Max,

Input Current @ Max

IOL = 4 mA, VCC = Min

HIGH Level Input Current

VCC = Max, VI = 2.7V

LOW Level Input Current

VCC = Max, VI = 0.4V

Short Circuit Output Current

VCC = Max (Note 3)

Supply Current with Outputs HIGH

Supply Current with Outputs LOW

Note 2: All typicals are at VCC = 5V, TA = 25C.

Propagation Delay Time

Propagation Delay Time

Physical Dimensions inches (millimeters) unless otherwise noted

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

DM74LS04 Hex Inverting Gates

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

1. Life support devices or systems are devices or systems

Revised March 2000

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

H = HIGH Logic Level

2000 Fairchild Semiconductor Corporation

DM74LS10 Triple 3-Input NAND Gate

Absolute Maximum Ratings(Note 1)

Operating Free Air Temperature Range

Storage Temperature Range