ISBN-13: 978-1540513212

Proceedings of ICAET-2016

Software defined AM transmitter using VHDL

[1]

V Bhagyalakshmi , [2] Jyoti.B

[1]
Assistant professor , GSSSIETW,Mysore, [2] Assistant professor , GSSSIETW,Mysore
[1]
vbhagyalakshmi@gmail.com, [2]jyothi.b @gsss.edu.in

Abstract Software Defined Radio (SDR) system is a radio

communication system where components that have typically
been implemented in hardware (i.e. mixers, filters, amplifiers,
modulators/demodulators, detectors. etc.) are instead
implemented using software on a personal computer or other
embedded computing devices. While the concept of SDR is not
new, the rapidly evolving capabilities of digital electronics are
making practical many processes that were once only
theoretically possible. The objective of this work is to design and
develop an Amplitude Modulation Software Defined Radio
Transmitter on FPGA. The FPGA is configured as a digital
amplitude modulator using behavioral modeling with VHDL. In
addition to that the FPGA should have the digital parts of ADC
and DAC which are basically mixed circuits. The base band
signal in the audio spectrum is acquired by the FPGA based
system and is amplitude modulated and fed to the antenna
through an ADC. In addition to that clock signal should also be
fed to the FPGA as clock generating circuit is not a digital
circuit. The system can be easily verified if it is designed for the
spectral range of AM receiver commonly available in the
market. A successful reception of the transmitted base band
signal in the AM receiver verifies the working of the proposed
system.

Globalization of Software Radio [1], which provides a

more comprehensive review of current R&D activities in
software radio handsets and base stations. For a general
introduction to software radio the reader is referred to the
classic 1995 Special Issue of IEEE Communications
Magazine [2] on the topic and to [3, 4].
Review a new direct digitization approach for
digital RF architectures for software radio. Although
direct digitization usually implies the simultaneous
digitization of all channels in a particular band at a down
converted IF, use this term to refer exclusively to the direct
digitization of all bands, from near DC to RF. Present
results on band selection and digitization of RF signals
directly at the carrier frequency with high resolution. These
novel approaches are enabled by a superconductor
analog-to-digital converter technology using an ultra fast IC
logic known as Rapid Single Flux Quantum (RSFQ) logic,
with performance capable of enabling envisioned software
radios [5].
Also referred to as spectrum commons [6], [7],
this model employs open sharing among peer users as the
basis for managing a spectral region. Advocates of this
model draw support from the phenomenal success of
wireless services operating in the unlicensed industrial,
scientific, and medical (ISM) radio band (e.g., WiFi).
Centralized [9], [10] and distributed [11][12] spectrum
sharing strategies have been initially investigated to address
technological challenges under this spectrum management
model.

Index Terms AM Modulator, FPGA, VHDL.

I. INTRODUCTION
Software Defined Radio is not a very new idea,
however with advances in Digital Signal Processing
technology and other associated electronics, the technology
has only recently been considered achievable. Numerous
companies and technical institutions have now decided to
pursue SDR research in recognition of the opportunities that
lie in the use of the technology. The program is unique
compared to all the existing programs as it is flexible. This
flexibility makes the FPGA a powerful instrument in the
development of SDR.

Although the SDR design methodology has been widely

studied, there have been only a few attempts to
mathematically model the design process [13] and [14].
Unfortunately, the existing mathematical formulations are
not applicable to many engineering problems, as they are
either excessively abstract in nature [13] or exclusive in
assumption [14]. In this paper, we present a rapid
prototyping method, applicable to industrial developments,
for the SDR, or indeed any embedded system, design flow.

The reprogrammable nature of the FPGA is what

makes it ideal for SDR, since any software upgrades or
changes in network architecture can be easily uploaded to the
device without any hardware reconfiguration. The proposed
project will make use of the available technologies, beginning
development as a Software Controlled Radio, where
frequency selection will be the variable controlled by a digital
system prototyped by an FPGA. The resources available on
the FPGA will allow further controls to be implemented, at a
later stage with no or little added cost.

To achieve rapid development, it is imperative that both

software-hardware requirements and assignments to be
reliably and readily identified. The key benefit of a
refinable development is that a roadmap may be envisioned
without delving into the details of the implementation. This
in turn avoids the over reliance on the error prone top-down
design flow, in the favour of more realistic paradigms such
as spiral design method [15].

II. LITERATURE SERVEY

The article complements one in the recent IEEE
Communications Magazine Feature Topic on

SYSTEM DESIGN AND IMPLEMENTATION

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Based on the literature review, upon comparing the

different possibilities to realise the system, a basic model of
the system has been planned. The same has been explained
in detail taking each block into consideration.

Fig 2. Block diagram of condenser microphone

The output of the microphone is to be fed to a high input
impedance amplifier in general. Upon prototyping of this
part, it was found that the microphone used had the ability
to make full VCC swing without an amplifier. Hence the
output of the circuit was taken out directly. The load test
that is related to the output impedance of the microphone
does matter. But since the next Stage being fed by the
microphone output happens to be a comparator; the
necessity of a buffer has also been undermined.

OVERVIEW OF THE SYSTEM

The objective of the system is to develop a modulator which
will receive an audio input and will amplitude modulate it.
The first block in the system is a microphone. The output of
the microphone is amplified and then fed to the analogy to
digital converter system. The block diagram shown in Fig 1
is an overview of the proposed system.

CLOCK GENERATION PROGRAM

This generates clock frequency which provides the base for
all timed application and modules that are functional in this
project. Crystal oscillator produces 50MHz frequency
signal. In this part of program output of crystal oscillator is
divided to get sampling frequency and carrier frequency
signal.
CARRIER FREQUENCY GENERATOR
In this part of program, the oscillator frequency 50 MHz is
divided by 25 to get 2 MHz frequency carrier signal.
Carrier signal is a square wave which is used for amplitude
modulation.

Fig 1. Functional block diagram of the system. A source of

carrier frequency is needed to generate the carrier
frequency. The output of the ADC is to be modulated
digitally with the modulator system. The final modulated
output is to be fed to the antenna or transmission part upon
necessity.

SAMPLING CLOCK GENERATOR

The Nyquist Theorem, also known as the sampling theorem,
is a principle that engineers follow in the digitization of
analog signals. For analog-to-digital conversion (ADC) to
result in a faithful reproduction of the signal, slices, called
samples, of the analog waveform must be taken frequently.
The number of samples per second is called the sampling
rate or sampling frequency. According to the Nyquist
Theorem, the sampling rate must be at least 2fmax, or twice
the highest analog frequency component. The sampling in
an analog-to-digital converter is actuated by a pulse
generator (clock). If the sampling rate is less than 2fmax,
some of the highest frequency components in the analog
input signal will not be correctly represented in the
digitized output. When such a digital signal is converted
back to analog form by a digital-to-analog converter, false
frequency components appear that were not in the original
analog signal. This undesirable condition is a form of
distortion called aliasing.

The overview of the system shows that the system has both
analog and digital circuits. Microphone, Amplifier and
Antenna are analog system and are totally beyond the
purview of implementation on FPGA. To realise ADC,
Modulator and Carrier Frequency Synthesis, FPGA or an
FPGA kit can be used. A point to be noted here is that ADC
and DAC comes under mixed system category.
The carrier frequency, the sampling clock for analog to
digital converter is to be synthesised by suitably dividing
the crystal based clock on the FPGA kit. FPGA as such will
never have a clock generator or time based signal synthesis
feature on it.
MICROPHONE SYSTEM
Audio input is fed to the condenser microphone as its core
converter of audio signal to electrical signal. A microphone
is an acoustic-to-electric transducer that converts sound
into an electrical signal. The block diagram of condenser
microphone is shown in Fig 2.

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From the above analysis it can be seen that at least

two samples of a sinusoid is required per cycle of the
sinusoid to recover it promptly. In addition to that looking
in to the type of conversion we have employed here, which
is a successive counter approach, we need a clock at higher
rate for clocking the analog to digital converter. Maximum
frequency of audio speech is 20 KHz. The Nyquist criteria
states that we need to sample the signal at a rate more than
twice the maximum frequency content in the analogy signal
to be digitised.
fm = 20 KHz
fs > fm x 2
fs > 40 Kilo Samples per second
Bus width of ADC = 3
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Proceedings of ICAET-2016

Number of quantisation levels = 2^3 = 8

fc >= 40 * 8 K = 320 K

When data is in binary form, the 0's and 1's may be of

several forms such as the TTL form where the logic zero
may be a value up to 0.8 volts and the 1 may be a voltage
from 2 to 5 volts. The data can be converted to clean digital
form using gates which are designed to be on or off
depending on the value of the incoming signal. Data in
clean binary digital form can be converted to an analog
form by using a summing amplifier which is Fig 4.

The FPGA kit has an inbuilt clock of 50 MHz. Hence it was

decided to divide the clock by a factor of 150 so that
sampling clock operates at 333 K Samples per second.
These frequency signals are obtained by dividing the crystal
frequency which generated on the FPGA kit.
Analog to Digital Converter (ADC)

A simple 4-bit D/A converter can be made with a four-input

summing amplifier. DAC is an analog circuit and hence is
realised with discrete components outside FPGA.

By comparing the different structures of analog to digital

converters, it is decided to use delta encoded ADC for the
realisation of analog to digital conversion stage in the
project. Fig 3 shows an overview of the ADC implemented
in the project.

Fig 4. Weighted summing amplifier

By the end of the project discussion, a revelation is made on
how multiple tasks to be carried out by different op-amps can
be integrated on to a single op-amp and thus making the
circuit simple and more reliable. Again the output of DAC is
compared with input voltage; this process continues to
produce modulated output.

Fig 3. Block Diagram of Analog to Digital Converter

COMPARATOR

BAND PASS FILTER DESIGN

Comparator compares the input signal which is coming
from Microphone is fed to the non inverting terminal and
the output of DAC which is fed to the inverting input of an
op amp. It is implemented in single power supply systems.
So that the values 0 V and 5 V are taken for modulation
process.

A band-pass filter is a device that passes frequencies within a

certain range and rejects frequencies outside that range. An
example of an analog electronic band-pass filter is an RLC
circuit. These filters can also be created by combining a
low-pass filter with a high-pass filter.

A standard op-amp operating without negative feedback

can be used as a comparator. When the non-inverting input
(V+) is at a higher voltage than the inverting input (V-), the
high gain of the op-amp causes it to output the most positive
voltage it can. When the non-inverting input (V+) drops
below the inverting input (V-), the op-amp outputs the most
negative voltage it can. Since the output voltage is limited
by the supply voltage, for an op-amp that uses a balanced,
split supply, In this case the supply is a single polarity
supply which takes the value of +Vcc and 0 v.

Very low frequencies are blocked by C2 and, therefore,

cannot appear at the op amp output, Very high frequencies
are fed back to the inverting opamp input with a factor of
early "1" (via C1 and C2), they are amplified by nearly
"zero". As a consequence: the circuit has a the feedback
network is, in principle; a "bridget-T" network which is
known to exhibit a complex "zero".

Up/down counter program is implemented on FPGA. In

this process initially the count is set to mid value 100.
Counter up counts if the output of the comparator is high
else the value is decremented i.e. down counted. Counter
output is fed to the DAC, which converts digital data to
analog data.
DIGITAL TO ANALOG CONVERTER (DAC)
Fig 5 Narrow Bandpass filter gain Vs frequency graph

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The narrow bandpass filter is designed to get a sharp

frequency of 2MHz, which is shown in the Fig. 5 Due to the
feedback action of the op amp the complex zero is
transferred to a complex pole pair which shown in Fig 6.

(C) of a turn is approximately one wavelength (l), and, the

distance (d) between the turns is approx. 0.25C. The size of
the reflector (R) is equal to C or l, and can be a circle or a
square. The design yields circular polarization (CP), which
can be either 'right hand' or 'left hand' (RHCP or LHCP
respectively), depending upon how the helix is wound. To
have maximum transfer of energy, both ends of the link
must use the same polarization, unless use a (passive)
reflector in the radio path.

Fig 6. Narrow band pass filter circuit

Designing of the parameter values are calculated by using
equations 1, 2, 3 and 4.
By Choosing C1 = C2 = 0.01 F
f c = 2MHz Af = 10
Q = f0/f = 2MHz/ 5KHz = 400 ohm
R1 = R4 = Q/ 2C1fcAf = 318.3 ohm
R3= 19 R1= 6.0478 ohm
R2= R1/19= 16.75 ohm

The gain (G) of the antenna, relative to an isotrope

(dBi), can be estimated by the equation 1,
(1)
(2)
(3)
(4)

G =11.8+ 10*log {(C / l) ^ 2*N*d}dBi

(5)

The characteristic impedance (Z) of the resulting

'transmission line' empirically seems to be:

ANTENNA DESIGN
Z = 140 * (C / l) Ohm
An antenna is an electrical conductor used in the
transmission and reception of electromagnetic energy by
converting radio waves into electrical signals and
vice-versa. In normal circuits, electric energy either
remains within the circuit and performs useful work or is
converted into heat. When a resonant element (an antenna)
is added to a RF circuit, it will redirect some of its power
along the antenna, which will create an electromagnetic
field. This energy is then radiated into space. This is basis
for radio communications.

Axial-mode helix antenna, first described by

Kraus in 1947, is probably the most widely used
circularly-polarized antenna, either in space or on the
ground. There are conflicting claims for the gain of the
antenna; most amateur literature, and even many standard
textbooks, quote gains which are far too optimistic. More
realistic gain relationships are available now in the
professional antenna journals, but are not well known in
amateur circles.

A helical antenna is used as a transmitting antenna

consisting of a conducting wire wound in the form of a helix.
In most cases, helical antennas are mounted over a ground
plane.
CRITICAL DESIGN PARAMETERS
The portable antenna environment is different
than that of mobile or base station antennas. In general, the
basic concepts of antenna tuning, gain, radiation pattern,
VSWR, etc. are the same, but significant new variables are
introduced:
The size of the chassis (expressed as a function of
wavelengths)
The shape of the chassis (short and squat, long and thin,
etc.)
The construction of the chassis (plastic or metal)
The environment in which it is used (surrounding objects,
metal, etc.)
The effects of the individual operating the product
All of the above have a significant effect upon the
antenna system performance and therefore must be taken
into consideration during the design stage.
The
helix antenna
can
be
considered as a
spring with N
turns with a
reflector. The
circumference

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71

The modeling data were compared with results

from the professional antenna literature. Reassuringly, the
modeling gives results which are intermediate between
published experimental and theoretical work. The
maximum possible gains are up to 4 or 5 dB lower than
those derived from the original Kraus formula for gain. The
maximum gain increases much more slowly with increasing
antenna length than the simple Kraus formula would
predict.
An empirical expression for the maximum possible gain
Gmax of the helical antenna as a function of its length L in
wavelengths is:
Gmax (dB) = 10.25 + 1.22 L - 0.0726 L^2

(7)

This expression is only valid for lengths L between 2 and 7

wavelengths. An empirical expression for the turn radius
Rmax at which peak gain occurs as a function of length L in
wavelengths .The antenna used for the transmitter is a
single coiled helix antenna with 42 turns. The Designed
values are calculated by using equation 8,9 and 10.
Assumed data,
N = 42 turns
S = 0.03 mm
D = 10 mm
C = D = 10 mm = 31.41 mm
= S/D = 0.25mm
A=NS=420.03mm=1.6m

(8)
(9)
(10)

Where, D = diameter of helix (center to center helix),

C = circumference of the helix,
S = spacing between turns,
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Proceedings of ICAET-2016

= pitch angle of the helix,

N = total number of turns,
A = axial length of the helical antenna.
Another important factor when designing an antenna
system is the location and orientation of the antenna on the
wireless device. Propagation within buildings is governed
by the following factors: attenuation due to walls, reflection
from walls, ceiling, floor, etc. and diffraction from
obstacles within a building. With this in mind, it is best to
mount the antenna higher than any obstacle between the
transmitter and receiver and to orient it in the same
electrical direction (polarity) as the receiver antenna.
Unfortunately, this is usually not possible in most portable
applications. Two important things to consider when
placing the antenna are

using Behavioural simulation. The Snapshots of the

simulation results are discussed in detail.
The Fig 7 shows the behavioural simulation result of the
amplitude modulator system designed. A point to be noted
is that, the system developed is a mixed system. The
simulation can verify only the digital part of the system.
The verification is carried out by looking into the different
signal lines which are shown in the simulation results. The
entire signal values are digital and are plotted with respect
to time.

Any metal surfaces that surround or partially surround the

antenna will distort the radiation pattern. This distortion
will impair the quality of transmission. Therefore, the
antenna must be placed outside of the shielded housing of
the device. Also, it should be placed as far away
horizontally from any surface that would block the line of
sight of the receiver antenna.
Another consideration while locating an antenna on the
appliance is the user effect. It is best to locate the antenna
away from the users body. The interaction between user
and the antenna can cause a de-tuning effect on the antenna
and also the user can absorb energy that was to be
transmitted into radio signals.
A digital modulation technique, broadcast system, and
apparatus for the spectral superposition of an analog AM
signal and a novel digitally modulated signal. Multiple
mutually orthogonal, continuous-valued noise-like
sequences are amplitude and phase modulated. Preferably,
modulation coefficients are mapped from the formatted
data to be transmitted and basis waveforms are generated
which are then modulated by the modulation coefficients.

Fig 7. Snap Shot of Design Object of Top Level Symbol

There are four major terminals contained in the block

diagram of Amplitude modulator shown in Fig 7. They are
described below. This snapshot represents a black box
model of SDRs Amplitude modulator. None of the actual
circuitry is shown but the definition enables the FPGA to
function according to the requirement specified by the
behavioural model without any internal components
knowledge.
(i) ck carrier frequency and sampling frequency
(ii) ip input from the comparator output
(iii) V in input for DAC module
(iv) Op which is fed to the input DAC

In the broadcast system of the present invention, an

amplitude modulated signal having a first frequency
spectrum is broadcast simultaneously with a plurality of
amplitude and/or phase modulated orthogonal noise-like
signals having a bandwidth which encompasses the first
frequency spectrum. The amplitude modulated signal
includes a first carrier modulated by an analog signal.
A first group of the amplitude and/or phase modulated
orthogonal noise-like signals lying within the first
frequency spectrum are modulated in-quadrature with said
first carrier signal. The second and third groups of the
amplitude and/or phase modulated orthogonal noise-like
signals lie outside of the first frequency spectrum and are
modulated both in-phase and in-quadrature with the first
carrier signal.
RESULTS
A digital system coded in VHDL can be verified with two
kind of simulation. They are behavioural simulation and
post route simulation. The verification of the code is done
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Fig 5. Snap Shot Of Design Objects Of modulator

The Fig 5. shows the block diagram which is generated
according behavioural code. This block diagram is

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ISBN-13: 978-1540513212
generated automatically when the AM code is simulated. It
shows the components of a circuit that would essentially
work as an amplitude modulator using FPGA base.

Proceedings of ICAET-2016
scheme. The testing of the prototype of the proposed system
verified. The current work offers scope to carry out further
developments in this regard.
Implementation of other modulation schemes on FPGA , as
the implementation of Amplitude modulation scheme using
VHDL gave satisfactory results, further developments
using Frequency modulation and other digital modulation
schemes can also be implemented.
Implementation of dynamically reconfigurable modulation
systems. Reconfiguration of the system can be done easily
using FPGA. So reconfigurable systems can be
implemented using this method.
Intelligent systems with auto modulation detection and
reconfiguration features.

REFERENCES
Fig 6. Behavioural simulated waveforms
The Fig 6. Shows the behavioural simulation of the
Amplitude modulator, the waveform shows the internal
clock generation (ck). The original clock has been divided
into carrier frequency and sampling frequency, calculations
are shown below.
fm = 20 KHz, fs > fm x 2
fs > 40 Kilo Samples per second
Bus width of ADC = 3
Number of quantization levels = 23 = 8
fc >= 40 * 8 K = 320 K
The FPGA kit has an inbuilt clock of 50 MHz. Hence it was
decided to divide the clock by a factor of 150 so that
sampling clock operates at 333 K Samples per second.
Clock frequency 50MHz from the crystal oscillator which
is shown in the first waveform, which is the base for
processing digital modulation. The second waveform
named ckamt which is a carrier frequency of 2Mhz
produced by dividing the main clock by 25. Ckst is the
sampling frequency produced by dividing the main clock ck
by 75. Input frequency is audio signal to the modulator in
the form digital data which is shown as ip. Vin and op are
the counter value and output from the modulator fed to the
DAC.
CONCLUSION
A software defined amplitude modulator has been designed,
implemented and verified. It has been found that the system
is working properly. The prototype system receives and
analog input and modulates the base band analog signal into
2 MHz, which comes in the Medium Wave Band of radio
communication. The system has been verified by tuning an
AM receiver in the MW band to a frequency of 2 MHz. The
software defined system is implemented on an FPGA
prototyping board with an on board crystal oscillator
operating at 50 MHz.
The project work has been carried out to test the feasibility
using a digital system for carrying out analog modulation
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[14] A.R. Rhiemeier, F. Jordnal, "Mathematical modelling of the

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