Fire 166cbc

FIRE Emulator for C166 Cell-Based-Core
TRACE32 Online Help

TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
FIRE In-Circuit Emulator ...............................................................................................................
FIRE Target Guides ....................................................................................................................
FIRE Emulator for C166 Cell-Based-Core .............................................................................
WARNING ..............................................................................................................................
Quick Start ............................................................................................................................
Troubleshooting ...................................................................................................................
Hang-Up
Dualport Errors
10
FAQ ........................................................................................................................................
10
Configuration ........................................................................................................................
11
Basics ....................................................................................................................................
12
Emulation Method
12
Emulation Modes
12
SYStem.MemAccess
Dualport access
13
SYStem.CpuAccess
Dualport access
14
General SYStem Settings and Restrictions .......................................................................
16
General Restrictions
16
SYStem.CPU
Processor type
16
SYStem.Option MODE
Operation mode
17
SYStem.Option BusType
Operation mode
18
Segmentation
18
Chip selects
19
SYStem.Option SGT
SYStem.Option CS
SYStem.Option CLOCK
PLL selects
19
CS programming
20
SYStem.Option EarlyWrite
Write operation mode
20
SYStem.Option WriteLimit
21
SYStem.Option CS_Register
SYStem.Option PERSTOP
Peripheral freeze
21
SYStem.Option DUALPORT
Dualport mode
21
SYStem.Option IMASKASM
Mask interrupts during assembler step
21
Mask interrupts during HLL step
22
Monitor base
22
SYStem.Option IMASKHLL
SYStem.Option MonBase
1989-2016 Lauterbach GmbH
SYStem.JtagClock
SYStem.Option ONCE
Jtag clock
22
On-circuit emulation
23
On-circuit emulation reset
23
SYStem.RESetOut
Peripheral reset
23
SYStem.Option BOOTSTRAP
Bootstrap mode
23
SYStem.Option ONCEReset
SYStem.Option ResetExt
Reset mode
24
Startup settings
25
Voltage sense
25
WRL/WRH mode
25
On-chip Trigger-Unit ............................................................................................................
26
SYStem.Option
SYStem.Option V33
SYStem.Option WRC
General Description
26
Possible Combinations
27
Examples
27
Specific TrOnchip Commands ............................................................................................

TrOnchip.view
View window
TrOnchip.RESet
TrOnchip.CONVert
TrOnchip.Address
TrOnchip.CYcle
28
28
Reset settings
28
Convert breakpoints
28
Select address selector
28
Select bus cycle
29
TrOnchip.Data
Set data selector value
29
TrOnchip.TaskID
Set task selector value
29
Trigger Commands ..............................................................................................................
30
TrBus.Out
Define source for the external trigger pulse
30
TrBus.Set
Define the target for the incoming trigger
30
Exception Control ................................................................................................................
31
Schematics
31
Reset
31
eXception.state
Exception control
31
Force exception
32
eXception.Enable
Enable exception
32
eXception.Trigger
Trigger on exception
33
Stimulate exception
33
Breakpoints ...........................................................................................................................
34
eXception.Activate
eXception.Pulse
Breakpoint Realization Modes
34
Memory Classes ...................................................................................................................

Overview
36
36
State Analyzer .......................................................................................................................
37
Keywords for the Display
37
Keywords for the Analyzer Trigger Unit
37
General C166CBC Keywords for the Emulator Trigger Unit

Port Analyzer ........................................................................................................................
37
38
Port Signals EGOLD
38
Port Signals EGOLDP
39
Port Signals UTAH
40
Technical Data ......................................................................................................................
41
Mechanical Dimensions
41
Adaptions
43
Adapters
44
Operation Voltage
46
Operation Frequency
46
Support ..................................................................................................................................
47
Probes
47
Available Tools
47
Compilers
48
Realtime Operation Systems
48
3rd Party Tool Integrations
49
Products ................................................................................................................................
50
Product Information
50
Order Information
50

Version 24-May-2016
F::d.l
ddr/line
code
P:00010832 6303
545
P:00010834
P:00010836
546
P:00010838
P:0001083A
547
P:0001083C
P:0001083E
P:00010840
label
333C
7303
add
add
6203
323C
mov
add
3247
8D06
6743
cmp/gt
bt/s
mov
549
P:00010842 6123
F::r
T
_
S
_
I
F
Q
_
M
_
Tsk
R0
R1
R2
R3
R4
R5
R6
R7
GBR
VBR
MACH
MACL
mnemonic
mov
{
0
1
1
0
12
4006C0
0
12
0
0
1800000
2BCE
mov
R8
R9
R10
R11
R12
R13
R14
R15
PC
PR
SR
0
0
0
0
0
0
407FEC
407FEC
10834
107A2
0F0
r0,r3
comment
; return,primz
primz = i + i + 3;
r3,r3
; primz,primz
#3,r3
; #3,primz
k = i + primz;
r0,r2
; return,k
r3,r2
; primz,k
while ( k <= SIZE )
r4,r2
; r4,k
1084E
r4,r7
{
flags[ k ] = FALSE;
r2,r1
; k,r1
SP >00407FF4
+04 0001080C
+08 00010016
+0C 00000000
+10 00000000
+14 DEADDEAD
+18 00000000
+1C 00000000
+20 00000000
+24 00000000
+28 00000000
+2C 00000000
+30 00000000
F::v.w
flags = (1, 1, 1, 1, 1,
ast = (word = 0x0,
count = 12346,
left = 0x400710,
right = 0x0,
field1 = 1,
field2 = 2)
For general informations about the In-Circuit Debugger refer to the FIRE Users Guide (fire_user.pdf). All
general commands are described in IDE Reference Guide (ide_ref.pdf) and General Reference
Guide.
WARNING
NOTE:
Do not connect or remove probe from target while target power is ON.
Power up:
Switch on emulator first, then target
Power down: Switch off target first, then emulator
Quick Start
Before debugging can be started, the emulator must be configured by software:
Ready to run setup files for most standard compilers can be found on the software CD in the directory ../
Demo/c166cbc/Compiler. All setup files are designed to run the emulator stand alone without target
hardware.
The following description should make the initial setup (to run the emulator together with the target
hardware) easier. It describes a typical setup with frequently used settings. It is recommended to use the
programming language PRACTICE to create a batch file, which includes all necessary setup commands.
PRACTICE files (*.cmm) can be created with the PRACTICE editor pedit (Command: PEDIT <file name>)
or with any other text editor.
A basic setup file includes the following parts:
1.
Set cpu-type and -mode
2.
Set system options
3.
Select dualport mode (optional)
4.
Set mapper (optional)
5.
Select monitor base
6.
Define CS settings
7.
Select frequency (optional)
8.
Activate the emulator
9.
Load application file (optional)
10.
Set breakpoints (optional)
11.
Start application
12.
Stop application (optional)
WARNING
Here a typical example, how to set up the system:

1.
Set cpu-type, bustype and -mode options

The command sys.cpu is used to select one derivative within a cpu-family and to set its operation
mode.
system.down
system.cpu pmb2850
system.cpu EXT16
2.
; switch the system down

; select derivative SH7044
; set the operation mode EXT16
Set system options

The system window controls the CPU specific setup. Please check this window very carefully and set
the appropriate options. Use the ? button in the main tool bar and click to the option check box
(Command: HELP.PICK) to get online help in a pop up window.
system.memaccess ARAM
system.option ew on
system.option wdtdis on
3.
; Select type of DP access

; Select early write for high-speed
; Disable watchdog
Select dualport mode (optional)

Dualport allows access to emulation RAM, while emulation is running. This is necessary to display
variables, set breakpoints or display the flag listings while the emulation is running.
System.CpuAccess selects how dualport access is done.
system.access request
4.
; request: a dedicated bus request

; signal of the bondout cpu is used
; denied: dualport is disabled
Set mapper
The mapper controls the memory access of the CPU. This means the use of internal or external
memory, the protection of a memory bank etc. Address ranges must be defined by using memory
classes.
map.reset
; reset mapper (all external)
map.ram 0--0bfff
map.i 0--0bfff
; emulation RAM:
map.ram 0x228000++7fff
map.i
0x228000++7fff
; emulation RAM
map.ram 0x410000++0xffff
map.i
0x410000++0xffff
; emulation RAM
Quick Start
5.
Select monitor base address

The emulation is done by a target-based monitor. An address range by 100h is used by the monitor
and cannot be used by the application. The monitor area must be in RAM and can be relocated in
steps by 100H.
system.option monbase 0x200
6.
; define area for monitor
Define CS settings
The emulator must have this settings for programming its internal address rebuilding system. All
buscon and addrsel registers are programmed by the emulator after activating the emulation system.
Otherwise no code can be loaded.
system.option buscon0 0xc4bf
; Settings for BUSCON
system.option buscon1 0xc4bf

system.option addrsel1 0x2206
system.option buscon2 0x0
system.option buscon3 0x40e
system.option buscon4 0x0
system.option pdconf 0x2c
system.option pdaltsel 0x0
system.option pfconf 0xb800
system.option pfaltsel 0x800
7.
Select frequency (optional)

The CPU can be clocked by an internal (emulator) or external (target) clock source. If the internal
clock is used, the clock is provides by the VCO of the emulator. The setting of the internal clock is
done by the vco command.
The current CPU frequency can be displayed in the counter window (Command: Count).The clock
output must be enabled.
vco.frequency 13.
;
;
;
;
input clock to the EXTAL pin of

the cpu is set to 13 MHz
(only necessary if internal clock
is used)
Quick Start
For the CPUs with PLL the PLL factor has to be defined.
vco.frequency 8.0
; input clock to the EXTAL pin of

; the cpu is set to 8 MHz
; set PLL factor
system.option clock 4.5
8.
Activate the emulator

When the emulator is activated a debug-monitor program is loaded into a hidden emulator memory.
Afterwards, a bondout reset-signal is inactivated and the monitor program starts. This program allows
access to user memory (data.dump, data.list) and cpu-registers, and gives control to start and stop
the emulation.
system.mode emulext
9.
; system works with external target

; clock
Load application file (optional)

Application can be loaded by various file formats. COFF format is often used to load code and symbol
information. For information about the load command for your compiler see Compiler.
d.load.omf keilcl /p /lpath
10.
; load application file
Set breakpoints (optional)

There are several ways to set breakpoints (Command: Break.Set). Breakpoints can be displayed
using the Break.List command.
breakpoint.set main /program
breakpoint.set flags /write
11.
;
;
;
;
set program break on function

main
set write break on variable
flags
Start application
Application can be started with giving a break address. For example go main starts the application
and stops at symbol main.
go
12.
; run application
Stop application (optional)

Application can be breaked manually by using th BREAK command.
break
; stop application manually
It is recommended to check the following chapters Configuration and Troubleshooting for all
questions regarding the correct setup.
Quick Start
Troubleshooting
Hang-Up
If you are not able to stop the emulation, there could be some typical reasons:
Active target-reset
The BREAK command wont stop the emulation if the target-reset

is active and the reset-line is enabled in the exception control.
Troubleshooting
Dualport Errors
Dual-Port Busy
GAP Mode: The CPU makes no cycles on external bus interface

ARAM Mode: The CPU makes no cycles on external bus interface
or the CPU makes only cycles in a small loop. For dualporting on
ARAM modules the address line A2 must be toggling.
FAQ
Debugging via
VPN
The debugger is accessed via internet/VPN and the performance is very

slow. What can be done to improve debug performance?
The main cause for bad debug performance via internet or VPN are low data
throughput and high latency. The ways to improve performance by the debugger
are limited:
in practice scripts, use "SCREEN.OFF" at the beginning of the script and

"SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates.
Please note that if your program stops (e.g. on error) without executing
"SCREEN.OFF", some windows will not
be updated.
"SYStem.POLLING SLOW" will set a lower frequency for target state

checks (e.g. power, reset, jtag state). It will take longer for the debugger to
recognize that the core stopped on a breakpoint.
"SETUP.URATE 1.s" will set the default update frequency of Data.List/

Data.Dump/Variable windows to 1 second (the slowest possible setting).
prevent unneeded memory accesses using "MAP.UPDATEONCE

[address-range]" for RAM and "MAP.CONST [address--range]" for ROM/
FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified
address range only once after the core stopped at a
breakpoint or manual break. "MAP.CONST" will read the specified address
range only once per SYStem.Mode command (e.g. SYStem.UP).
10
FAQ
Configuration
There is no special hardware configuration necessary for C166-CBC devices. The configuration of the used
derivative and cpu-mode is done via the SYSTEM commands by software.
11
Configuration
Basics
Emulation Method
The FIRE Emulator uses a production versions of the C166 CBC CPUs.
NOTE: The emulator chip replaces the target cpu, i.e. the target cpu must be removed during emulation!
Emulation Modes
F::sys
system
Down
Up
RESet
Mode
RESet
AloneInt
AloneExt
EmulInt
EmulExt
CPU
PMB2850
MemAccess
ARAM
CPU
GAP
Denied
CpuAccess
Enable
Denied
TimeReq
1.000ms
JtagClock
5000000.
Option
WDT
PERSTOP
DUALPORT
EarlyWrit
WRC
IMASKASM
IMASKHLL
BusType
ROMEN
MODE
EXT8
MONBASE
0x200
ADDRSELx
0x0
0x0
0x0
0x0
0x0
PDCONF
0x0
PFCONF
0x0
BUSCONx
0x60D
0x0
0x0
0x0
0x0
PDALTSEL
0x0
PFALTSEL
0x0
The emulator can operate in 5 modes. The modes are selected by the SYStem.Mode command.
Format:
SYStem.Mode <mode>
<mode>:
Reset
AloneInt
AloneExt
EmulInt
EmulExt
12
Basics
Reset
CPU is in reset.
AloneInt
CPU is running with internal clock. This mode is used for 'standalone' operation.
AloneExtl
CPU is running with external clock.
EmulInt
CPU is running with internal clock.
EmulExt
CPU is running with external clock.
In active mode, the power of the target is sensed and by switching down the target the emulator changes to
RESET mode. The probe is not supplied by the target power. When running without target, the target
voltage is simulated by an internal pull-up resistor. The default voltage is 3.3V for UTAH and 2.0 V for
EGOLD devices.
SYStem.MemAccess
Dualport access
Format:
SYStem.MemAccess <option>
<option>:
GAP
ARAM
CPU
Denied
ARAM
The direct access to the asynchronous RAM is used. Any dualport logic on the
emulation system is bypassed.
GAP
The dualport access is done by inserting extra memory cycles between CPU
cycles.
CPU
The OCDS interface of the CPU is used for dualport accesses.
Denied
Dualport access is not possible while the emulation is running.
Dualport allows access to emulation RAM and on-chip ROM/FLASH, while emulation is running. This is
necessary to display variables, set breakpoints or display flag listings while the emulation is running.
Dualport access is only possible on the emulators internal RAM and not on target RAM (except for CPU
access mode).
NOTE: There is no dualport access to the on-chip IRAM and XRAM of the cpu, because this RAM is
physically internal at the cpu (except for CPU access mode).
13
Basics
SYStem.CpuAccess
Dualport access
Format:
SYStem.CpuAccess <option>
<option>:
Enable
Denied
Enable
If a dualport read/write access is requested to a non-mapped memory, a spot

point (emulation break and go) is used to access the memory.
Denied
Dualport access via spot point is not possible.
The emulator uses a two stage strategy to realize the best possible dualport access method:
If MemAccess is set to ARAM or GAP, the emulation controller tries a bus arbitration access as dualport
cycle. This is possible if memory is mapped to internal and on read cycles to shadow memory. Shadow
memory means, that memory is mapped in the emulator (map.ram), but the area is mapped external
(map.extern). On access to external mapped memory and write access to shadow memory the dualport is
executed as a spot point if CpuAccess is enabled. Dualport on access to external mapped memory and
write access to shadow memory is disabled if CpuAccess is disabled.
If MemAccess is set to CPU, the emulation controller uses the OCDS interface of the CPU to realize the
dualport cycle. The advantage of this method is that all memories, independent on the mapping, can be
used. CpuAccess switch is ignored if MemAccess is set to CPU.
If MemAccess is set to Denied and CpuAccess is enabled, the emulation controller uses a spot point to
realize the dualport cycle. If MemAccess is set to Denied and CpuAccess is disabled, dualport access is not
possible.
14
Basics
The following table shows how the dualport is realized depending on the used system setting:
MemAc
cess
CpuAccess
Read
Map
Int.
Write
Map
Int.
Read
Shado
w
Write
Shado
w
Read
Map
Ext.
Write
Map
Ext.
GAP/
ARAM
Enable
GAP/
ARAM
GAP/
ARAM
GAP/
ARAM
Spot
Spot
Spot
GAP/
ARAM
Denied
GAP/
ARAM
GAP/
ARAM
GAP/
ARAM
CPU
Enable
OCDS
OCDS
OCDS
OCDS
OCDS
OCDS
CPU
Denied
OCDS
OCDS
OCDS
OCDS
OCDS
OCDS
Denied
Enable
Spot
Spot
Spot
Spot
Spot
Spot
Denied
Denied
GAP/ARAM: The bus arbitration interface of the CPU is used for dualport access. Application
performance is only slightly influenced.
CPU: The OCDS interface of the CPU is used for dualport access. Application performance is more
influenced than with request mode.
Spot: The emulation is breaked, memory access is done via CPU, emulation is continued. Application
performance is most influenced with this method.
15
Basics
General SYStem Settings and Restrictions
General Restrictions
On-chip RAM
The CPUs on-chip IRAM and XRAM is physically internal at the chip.
This means that there is no emulator based dualport access available to
this RAM.
Interrupt requests
during the emulation is stopped
Exceptions and interrupts are not handled during the emulation is

stopped. Some of them are stored and executed after starting the
emulation (see chapter Exception Control). If you will have problems
with either your target hardware or you application program because of
the blocked interrupts, then you have to use a foreground monitor.
Pending interrupts
during single-step
When executing an assembler step and external or internal interrupts are

pending, the emulator will not step into the interrupt handler and stops at
the next instruction. The execution of the interrupt program can be
avoided either by preventing the interrupt, e.g. stop the timer while the
emulation is stopped (see timer control) or by masking the interrupt in
the CPU (command SETUP.IMASKASM). For HLL steps the problem
can be solved in the same way (command SETUP.IMASKHLL).
SYStem.CPU
Processor type
Format:
SYStem.CPU <type>
<type>:
PMB2850
PMB6850
C165UTAH
This selects the exact derivative within a CPU-Family.
16
SYStem.Option MODE
Operation mode
Format:
SYStem.Option MODE <mode>
<mode>:
EXT8
EXT16
INT8
INT16
This option specifies operation mode of the cpu, which is normally defined with the MON0 and MON1 pins of
the cpu. But, the values of this pins in the target are not responsible for the operation mode, so that the pin
levels can differ from the emulator setting.
EXT8
CS0 is an external memory area with 8-bit bus width. The on-chip ROM is
disabled.
EXT16
disabled.
INT8
enabled.
INT16
enabled.
17
Operation mode
Format:
SYStem.Option BusType <mode>
<mode>:
ROMEN
NOMUX8
NOMUX16
MUX8
MUX16
This option specifies operation mode of the cpu, which is normally defined with the P0L.[7..6] and EA- pins
of the cpu.
NOMUX8
CS0 is an external memory area with 8-bit bus width (non-multiplexed). The onchip ROM is disabled.
NOMUX16
CS0 is an external memory area with 16-bit bus width (non-multiplexed). The onchip ROM is disabled.
MUX8
CS0 is an external memory area with 8-bit bus width (multiplexed). The on-chip
ROM is disabled.
MUX16
CS0 is an external memory area with 16-bit bus width (multiplexed). The on-chip
ROM is disabled.
ROMEN
The on-chip ROM is enabled.
SYStem.Option SGT
Segmentation
Format:
SYStem.Option SGT <size>
<size>:
256K
1M
2M
8M
16M
The segmentation settings define the reset vector on cpu reset.The 16 Mbyte mode disables all address
regeneration operations (fastest memory mode). All address lines A0 to A22 must me activated (UTAH
only). This is the fastest memory mode which allows zero wait state emulation at 36 MHz core frequency.
18
SYStem.Option CS
Chip selects
Format:
SYStem.Option CS <size>
<size>:
0
2
3
5
The reset vector for the chip selects is defined.
SYStem.Option CLOCK
PLL selects
Format:
SYStem.Option CLOCK <factor>
<factor>:
0.375
0.5
1.0
1.125
1.5
3.0
4.5
6.0
The reset vector for the PLL multiplier is defined for the UTAH emulation probe.
19
SYStem.Option CS_Register
CS programming
Format:
SYStem.Option <cs_reg>
<cs_reg>:
BUSCON[4..0]
ADDRSEL[4..0]
PDCON
PDALTSEL
PFCON
PFALTSEL
For correct operation of the C166CBC emulators all chip-select and address-line related registers must be
programmed before emulator is started. The address-regeneration is done by the emulator logic in
hardware. The BUSCON and ADDRSEL registers are programmed by the emulator system. They should
not be changed later on. The XBUSCON and XADDRSEL registers (EGOLD) must be programmed by the
user.
A16..A22
CS0..CS4
Address
Regenerator
Port D
A16..A23 to Memory
Port F
SYStem.Option EarlyWrite
Format:
SYStem.Option EarlyWrite [ON | OFF]
On high-speed emulation of the cpu, the write cycle for the dualport emulation memory must be before the
end of the cycle. Otherwise the address must be latched, which results in slower overall operations of the
system. The option is necessary for zero-wait state operation at frequencies which exceeds 20 MHz core
frequency. The option should be set to off at lower frequencies, if the RWDC bit is activated at any
BUSCONx register. If no RWDC bit is set, the option can be activated at any frequency.
20
SYStem.Option WriteLimit
Format:
SYStem.Option WriteLimit [ON | OFF]
Limited the write cycle for the dualport. On high-speed emulation of the cpu, the write cycle for the dualport
emulation memory should be limited, as the addresses can change before the end of the cycle. Otherwise
the address must be latched, which results in slower overall operations of the system. This option should be
set for system settings with zero tristate cycles (MTTC bit in BUSCON registers).
core frequency. The option should be set to off at lower frequencies, if the RWDC bit is activated at any
BUSCONx register. If no RWDC bit is set, the option can be activated at any frequency.
SYStem.Option PERSTOP
Format:
Peripheral freeze
SYStem.Option PERSTOP [ON | OFF]
This controls the operation mode of the peripherals (e.g. timer), when a debug event is raised. A debug
event causes the peripherals to suspend, if this option is activated and the suspend enable bit in the
peripheral module is set.
SYStem.Option DUALPORT
Format:
Dualport mode
SYStem.Option DUALPORT [ON | OFF]
The JTAG debugger use the Debug Peripheral Event Controller (DPEC) to access memory. This acts like a
cycle stealing DMA. Therefore memory access can be done even while the CPU is running. On activating
this option the opened data windows will also be refreshed while a user program is running. Please consider
that in this mode the user program will not be executed at full speed.
SYStem.Option IMASKASM
Format:
Mask interrupts during assembler step
SYStem.Option IMASKASM [ON | OFF]
If enabled, the interrupt mask bits of the cpu will be set during assembler single-step operations. The
interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are
restored to the value before the step.
21
SYStem.Option IMASKHLL
Format:
Mask interrupts during HLL step
SYStem.Option IMASKHLL [ON | OFF]
If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
the value before the step.
NOTE: By changing the status register through target software, this option can affect the flow of the
target program. Accesses to the interrupt-mask bits will see the wrong values.
SYStem.Option MonBase
Format:
Monitor base
SYStem.Option MONBASE <start address>
This is the start address where the exception routine is or will be loaded. The size of the exception routine is
at the moment 26 bytes.
SYStem.JtagClock
Jtag clock
Format:
SYStem.JtagClock <rate>
<rate>:
EXT | 5000000. | 2500000. | 1250000. | 625000.
Selects the frequency for the JTAG clock. This influences the speed of data transmission between target and
debugger.
EXT selects the clock on the pin CPUCLOCK of the JTAG connector as clock source.
A clock rate between 625 kHz and 5 MHz can be selected. Default is 5 MHz
22
SYStem.Option ONCE
Format:
On-circuit emulation
SYStem.Option ONCE [ON | OFF]
Set to ON when using the Clip-Over-Adapter with QFP-Packages. The CPU chip on the target board is set
to tristate on RESET of the target system (Push reset key on your target).
P0.0
Target
ONCE10K
Emulator
SYStem.Option ONCEReset
Format:
On-circuit emulation reset
SYStem.Option ONCEReset [ON | OFF]
Some new probes support target reset out of the probe for ONCE mode. The RSTIN input of the CPU must
be an open-drain type. Then the emulator can force an RSTIN signal on the target when an
SYSTEM.MODE or SYSTEM.UP command is executed.
SYStem.RESetOut
Format:
Peripheral reset
SYStem.RESetOut
The SRST instruction is executed. The RSTOUT line is set to active.
Bootstrap mode
Format:
SYStem.Option BOOTSTRAP [ON | OFF]
BOOTSTRAP
Bootstrap Mode for C165UTAH.
23
SYStem.Option ResetExt
Reset mode
Format:
SYStem.Option ResetExt [ON | OFF]
ResetExt
The setup after RESET is defined by the target system. The internal setups
(BOOTSTRAP, etc.) are ignored. This mode is valid for the C165UTAH probe
only.
Usually the probe can use the reset vector from the target. However some
targets supply this vector on reset of the target only (which must not be the
same time as the reset of the emulator), or the pull-down resistors didnt work
very fine (the buffers on Port 0 of the emulator need some input current). In all
this situations the internal reset vectors should be used:
SYStem.Option ChipSelect
SYStem.Option Clock
RSTINTarget
Emulator
24
SYStem.Option
Startup settings
Format:
SYStem.Option <mode> [ON | OFF]
<mode>:
XPerEN
XVisible
WDTdis
XPerEN
Activates the XPEN bit in the SYSCON register.
XVISIBLE
Activates the XVISIBLE bit in the SYSCON register.
WDTdis
Disables the WDT (WatchDogTimer) while activating the emulator.
SYStem.Option V33
Format:
Voltage sense
SYStemOption V33 [ON | OFF]
The threshold level for the power-down sense is reduced to 2.8V for operation with 3.3V targets.
SYStem.Option WRC
Format:
WRL/WRH mode
SYStemOption WRC [ON | OFF]
Activates the WRL/WRH mode.
25
On-chip Trigger-Unit
F::to
tronchip
RESet
CONVert
Data
TaskID
CYcle
Read
Write
eXecute
compare
NoMatch
Address
Alpha
Beta
Charly
Delta
Echo
General Description
The on-chip trigger-unit consists of one range and up to three masked value comparators. The inputs of the
comparators can be switched to the read address, write address execution address or the task ID register.
For details check the description of the OCDS cell in the processor manuals. Simple breakpoints and most
breakpoints with data values can be set directly with the Break.Set command. The TrOnchip command
allows to use more specific features and trigger on the TASKID register.
26
Possible Combinations
One
Addr
Two
Addr
Three
Addr
Four
Addr
Two
Masked
Ranges
One
Range
No Data Selector
Not Data
Not Data Range
One Data Value
Two Data Values
Three Data Values
One Data Mask
Two Data Masks
One Data Range
Other combinations may also be possible. The debugger software tries to make the best use of the on-chip
trigger registers. Ranges may be converted to masks and masks may be converted to ranges by the
debugger if this allows a better breakpoint usage. If the TrOnchip.CONvert is turned on data ranges and
masks may be extended to fit into the comparators.
Examples
Assume that there is a byte variable called 'flag', and you want to stop the emulation if the value 0x59 is
written to the variable.
TrOnchip.A.Break On
; The emulation stops on a compare match

; event
Break.Set flag /Alpha
; Set an alpha breakpoint to the address

; of the variable flag
TrOnchip.A Value 0xxx59
; Specify data pattern
TrOnchip.A Cycle Write
; Specify that you want to trigger only on

; a write access
The same can be done with one breakpoint command:

B.S flag /W /DATA.B 0x59
; Stop on a byte write of 0x59
27
Specific TrOnchip Commands
TrOnchip.view
Format:
View window
TrOnchip.view
Opens a control panel to configure the on-chip breakpoint registers.
TrOnchip.RESet
Format:
Reset settings
TrOnchip.RESet
Resets the trigger system to the default state.
TrOnchip.CONVert
Format:
Convert breakpoints
TrOnchip.CONVert [ON | OFF]
The masked hardware breakpoints can only cover specific ranges. When enabled (default) the on-chip
breakpoints are automatically converted to a larger range to fit in a masked comparator if required. If the
switch is off, the system will only accept breakpoints which exactly fit to the on-chip breakpoint hardware.
TrOnchip.Address
Select address selector
Format:
TrOnchip.Address <type>
<cycle>:
Alpha
Beta
Charly
Delta
Echo
Defines the address selector used for the on-chip trigger.

28
TrOnchip.CYcle
Select bus cycle
Format:
TrOnchip.CYcle <type>
<cycle>:
Read
Write
eXecute
Defines the bus cycle used for the on-chip trigger.

Read
Trigger on read cycles
Write
Trigger on write cycles
eXecute
Trigger on program execution
TrOnchip.Data
Format:
Set data selector value
TrOnchip.Data <hexmask> | <bitmask> | <range>
Defines the data value. The value can be up to three single values or two ranges depending on the number
and complexity of the address used for the breakpoint. The value is always 16bits wide. Triggering on an odd
byte requires that the required data value is placed in bits 8..16 of the value.
TrOnchip.TaskID
Format:
Set task selector value
TrOnchip.TaskID <hexmask> | <bitmask> | <range>
Defines the task value. The value can be up to three single values or two ranges depending on the number
and complexity of the address used for the breakpoint.
29
Trigger Commands
TrBus.Out
Format:
Define source for the external trigger pulse
TrBus.Out Break | ABreak | ATrigger [ON | OFF]
Define the source for the external trigger pulse.

Break
Generate an external trigger pulse when the program execution is stopped.
ABreak
Generate an external trigger pulse when the sampling to the trace buffer is
stopped.
ATrigger
Generate an external trigger pulse when a trigger is generated for the trace. A
trigger for the trace can be used to stop the sampling to the trace buffer after a
specified delay Analyzer.TDelay.
TrBus.Set
Format:
Define the target for the incoming trigger
TrBus.Set Break | ATrigger [ON | OFF]
Select the target for the incoming trigger signal.

Break
Stop the program execution when the external trigger signal becomes active.
ATrigger
Generate a trigger for the trace when the external trigger signal becomes
active. A trigger for the trace can be used to stop the sampling to the trace
buffer directly or after a specified delay Analyzer.TDelay.
30
Trigger Commands
Exception Control
Schematics
Reset
Vcc
X.Enable
&
Run
22K
RESETIN(Target)
RESETIN(CPU)
22R
X.Activate
or
X.Pulse
eXception.state
Exception control
Format:
F::x
exception
OFF
ON
RESet
eXception.state
Activate
OFF
RESET
Enable
OFF
ON
RESET
Pulse
OFF
RESET
Pulse
Single
Width
1.000us
PERiod
OFF
ON
0.000
31
Exception Control
eXception.Activate
Force exception
Format:
eXception.Activate RESET [ON | OFF]
Format:
eXception.Activate OFF
RESET
Activates the RESET line.
OFF
No activation of any exception line.
eXception.Enable
Enable exception
Format:
eXception.Enable RESET [ON | OFF]
Format:
eXception.Enable OFF
Format:
eXception.Enable ON
RESET
Enables the RESET line.
ON
Enables all exception line.
OFF
Disables all exception lines.
32
Exception Control
eXception.Trigger
Trigger on exception
Format:
eXception.Trigger OFF
Format:
eXception.Trigger ON
ON
Trigger on all exception lines.
OFF
No trigger on any exception lines.
eXception.Pulse
Stimulate exception
Format:
eXception.Pulse RESET [ON | OFF]
Format:
eXception.Pulse OFF
RESET
Trigger on RESET line.
OFF
No trigger on any exception line.
33
Exception Control
Breakpoints
For a basic description of the breakpoint system please refer to FIRE Users Guide.
Breakpoint Realization Modes

This chapter describes the different realization modes and shows their availability for the logical breakpoints
types.
Software
Breakpoints
Synchronous Breakpoints:
The user application code is patched with a special break-instruction of the
bondout CPU (opcode 0x0) before jumping into the user program. After
executing this instruction, the CPU stops the user program and jumps into the
emulator debug monitor.
Asynchronous Breakpoints:
These breakpoints are used as address selectors for the trigger unit (see FIRE
Users Guide).
On-chip
Breakpoints
The bondout CPU has an on-chip trigger-unit with four independent channels.
Synchronous Breakpoints:
They can be used if you would like to set a breakpoint in a target memory where
no code can be patched (e.g. EPROM or Flash).
Asynchronous Breakpoints:
The information, that a breakpoint has occurred is switched from the bondout
break controller to the trigger unit, so that the trigger unit for example can start
the analyzer.
NOTE: Since there is no breakpoint RAM in parallel to the CPUs on-chip RAM,
the on-chip trigger-unit is always used for asynchronous breakpoints to the onchip RAM.
34
Breakpoints
The following table shows realization of the logical breakpoint types in auto-mode.
Breakpoint
Type
Realization in Auto Mode
Program
Software
HLL
Software
On-chip (If the address is mapped as ReadOnly)
Stepmode (If HLL-Line is too complex)
Spot
Software
On-chip (If the address is mapped as ReadOnly)
Read, Write
On-chip
Alpha, Beta,
Charly, Delta,
Echo
Hardware
On-chip (CPUs onchip RAM area)
On-chip (If option Watch, Break or RPE is set in the on-chip trigger-unit)
35
Breakpoints
Memory Classes
Overview
Access Class
Description
CPU (Program and Data)
Data
Program
Bit Address
ED
Dualport Data
EP
Dualport Program
C:, E:, D:, P:, ED:, EP:

C:, P: and D:
This storage classes operate on the same physical memory. They are only used to be compatible with other
emulation probes.
E:, EP: and ED:
The E: prefix is used for accesses via dualport. The on-chip I/O-registers and the on-chip RAM area cant be
accessed via dualport (except for CPU access mode).
36
Memory Classes
State Analyzer
Keywords for the Display

AREA
Access area
STATE
CPU status
Keywords for the Analyzer Trigger Unit

General C166CBC Keywords for the Emulator Trigger Unit
Input Event
Meaning
BRKOUT
BYTE
Byte transfer
DATA
Data access
FETCH
Program access
Read
Read access
RESET
RSTOUT
Word
Word transfer
Write
Write access
For not CPU-specific keywords, see non-declarable input variables in ICE/FIRE Analyzer Trigger Unit
Programming Guide (analyzer_prog.pdf).
37
State Analyzer
Port Analyzer
Port Signals EGOLD

Name
Group
Description
CC01IO
CCIO
Signal CC01IO
CC02IO
CCIO
Signal CC02IO
CC06IO
CCIO
Signal CC06IO
CS0-
CS
Chip Select CS0-
CS1-
CS
Chip Select CS1-
CS2-
CS
Chip Select CS2-
CS3-
CS
Chip Select CS3-
CS4-
CS
Chip Select CS4-
KP0 .. KP9
KP
Signal KP0 .. KP9
BPDM1 .. BPDM2
MISC
Signal BPDM1 .. BPDM2
CC00IO
MISC
Signal CC00IO
CCIN
MISC
Signal CCIN
CCIO
MISC
Signal CCIO
CCIOSW
MISC
Signal CCIOSW
CCLK
MISC
Signal CCLK
CCRST
MISC
Signal CCRST
CCVZ-
MISC
Signal CCVZ-
CLKANA
MISC
Signal CLKANA
CLKOUT
MISC
Signal CLKOUT
CLKSXM
MISC
Signal CLKSXM
DACI
MISC
Signal DACI
DACQ
MISC
Signal DACQ
DSPOUT0 .. DSPOUT1
MISC
Signal DSPOUT0 .. DSPOUT1
GAIMCLK
MISC
Signal GAIMCLK
GAIMDATA
MISC
Signal GAIMDATA
GAIMRXON
MISC
Signal GAIMRXON
HLDA-
MISC
Signal HLDA-
MRST
MISC
Signal MRST
MTSR
MISC
Signal MTSR
PDOUT
MISC
Signal PDOUT
READY-
MISC
Signal READY-
RFSD
MISC
Signal RFSD
RSTOUT-
MISC
Signal RSTOUT-
RXDD
MISC
Signal RXDD
SSCCLK
MISC
Signal SSCCLK
SSCLK
MISC
Signal SSCLK
T5IN
MISC
Signal T5IN
TFSD
MISC
Signal TFSD
TXDD
MISC
Signal TXDD
VBIN
MISC
Signal VBIN
VBOUT
MISC
Signal VBOUT
VCLK
MISC
Signal VCLK
D08 .. D15
P0H
Port D08 .. D15
38
Port Analyzer
Name
Group
Description
RFCLK
RF
Signal RFCLK
RFDATA
RF
Signal RFDATA
RFSTR0 .. RFSTR5
RF
Signal RFSTR0 .. RFSTR5
RXD0 .. RXD1
RXTX
Signal RXD0 .. RXD1
TXD0 .. TXD1
RXTX
Signal TXD0 .. TXD1
BHE-
STR
Strobe BHE-
RD-
STR
Strobe RD-
WR-
STR
Strobe WR-
TOUT0 .. TOUT1
TOUT
Signal TOUT0 .. TOUT1
TOUT10 .. TOUT12
TOUT
TOUT2 .. TOUT9
TOUT
Name
Group
Description
CC00IO
CCIO
Signal CC00IO
CC01IO
CCIO
Signal CC01IO
CC02IO
CCIO
Signal CC02IO
CC06IO
CCIO
Signal CC06IO
CS0-
CS
Chip Select CS0-
CS1-
CS
Chip Select CS1-
CS2-
CS
Chip Select CS2-
CS3-
CS
Chip Select CS3-
CS4-
CS
Chip Select CS4-
KP0 .. KP9
KP
Signal KP0 .. KP9
CCIN
MISC
Signal CCIN
CCIO
MISC
Signal CCIO
CCIOSW
MISC
Signal CCIOSW
CCLK
MISC
Signal CCLK
CCRST
MISC
Signal CCRST
CCVZ-
MISC
Signal CCVZ-
CLKOUT
MISC
Signal CLKOUT
CLKSXM
MISC
Signal CLKSXM
DSPOUT0 .. DSPOUT1
MISC
Signal DSPOUT0 .. DSPOUT1
Port Signals EGOLDP
HLDA-
MISC
Signal HLDA-
MRST
MISC
Signal MRST
MTSR
MISC
Signal MTSR
PDOUT
MISC
Signal PDOUT
READY-
MISC
Signal READY-
RESETIN-
MISC
Signal RESETIN-
RFSD
MISC
Signal RFSD
RSTOUT-
MISC
Signal RSTOUT-
RTCOUT
MISC
Signal RTCOUT
RXDD
MISC
Signal RXDD
SCLK
MISC
Signal SCLK
SSCCLK
MISC
Signal SSCCLK
39
Port Analyzer
Name
Group
Description
TFSD
MISC
Signal TFSD
TXDD
MISC
Signal TXDD
VCXO2EN
MISC
Signal VCXO2EN
VCXOEN
MISC
Signal VCXOEN
D08 .. D15
P0H
Port D08 .. D15
RFCLK
RF
Signal RFCLK
RFDATA
RF
Signal RFDATA
RFSTR0 .. RFSTR4
RF
Signal RFSTR0 .. RFSTR4
RXD0 .. RXD1
RXTX
Signal RXD0 .. RXD1
TXD0 .. TXD1
RXTX
Signal TXD0 .. TXD1
BHE-
STR
Strobe BHE-
RD-
STR
Strobe RD-
WR-
STR
Strobe WR-
TOUT0 .. TOUT1
TOUT
TOUT10 .. TOUT12
TOUT
TOUT2 .. TOUT9
TOUT
Group
Description
Port Signals UTAH

Name
DCL
MISC
Signal DCL
DD
MISC
Signal DD
DMNS
MISC
Signal DMNS
DPLS
MISC
Signal DPLS
DU
MISC
Signal DU
FSC
MISC
Signal FSC
RSTOUT-
MISC
Signal RSTOUT-
P008 .. P015
P0H
Port P008 .. P015
P100 .. P115
P1
Port P100 .. P115
P200 .. P207
P2
Port P200 .. P207
P303
P3
Port P303
P305 .. P313
P3
Port P305 .. P313
P315
P3
Port P315
P400 .. P407
P4
Port P400 .. P407
P600 .. P607
P6
Port P600 .. P607
P700 .. P705
P7
Port P700 .. P705
BHE-
STR
Strobe BHE-
RD-
STR
Strobe RD-
WR-
STR
Strobe WR-
40
Port Analyzer
Technical Data
Mechanical Dimensions
Dimension
LA-9590
FIRE-PMB2850
41
Technical Data
Dimension
LA-9591
FIRE-PMB6850
LA-9592
FIRE-C165UTAH
42
Technical Data
Adaptions
CPU
Adaption
C161U
ET100-QF49
C165H
C165UTAH
ET144-QF63
43
Technical Data
Adapters
Socket CPU
Adapter
ET100-QF49
YA-1091 ET100-EYA-QF49
Emul. Adapter for YAMAICHI socket ET100-QF49
C161U
8
6
56
SIDE VIEW
66
18
14
TOP VIEW (all dimensions in mm)
44
Technical Data
Socket CPU
Adapter
ET144-QF63
YA-1111 ET144-EYA-QF63
C165H
C165UTAH
8
6
69
SIDE VIEW
69
17
18
TOP VIEW (all dimensions in mm)
45
Technical Data
Operation Voltage
This list contains information on probes available for other voltage ranges. Probes not noted here supply an
operation voltage range of 4.5 5.5 V.
CPU
Module
Adapter
Voltage Range
C161U
C165H
C165UTAH
PMB6850_E-GOLD+
3.0 .. 3.6 V
3.0 .. 3.6 V
3.0 .. 3.6 V
1.8 .. 2.2 V
Operation Frequency
Module
CPU
F-W010
F-W110
S-W010
S-W110
CHIP
C161U
C165H
C165UTAH
38.0
38.0
38.0
38.0+
38.0+
38.0+
27.5
27.5
27.5
38.0+
38.0+
38.0+
38.0
38.0
38.0
TRACE HEAD
RAM
46
Technical Data
Support
Probes
LA-9591
PMB6850_E-GOLD+ LAEGOLDP 1.8..2.2V
LA-9592
C161U
ET100-QF49 3.0..3.6V
C165H
ET144-QF63 3.0..3.6V
C165UTAH
ET144-QF63 3.0..3.6V
YES
YES
YES
YES YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
C161U
C165H
C165UTAH
PMB6850_E-GOLD+
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
Compilers
Language
Compiler
Company
Option
C166
ARM Germany GmbH
EOMF-166
Comment
47
Support
Language
Compiler
Company
Option
C
C
XC16X/ST10
GNU-GCC166
ELF/DWARF
DBX
C
C++
C166
GNU-CPP166
C++
CP166
Cosmic Software
HighTec EDV-Systeme
GmbH
TASKING
HighTec EDV-Systeme
GmbH
TASKING
Comment
IEEE
DBX
IEEE
Realtime Operation Systems

Name
Company
Comment
ARTX-166
CMX-RTX
Elektrobit tresos
Erika
Nucleus PLUS
osCAN
OSE Basic
OSE Epsilon
OSEK
ProOSEK
PXROS
RTX166/-tiny
RTXC 3.2
RTXC Quadros
Rubus OS
SDT-Cmicro
uC/OS-II
ARM Germany GmbH

CMX Systems Inc.
Elektrobit Automotive GmbH
Evidence
Mentor Graphics Corporation
Vector
Enea OSE Systems
Enea OSE Systems
Elektrobit Automotive GmbH
HighTec EDV-Systeme GmbH
ARM Germany GmbH
Quadros Systems Inc.
Quadros Systems Inc.
Articus Systems AB
IBM Corp.
Micrium Inc.
via ORTI
via ORTI
via ORTI
(OS166)
(OS166), 3.x
via ORTI
via ORTI
2.0 to 2.92
48
Support
3rd Party Tool Integrations

CPU
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
C166
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
SDT CMICRO
Host
Windows
Windows
Windows
Code Confidence Ltd
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
IBM Corp.
Windows
49
Support
Products
Product Information
OrderNo Code
Text
LA-9590
FIRE Emulator for PMB2850
FIRE-PMB2850
FIRE Emulator for EGOLD,

adaption to ADEGOLD,
requires FIRE-ARAM
LA-9591
FIRE-PMB6850
FIRE Emulator for EGOLD+,

adaption to ADEGOLDP,
requires FIRE-ARAM
LA-9592
FIRE Emulator for C165UTAH
FIRE-C165UTAH
FIRE Emulator for C165UTAH, C161UTAH, C165H,

adaption to ET144-QF63, ET100QF49,
requires FIRE-ARAM
Order Information
Order No.
Code
Text
LA-9590
LA-9591
LA-9592
FIRE-PMB2850
FIRE-PMB6850
FIRE-C165UTAH

FIRE Emulator for C165UTAH
Additional Options
TO-1250
ET100-ETO-QF49
TO-1255
ET100-ETO-SE
YA-1091
ET100-EYA-QF49
ET-1092
ET100-SET-QF49
TO-1251
ET100-STO-QF49
TO-1310
ET144-ETO-QF63
YA-1111
ET144-EYA-QF63
ET-1110
ET144-SET-QF63
TO-1311
ET144-STO-QF63
Emul. Adapter for T0 socket ET100-QF49

Emul. Adapter for T0 socket ET100-SE 0.4mm
Surface Mountable Adapter for ET100-QF49
Emul. Adapter TO-surface mount. ET100-QF49
Emul. Adapter for T0 socket ET144-QF63
Surface Mountable Adapter for ET144-QF63
Emul. Adapter TO-surface mount. ET144-QF63
50
Products

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FIRE Emulator for C166 Cell-Based-Core

TRACE32 Online Help

FIRE In-Circuit Emulator ...............................................................................................................

FIRE Target Guides ....................................................................................................................

FIRE Emulator for C166 Cell-Based-Core .............................................................................

Quick Start ............................................................................................................................

General SYStem Settings and Restrictions .......................................................................

Write operation mode

Write operation mode

Mask interrupts during assembler step

Mask interrupts during HLL step

FIRE Emulator for C166 Cell-Based-Core

On-circuit emulation reset

On-chip Trigger-Unit ............................................................................................................

Specific TrOnchip Commands ............................................................................................

Select address selector

Select bus cycle

Set data selector value

Set task selector value

Trigger Commands ..............................................................................................................

Define source for the external trigger pulse

Define the target for the incoming trigger

Exception Control ................................................................................................................

Breakpoint Realization Modes

Memory Classes ...................................................................................................................

State Analyzer .......................................................................................................................

Keywords for the Display

Keywords for the Analyzer Trigger Unit

General C166CBC Keywords for the Emulator Trigger Unit

FIRE Emulator for C166 Cell-Based-Core

Port Signals EGOLD

Port Signals EGOLDP

Port Signals UTAH

Technical Data ......................................................................................................................

Realtime Operation Systems

3rd Party Tool Integrations

1989-2016 Lauterbach GmbH

FIRE Emulator for C166 Cell-Based-Core

FIRE Emulator for C166 Cell-Based-Core

1989-2016 Lauterbach GmbH

FIRE Emulator for C166 Cell-Based-Core

Set cpu-type and -mode

Set system options

Select dualport mode (optional)

Set mapper (optional)

Select monitor base

Select frequency (optional)

Activate the emulator

Load application file (optional)

Set breakpoints (optional)

Stop application (optional)

1989-2016 Lauterbach GmbH

FIRE Emulator for C166 Cell-Based-Core

Here a typical example, how to set up the system:

Set cpu-type, bustype and -mode options

; switch the system down

Set system options

; Select type of DP access

Select dualport mode (optional)

; request: a dedicated bus request

; reset mapper (all external)

1989-2016 Lauterbach GmbH

FIRE Emulator for C166 Cell-Based-Core

Select monitor base address