Professional Documents
Culture Documents
Warning .................................................................................................................................
Troubleshooting ...................................................................................................................
10
Hang-Up
10
Dualport Errors
10
FAQ ........................................................................................................................................
11
Configuration ........................................................................................................................
13
Basics ....................................................................................................................................
14
Emulation Method
14
Emulation Modes
14
Dualport Access
15
18
18
SYStem.CPU
Processor type
18
SYStem.CPU
Operation mode
19
SYStem.Option V33
SYStem.Option IMASKASM
19
20
20
SYStem.Option IMASKHLL
20
21
21
SYStem.Option PLL
Onchip PLL
21
SYStem.Option MTU
21
SYStem.Option CMT
22
23
23
SYStem.Option PLL
Onchip PLL
23
SYStem.Option ATU
23
24
24
SYStem.Option ATU
24
SYStem.Option CMT
25
26
General Description
26
Address Selectors
26
Sequential Mode
27
Examples
27
View window
TrOnchip.RESet
29
29
Reset settings
29
TrOnchip.CONVert
Convert breakpoints
29
TrOnchip.A.Watch
30
TrOnchip.A.Break
Stop emulation
30
TrOnchip.A.CYcle
31
TrOnchip.A.Type
32
TrOnchip.A.Size
32
TrOnchip.A.Value
33
TrOnchip.SEQ
33
TrOnchip.RPE
34
34
35
TrOnchip.A.Count
Reset
35
36
37
NMI
38
39
Breakpoints ...........................................................................................................................
Breakpoint Realization Modes
40
40
42
42
43
43
44
44
44
44
45
45
46
1989-2016 Lauterbach GmbH
47
49
50
52
55
Mechanical Dimensions
55
Adaptions
61
Adapters
63
Operation Voltage
69
Operation Frequency
70
Support ..................................................................................................................................
71
Probes
71
Available Tools
72
Compiler Support
72
73
73
Products ................................................................................................................................
75
Product Information
75
Order Information
77
F::d.l
ddr/line
code
P:00010832 6303
545
P:00010834
P:00010836
546
P:00010838
P:0001083A
547
P:0001083C
P:0001083E
P:00010840
label
333C
7303
add
add
6203
323C
mov
add
3247
8D06
6743
cmp/gt
bt/s
mov
549
P:00010842 6123
F::r
T
_
S
_
I
F
Q
_
M
_
Tsk
R0
R1
R2
R3
R4
R5
R6
R7
GBR
VBR
MACH
MACL
mnemonic
mov
{
0
1
1
0
12
4006C0
0
12
0
0
1800000
2BCE
mov
R8
R9
R10
R11
R12
R13
R14
R15
PC
PR
SR
0
0
0
0
0
0
407FEC
407FEC
10834
107A2
0F0
r0,r3
comment
; return,primz
primz = i + i + 3;
r3,r3
; primz,primz
#3,r3
; #3,primz
k = i + primz;
r0,r2
; return,k
r3,r2
; primz,k
while ( k <= SIZE )
r4,r2
; r4,k
1084E
r4,r7
{
flags[ k ] = FALSE;
r2,r1
; k,r1
SP >00407FF4
+04 0001080C
+08 00010016
+0C 00000000
+10 00000000
+14 DEADDEAD
+18 00000000
+1C 00000000
+20 00000000
+24 00000000
+28 00000000
+2C 00000000
+30 00000000
F::v.w
flags = (1, 1, 1, 1, 1,
ast = (word = 0x0,
count = 12346,
left = 0x400710,
right = 0x0,
field1 = 1,
field2 = 2)
For general informations about the In-Circuit Debugger refer to the FIRE Users Guide (fire_user.pdf). All
general commands are described in IDE Reference Guide (ide_ref.pdf) and General Reference
Guide.
Warning
NOTE:
Do not connect or remove probe from target while target power is ON.
Power up:
Switch on emulator first, then target
Power down: Switch off target first, then emulator
Warning
Quick Start
Before debugging can be started, the emulator must be configured by software:
Ready to run setup files for most standard compilers can be found on the software CD in the directory ../
Demo/Sh7000/Compiler. All setup files are designed to run the emulator stand alone without target
hardware.
The following description should make the initial setup (to run the emulator together with the target
hardware) easier. It describes a typical setup with frequently used settings. It is recommended to use the
programming language PRACTICE to create a batch file, which includes all necessary setup commands.
PRACTICE files (*.cmm) can be created with the PRACTICE editor pedit (Command: PEDIT <file name>)
or with any other text editor.
A basic setup file includes the following parts:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Start application
10.
Quick Start
2.
3.
4.
;
;
;
;
;
;
;
Quick Start
5.
6.
7.
8.
9.
;
;
;
;
Start application
Application can be started with giving a break address. For example go main starts the application
and stops at symbol main.
go
; run application
Quick Start
10.
It is recommended to check the following chapters for all questions regarding the correct setup:
Configuration
Troubleshooting
Quick Start
Troubleshooting
Hang-Up
If you are not able to stop the emulation, there could be some typical reasons:
Active target-reset
Dualport Errors
Dual-Port Busy
Request Mode: The bus is not released by the cpu within the
selected time with the sys.TimeReq option.
AUD Mode: This error occurs, if you try to dump a memory area
which cant be seen by the cpu (for example, any external memory
areas in single-chip mode).
10
Troubleshooting
FAQ
Debugging via
VPN
SH-2
Dualport
Access to Onchip RAM
SH-2
Dump of
External
Memory in
Mode ROM
11
FAQ
SH-2
Illegal-SlotInstruction
Exception
12
FAQ
Configuration
There is no special hardware configuration necessary for the SH2. The configuration of the used derivative
and cpu-mode is done via the SYSTEM commands by software.
13
Configuration
Basics
Emulation Method
The FIRE Emulator uses a bondout versions of the SH2 CPUs.
NOTE: The bondout chip replaces the target cpu, i.e. the target cpu must be removed during emulation!
Emulation Modes
F::sys
system
Down
Up
RESet
Mode
RESet
AloneInt
AloneExt
EmulInt
EmulExt
Access
Request
Denied
TimeReq
1.000ms
CPU
SH7040
Option
V33
IMASKASM
IMASKHLL
PLL
1
2
4
Option
MTU0
MTU1
MTU2
MTU3
MTU4
CMT0
CMT1
CPU
EXT8
EXT16
EXT32
ROM
SINGLE
The emulator can operate in 5 modes. The modes are selected by the SYStem.Mode command.
Format:
SYStem.Mode <mode>
<mode>:
Reset
AloneInternal
AloneExternal
EmulInternal
EmulExternal
14
Basics
Reset
CPU is in reset.
Alone Internal
CPU is running with internal clock. Bus strobe signals (RD, WR, CS, RAS, CAS)
are disabled. This mode is used for 'standalone' operation.
Alone External
CPU is running with external clock. Bus strobe signals are disabled.
Emulation
Internal
CPU is running with internal clock. Bus strobe signals are enabled.
Emulation
External
CPU is running with external clock. Bus strobe signals are enabled.
In active mode, the power of the target is sensed and by switching down the target the emulator changes to
RESET mode. The probe is not supplied by the target power. When running without target, the target
voltage is simulated by an internal pull-up resistor.
Dualport Access
Format:
SYStem.MemAccess <option>
<option>:
Request
AUD
Denied
Request
The CPU bus access is stopped by a dedicated bondout bus-request signal for
performing a dualport access.
AUD
The AUD interface of the chip is used in monitor -mode for the dual-port
accesses. In this mode, you can even access target memories and onchip
peripherals while the application program is running.
If request or denied is selected, then the AUD interface can be used by the
target hardware.
Denied
Dualport allows access to emulation RAM and onchip ROM/FLASH, while emulation is running. This is
necessary to display variables, set breakpoints or display flag listings while the emulation is running.
Dualport access is only possible on the emulators internal RAM and not on target RAM.
NOTE:There is no dualport access to the onchip RAM of the cpu in request-mode, because this RAM is
physically internal at the bondout cpu.
1989-2016 Lauterbach GmbH
15
Basics
Format:
SYStem.CpuAccess <option>
<option>:
Enable
Denied
Enable
Denied
The emulator uses a two stage strategy to realize the best possible dualport access method:
If MemAccess is set to Request, the emulation controller tries a bus arbitration access as dualport cycle.
This is possible if memory is mapped to internal and on read cycles to shadow memory. Shadow memory
means, that memory is mapped in the emulator (map.ram), but the area is mapped external (map.extern).
On access to external mapped memory and write access to shadow memory the dualport is executed as a
spot point if CpuAccess is enabled. Dualport on access to external mapped memory and write access to
shadow memory is disabled if CpuAccess is disabled.
If MemAccess is set to AUD, the emulation controller uses the AUD interface of the CPU to realize the
dualport cycle. The advantage of this method is that all memories, independent on the mapping, can be
used. CpuAccess switch is ignored if MemAccess is set to AUD.
If MemAccess is set to Denied and CpuAccess is enabled, the emulation controller uses a spot point to
realize the dualport cycle. If MemAccess is set to Denied and CpuAccess is disabled, dualport access is not
possible.
The following table shows how the dualport is realized depending on the used system setting:
Mem
Access
Cpu
Access
Read
Map
Int.
Write
Map
Int.
Read
Shado
w
Write
Shado
w
Read
Map
Ext.
Write
Map
Ext.
Request
Enable
request
request
request
spot
spot
spot
Request
Denied
request
request
request
AUD
Enable
aud
aud
aud
aud
aud
aud
AUD
Denied
aud
aud
aud
aud
aud
aud
Denied
Enable
spot
spot
spot
spot
spot
spot
Denied
Denied
16
Basics
request: The bus arbitration interface of the CPU is used for dualport access. Application performance is
only slightly influenced.
aud: The AUD interface of the CPU is used for dualport access. Application performance is more
influenced than with request mode.
spot: The emulation is breaked, memory access is done via CPU, emulation is continued. Application
performance is most influenced with this method.
17
Basics
General Restrictions
Onchip RAM
The CPUs onchip RAM is physically internal at the bondout chip. This
means that there is no dualport access available to this RAM. Except
for SH7055 there is no Break- and Flag-RAM parallel to the onchip
RAM, so that there is no flag information available for it. The address
selectors for the emulator trigger-unit and the read and write
breakpoints are realized with the four channel onchip trigger-unit of the
bondout chip.
Interrupt requests
during the emulation
is stopped
Pending interrupts
during single-step
SYStem.CPU
Processor type
Format:
SYStem.CPU <type>
<type>:
SH7011|SH7016|SH7017
SH7014
SH7040|SH7042|SH7044
SH7041|SH7043|SH7045
SH7050
SH7051
SH7055
18
SYStem.CPU
Operation mode
Format:
SYStem.CPU <mode>
<mode>:
EXT8
EXT16
EXT32
ROM
SINGLE
This option specifies operation mode of the cpu, which is normally defined with the MD0 and MD1 pins of
the cpu. But, the values of this pins in the target are not responsible for the operation mode, so that the pin
levels can differ from the emulator setting.
EXT8
CS0 is an external memory area with 8-bit bus width. The onchip ROM is
disabled.
EXT16
CS0 is an external memory area with 16-bit bus width. The onchip ROM is
disabled.
EXT32
CS0 is an external memory area with 32-bit bus width. The onchip ROM is
disabled.
ROM
SINGLE
SYStem.Option V33
Format:
The emulator has a detection logic to detect a target power fail. This option must be set to on, if a 3.3 V
target is used.
19
SYStem.Option IMASKASM
Format:
If enabled, the interrupt mask bits of the cpu will be set during assembler single-step operations. The
interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are
restored to the value before the step.
SYStem.Option IMASKHLL
Format:
If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
the value before the step.
NOTE: By changing the status register through target software, this option can affect the flow of the
target program. Accesses to the interrupt-mask bits will see the wrong values.
20
SH7011
The Input-Pins IRQ0..7 and WAIT have 22K pull-up resistors in the
emulator to avoid that external interrupts are triggered or external
bus-cycles wont be terminated in stand-alone mode.
SYStem.Option PLL
Format:
Onchip PLL
SYStem.Option PLL 1 | 2 | 4
This option specifies the multiplication factor of the onchip PLL, which is normally defined with the MD2 and
MD3 pins of the cpu. But, the values of this pins in the target are not responsible for the multiplication factor,
so that the pin levels can differ from the emulator setting.
SYStem.Option MTU
Format:
<channel>:
0|1|2|3|4
This option controls the timers of the CPUs Multifunction Timer Pulse Unit for each channel independently.
Normally, the timers continue running if the emulation is stopped. If the option is now switched on, the
corresponding timer will stop after entering the break mode and will start running again before the emulation
is started. This is done by manipulating the timer start register by the emulators background monitor
program. Since there have to be done some important actions in the monitor before the timer control, the
starting and stopping cant be synchronous to the emulators go and break.
21
SYStem.Option CMT
Format:
<channel>:
0|1
This option controls the timers of the CPUs Compare Match Timer Unit for each channel independently.
Normally, the timers continue running if the emulation is stopped. If the option is now switched on, the
corresponding timer will stop after entering the break mode and will start running again before the emulation
is started. This is done by manipulating the timer start register by the emulators background monitor
program. Since there have to be done some important actions in the monitor before the timer control, the
starting and stopping cant be synchronous to the emulators go and break.
22
SYStem.Option PLL
Format:
Onchip PLL
SYStem.Option PLL 1 | 2 | 4
This option specifies the multiplication factor of the onchip PLL, which is normally defined with the MD2 and
MD3 pins of the cpu. But, the values of this pins in the target are not responsible for the multiplication factor,
so that the pin levels can differ from the emulator setting.
SYStem.Option ATU
Format:
<channel>:
0|1|2|3|4|5|6|7|8|9
This option controls the timers of the CPUs Advanced Timer Unit for each channel independently.
Normally, the timers continue running if the emulation is stopped. If the option is now switched on, the
corresponding timer will stop after entering the break mode and will start running again before the emulation
is started. This is done by manipulating the timer start register by the emulators background monitor
program. Since there have to be done some important actions in the monitor before the timer control, the
starting and stopping cant be synchronous to the emulators go and break.
23
SYStem.Option ATU
Format:
<channel>:
0 | 1A | 1B | 2A | 2B | 3 | 4 | 5 | 6A | 6B | 6C | 6D | 7A | 7B | 7C | 7D | 10 | 11
This option controls the timers of the CPUs Advanced Timer Unit for each channel independently.
Normally, the timers continue running if the emulation is stopped. If the option is now switched on, the
corresponding timer will stop after entering the break mode and will start running again before the emulation
is started. This is done by manipulating the timer start register by the emulators background monitor
program. Since there have to be done some important actions in the monitor before the timer control, the
starting and stopping cant be synchronous to the emulators go and break.
24
SYStem.Option CMT
Format:
<channel>:
0|1
This option controls the timers of the CPUs Compare Match Timer Unit for each channel independently.
Normally, the timers continue running if the emulation is stopped. If the option is now switched on, the
corresponding timer will stop after entering the break mode and will start running again before the emulation
is started. This is done by manipulating the timer start register by the emulators background monitor
program. Since there have to be done some important actions in the monitor before the timer control, the
starting and stopping cant be synchronous to the emulators go and break.
25
General Description
The onchip trigger-unit consists of four channels (A to D), which can work independently or can be
combined.The address and data values, and the bus cycle type, the bus master type and the operand
size can be set for each channel. There are two output events: A hardware signal can be generated and
the emulation can be stopped if a condition has matched. Furthermore is a sequential mode available.
Address Selectors
The address values for the trigger channels are set with the asynchronous breakpoints. There is a fixed
connection between the breakpoint types and the channels:
Example: Break.Set 400000 /Alpha /Onchip sets the address of channel A to 0x400000. You mustnt set
the option Onchip, if you have selected the Watch or Break option for the corresponing channel. If you
then open a Break.List window, then you can see the breakpoint marked as on-chip.
On-chip Breakpoints can also be set as a range. Then there are two channels used for one range: Channels
A or C are for the start address and channels B or D for the end address, e.g. Break.Set 1000--2000 /Charly
/Onchip sets an address range from 0x1000 to 0x2000 with the channels A and B. The output events must
be set in channel A for an AB-range and in channel C for a CD-range.
26
Sequential Mode
The onchip trigger-unit can also be used in a sequential mode. There are three possibilities:
If the conditions have matched sequentially, then the output event occurs, but this event must be set in all
participating channels (e.g. set A.Break, B.Break and C.Break if you want to stop the emulation after a C > B
> A sequence).
A reset pointer address can be defined with an Echo breakpoint to reset a sequence to the start event.
The reset is initialized when the pointer address is passed.
There is a repeat counter available. This value defines the number of times the sequence must be passed,
before the output event becomes active. This counter works also with channel A when it is used
independently.
Examples
Assume that there is a byte variable called 'flag', and you want to stop the emulation if the value 0x59 is
written to the variable.
TrOnchip.A.Break On
27
Assume that there is a byte variable called 'flag' in the onchip RAM, and you want to mark only read cycles to
this variable.
TrOnchip.A.Watch On
;
;
;
;
mark.a if bta
s.e
;
;
;
;
;
start:
goto level1 if ab
level1:
s.e
goto start if bb
NOTE: Analyzer trigger signals (BTA, BTB, BTC, BTD) are delayed one or two bus cycles. This means in the
previous example, that the mark in the analyzer.list will be placed one or two bus cycles after the onchip
trigger-unit match. Therefore analyzer programming files should not use sample.enable if bta.
28
TrOnchip.view
Format:
View window
TrOnchip.view
TrOnchip.RESet
Format:
Reset settings
TrOnchip.RESet
TrOnchip.CONVert
Format:
Convert breakpoints
The hardware breakpoints of the SH can only cover specific ranges. When enabled (default) the on-chip
breakpopints are automatically converted from a range to a single address if required. If the switch is off, the
system will only accept breakpoints which exactly fit to the on-chip breakpopint hardware.
29
TrOnchip.A.Watch
Format:
Activates a hardware output signal, if a condition has matched for the corresponding channel. It can be used
to program the emulator trigger unit with special keywords. Furthermore, a condition match can be seen in
the analyzer.list /all window under the corresponding keywords.
NOTE:
If the Watch option is on, then an asynchronous hardware breakpoint is automatically set as onchip.
The hardware output signal becomes active one or two bus cycles after the trigger condition has
matched, so you wont see the requested bus cycle at a selective trace. But if you use the
analyzer option PreTrace, then you can find the requested bus cycle in every traced block.
TrOnchip.A.Break
Format:
Stop emulation
Stops the emulation, if a condition has matched for the corresponding channel.
30
TrOnchip.A.CYcle
Format:
TrOnchip.A.CYcle <cycle>
TrOnchip.B.CYcle <cycle>
TrOnchip.C.CYcle <cycle>
TrOnchip.D.CYcle <cycle>
<cycle>:
ANY
Read
Write
Access
Fetch
Read
Write
Access
Fetch
31
TrOnchip.A.Type
Format:
TrOnchip.A.Type <type>
TrOnchip.B.Type <type>
TrOnchip.C.Type <type>
TrOnchip.D.Type <type>
<type>:
ANY
CPU
DMA
CPU
DMA
TrOnchip.A.Size
Format:
TrOnchip.A.Size <size>
TrOnchip.B.Size <size>
TrOnchip.C.Size <size>
TrOnchip.D.Size <size>
<size>:
ANY
Byte
Word
Long
Byte
Word
Long
32
TrOnchip.A.Value
Format:
Defines the four data selectors as hex or binary mask (x means don't care).
NOTE: If you want to trigger on a certain byte access, the upper 24 bits must be set as dont care (e.g.
0xxxxxx55). If you want to trigger on a certain word access, the upper 16 bits must be set as dont care
(e.g. 0xxxxAA55). The placement of the data within the word depends on the bus width of the access. An
easier way to use data values is to supply the data and access width with the Break.Set command.
TrOnchip.SEQ
Format:
TrOnchip.SEQ <mode>
<mode>:
OFF
BA
CBA
DCBA
BA
CBA
DCBA
33
TrOnchip.RPE
Format:
Sets a reset pointer for a sequential triggering. The Echo Breakpoint is used to set the address of the reset
pointer.
NOTE: If this option is on, the an Echo breakpoint is automatically set as the onchip reset pointer.
TrOnchip.A.Count
Format:
TrOnchip.A.Count <value>
Sets a compare match counter for channel A or for a trigger sequence. This means, that the trigger result
becomes active, when the condition has matched for <value> times, e.g. the application stops after
repeating C > B > A for five times.
The maximum <value> is 65536 (216).
34
Exception Control
F::x
exception
OFF
ON
RESet
Delay
OFF
Activate
OFF
RESET
MRESET
NMI
Enable
OFF
ON
RESET
MRESET
NMI
BRQ
Pulse
OFF
RESET
MRESET
NMI
Pulse
Single
Width
1.000us
PERiod
OFF
ON
0.000
NMIPOL
+
The exception control system depends on the used cpu family (SH701x/704x or SH705x). The window
shown here is for the SH701x/704x.
Reset
Vcc
X.Enable
&
Run
22K
RESET
(Target)
RESET
(CPU)
22R
X.Activate
or
X.Pulse
Format:
Format:
35
Exception Control
22K
X.Enable
MRESET
(Target)
MRESET
(CPU)
22R
X.Activate
or
X.Pulse
Format:
Format:
36
Exception Control
22K
X.Enable
HSTBY
(Target)
HSTBY
(CPU)
22R
X.Activate
or
X.Pulse
Format:
Format:
37
Exception Control
NMI
Vcc
22K
X.Enable
X.NMIPOL
NMI
(Target)
NMI
(CPU)
22R
X.Activate
or
X.Pulse
10K
GND
Format:
Format:
Format:
eXception.NMIPOL [+ | -]
Selects the NMI edge. Set it corresponding to the bit NMIE in the Interrupt Control Register ICR of the CPU.
Selects the falling edge and the 22K pull-up resistor is active (see drawing above).
+
Selects the rising edge and the 10K pull-down resistor is active (see drawing above).
38
Exception Control
39
Exception Control
Breakpoints
For a basic description of the breakpoint system please refer to FIRE Users Guide.
Synchronous Breakpoints:
The user application code is patched with a special break-instruction of the
bondout CPU (opcode 0x0) before jumping into the user program. After
executing this instruction, the CPU stops the user program and jumps into the
emulator debug monitor.
Asynchronous Breakpoints:
These breakpoints are used as address selectors for the trigger unit (see FIRE
Users Guide).
Hardware
Breakpoints
Synchronous Breakpoints:
The user application is stopped before the instruction is executed. For this, the
bondout break opcode is switched to the CPU data-bus instead of the user
application opcode via hardware. This type of breakpoint is useful if you would
like to set a breakpoint in a target memory where no code can be patched (e.g.
EPROM or Flash).
NOTE: This breakpoint type doesnt work in the onchip ROM and RAM area.
There are only synchronous software breakpoints available.
Asynchronous Breakpoints: See FIRE Users Guide).
Onchip
Breakpoints
The bondout CPU has an onchip trigger-unit with four independent channels.
Synchronous Breakpoints:
They can be used if you would like to set a breakpoint in a target memory where
no code can be patched (e.g. EPROM or Flash).
Asynchronous Breakpoints:
The information, that a breakpoint has occurred is switched from the bondout
break controller to the trigger unit, so that the trigger unit for example can start
the analyzer.
NOTE: Since there is no breakpoint RAM in parallel to the CPUs onchip RAM
(except SH7055), the onchip trigger-unit is always used for asynchronous
breakpoints to the on-chip RAM.
40
Breakpoints
The following table shows realization of the logical breakpoint types in auto-mode.
Breakpoint
Type
Program
Software
HLL
Software
Onchip (If the address is mapped as ReadOnly)
Stepmode (If HLL-Line is too complex)
Spot
Software
Onchip (If the address is mapped as ReadOnly)
Read, Write
Onchip
Alpha, Beta,
Charly, Delta,
Echo
Hardware
Onchip (CPUs onchip RAM area except SH7055)
Onchip (If option Watch, Break or RPE is set in the onchip trigger-unit)
41
Breakpoints
Memory Classes
Overview
Access Class
Description
Data
Program
ED
Dualport Data
EP
Dualport Program
42
Memory Classes
State Analyzer
Access area
STATE
CPU status
ASEIF
ASEHLIR
ASELLIR
ASEHEXP
ASEBTA
ASEBTB
ASEBTC
ASEBTD
43
State Analyzer
Meaning
Analyzer
hardware
FEC
BTA
BTB
BTC
BTD
DATA
Data access
FETCH
Prefetch cycle
Read
Read access
Write
Write access
Meaning
Analyzer
hardware
FEC
none
Meaning
Analyzer
hardware
FEC
none
For not CPU-specific keywords, see non-declarable input variables in ICE/FIRE Analyzer Trigger Unit
Programming Guide (analyzer_prog.pdf).
44
State Analyzer
Port Analyzer
Group
Description
A01 .. A21
ADDR
AN0 .. AN6
AN
D00 .. D15
DATA
PA00 .. PA15
PA
2*SH7055
Signal 2*SH7055
PA18 .. PA19
PA
PB00 .. PB15
PB
PC00 .. PC04
PC
PD00 .. PD13
PD
PE00
PE
Port PE00
PE00 .. PE02
PE
PE02 .. PE04
PE
PE04 .. PE05
PE
PE05 .. PE06
PE
PE06 .. PE07
PE
PE07 .. PE12
PE
PE12 .. PE13
PE
PE13 .. PE14
PE
PE14 .. PE15
PE
PF00 .. PF15
PF
PG00 .. PG03
PG
PH00 .. PH15
PH
PJ00 .. PJ15
PJ
PK00 .. PK15
PK
PL00 .. PL13
PL
RXD
SCI
Receive Data
TXD
SCI
Transmit Data
CK
STROBES
System Clock
CS0-
STROBES
Chip Select 0
CS1-
STROBES
Chip Select 1
RD-
STROBES
Read
WAIT-
STROBES
Wait
WRH-
STROBES
Upper Write
WRL-
STROBES
Lower Write
45
Port Analyzer
Group
Description
ADDR
2*SH7055
A00 .. A17
Signal 2*SH7055
D00 .. D15
DATA
PA00
PA
Port PA00
PA00 .. PA01
PA
PA01 .. PA02
PA
PA02 .. PA03
PA
PA03 .. PA04
PA
PA04 .. PA05
PA
PA05 .. PA06
PA
PA06 .. PA07
PA
PA07 .. PA08
PA
PA08 .. PA09
PA
PA09 .. PA15
PA
PA15
PA
Port PA15
PB00 .. PB02
PB
PB02 .. PB03
PB
PB03 .. PB04
PB
PB04 .. PB05
PB
PB05 .. PB06
PB
PB06 .. PB07
PB
PB07 .. PB08
PB
PB08 .. PB09
PB
PB09 .. PB15
PB
PC00 .. PC04
PC
PD00 .. PD13
PD
PE00
PE
Port PE00
PE00 .. PE01
PE
PE01 .. PE02
PE
PE02 .. PE03
PE
PE03 .. PE04
PE
PE04 .. PE05
PE
PE05 .. PE06
PE
PE06 .. PE07
PE
PE07 .. PE08
PE
PE08 .. PE09
PE
PE09 .. PE10
PE
PE10 .. PE11
PE
PE11 .. PE12
PE
PE12 .. PE13
PE
PE13 .. PE14
PE
PE14 .. PE15
PE
PE15
PE
Port PE15
PF0
PF
Port PF0
PF00 .. PF09
PF
PF1
PF
Port PF1
PF10 .. PF15
PF
PF2 .. PF7
PF
PG00 .. PG03
PG
46
Port Analyzer
Name
Group
Description
PH00 .. PH15
PH
PJ00 .. PJ15
PJ
PK00 .. PK15
PK
PL00 .. PL13
PL
CS0-
STROBES
Chip Select 0
CS1-
STROBES
Chip Select 1
RD-
STROBES
Read
WRH-
STROBES
WRL-
STROBES
Group
Description
PA00
PA
Port PA00
PA00 .. PA01
PA
PA01 .. PA02
PA
PA02 .. PA03
PA
PA03 .. PA04
PA
PA04 .. PA05
PA
PA05 .. PA06
PA
PA06 .. PA07
PA
PA07 .. PA08
PA
PA08 .. PA09
PA
PA09 .. PA10
PA
PA10 .. PA11
PA
PA11 .. PA12
PA
PA12 .. PA13
PA
PA13 .. PA14
PA
PA14 .. PA15
PA
PA15
PA
Port PA15
2*SH7055
Signal 2*SH7055
PB00
PB
Port PB00
PB00 .. PB01
PB
PB01 .. PB02
PB
PB02 .. PB03
PB
PB03 .. PB04
PB
PB04 .. PB05
PB
PB05 .. PB06
PB
PB06 .. PB07
PB
PB07 .. PB08
PB
PB08 .. PB09
PB
PB09 .. PB15
PB
PC00
PC
Port PC00
PC00 .. PC01
PC
PC01 .. PC02
PC
PC02 .. PC03
PC
PC03 .. PC04
PC
47
Port Analyzer
Name
Group
Description
PC04 .. PC15
PC
PD00
PD
Port PD00
PD00 .. PD01
PD
PD01 .. PD02
PD
PD02 .. PD03
PD
PD03 .. PD04
PD
PD04 .. PD05
PD
PD05 .. PD06
PD
PD06 .. PD07
PD
PD07 .. PD08
PD
PD08 .. PD09
PD
PD09 .. PD10
PD
PD10 .. PD11
PD
PD11 .. PD12
PD
PD12 .. PD13
PD
PD13 .. PD15
PD
PE00
PE
Port PE00
PE00 .. PE01
PE
PE01 .. PE02
PE
PE02 .. PE03
PE
PE03 .. PE04
PE
PE04 .. PE05
PE
PE05 .. PE06
PE
PE06 .. PE07
PE
PE07 .. PE08
PE
PE08 .. PE09
PE
PE09 .. PE10
PE
PE10 .. PE11
PE
PE11 .. PE12
PE
PE12 .. PE13
PE
PE13 .. PE14
PE
PE14 .. PE15
PE
PE15
PE
Port PE15
PF0
PF
Port PF0
PF00 .. PF09
PF
PF1
PF
Port PF1
PF10 .. PF15
PF
PF2 .. PF7
PF
PG00 .. PG03
PG
PH00 .. PH15
PH
PJ00 .. PJ15
PJ
PK00 .. PK15
PK
PL00 .. PL13
PL
48
Port Analyzer
Group
Description
PA00
PA
Port PA00
PA00 .. PA01
PA
PA01 .. PA02
PA
PA02 .. PA03
PA
PA03 .. PA04
PA
PA04 .. PA05
PA
PA05 .. PA06
PA
PA06 .. PA07
PA
PA07 .. PA08
PA
PA08 .. PA09
PA
PA09 .. PA10
PA
PA10 .. PA11
PA
PA11 .. PA12
PA
PA12 .. PA13
PA
PA13 .. PA14
PA
PA14 .. PA15
PA
PA15
PA
Port PA15
2*SH7055
Signal 2*SH7055
PB00
PB
Port PB00
PB00 .. PB01
PB
PB01 .. PB02
PB
PB02 .. PB03
PB
PB03 .. PB04
PB
PB04 .. PB05
PB
PB05 .. PB06
PB
PB06 .. PB07
PB
PB07 .. PB08
PB
PB08 .. PB09
PB
PB09 .. PB15
PB
PC00
PC
Port PC00
PC00 .. PC01
PC
PC01 .. PC02
PC
PC02 .. PC03
PC
PC03 .. PC04
PC
PC04 .. PC15
PC
PD00
PD
Port PD00
PD00 .. PD01
PD
PD01 .. PD02
PD
PD02 .. PD03
PD
PD03 .. PD04
PD
PD04 .. PD05
PD
PD05 .. PD06
PD
PD06 .. PD07
PD
PD07 .. PD08
PD
PD08 .. PD09
PD
PD09 .. PD10
PD
PD10 .. PD11
PD
PD11 .. PD12
PD
PD12 .. PD13
PD
49
Port Analyzer
Name
Group
Description
PD13 .. PD15
PD
PE00
PE
Port PE00
PE00 .. PE01
PE
PE01 .. PE02
PE
PE02 .. PE03
PE
PE03 .. PE04
PE
PE04 .. PE05
PE
PE05 .. PE06
PE
PE06 .. PE07
PE
PE07 .. PE08
PE
PE08 .. PE09
PE
PE09 .. PE10
PE
PE10 .. PE11
PE
PE11 .. PE12
PE
PE12 .. PE13
PE
PE13 .. PE14
PE
PE14 .. PE15
PE
PE15
PE
Port PE15
PF0
PF
Port PF0
PF00 .. PF09
PF
PF1
PF
Port PF1
PF10 .. PF15
PF
PF2 .. PF7
PF
PG00 .. PG03
PG
PH00 .. PH15
PH
PJ00 .. PJ15
PJ
PK00 .. PK15
PK
PL00 .. PL13
PL
Group
Description
PA00
PA
Port PA00
PA00 .. PA01
PA
PA01 .. PA02
PA
PA02 .. PA03
PA
PA03 .. PA04
PA
PA04 .. PA05
PA
PA05 .. PA06
PA
PA06 .. PA07
PA
PA07 .. PA08
PA
PA08 .. PA09
PA
PA09 .. PA10
PA
PA10 .. PA11
PA
PA11 .. PA12
PA
PA12 .. PA13
PA
2*SH7055
Signal 2*SH7055
50
Port Analyzer
Name
Group
Description
PA13 .. PA14
PA
PA14 .. PA15
PA
PA15 .. PA23
PA
PB00
PB
Port PB00
PB00 .. PB01
PB
PB01 .. PB02
PB
PB02 .. PB03
PB
PB03 .. PB04
PB
PB04 .. PB05
PB
PB05 .. PB06
PB
PB06 .. PB07
PB
PB07 .. PB08
PB
PB08 .. PB09
PB
PB09 .. PB15
PB
PC00
PC
Port PC00
PC00 .. PC01
PC
PC01 .. PC02
PC
PC02 .. PC03
PC
PC03 .. PC04
PC
PC04 .. PC15
PC
PD00
PD
Port PD00
PD00 .. PD01
PD
PD01 .. PD02
PD
PD02 .. PD03
PD
PD03 .. PD04
PD
PD04 .. PD05
PD
PD05 .. PD06
PD
PD06 .. PD07
PD
PD07 .. PD08
PD
PD08 .. PD09
PD
PD09 .. PD10
PD
PD10 .. PD11
PD
PD11 .. PD12
PD
PD12 .. PD13
PD
PD13 .. PD31
PD
PE00
PE
Port PE00
PE00 .. PE01
PE
PE01 .. PE02
PE
PE02 .. PE03
PE
PE03 .. PE04
PE
PE04 .. PE05
PE
PE05 .. PE06
PE
PE06 .. PE07
PE
PE07 .. PE08
PE
PE08 .. PE09
PE
PE09 .. PE10
PE
PE10 .. PE11
PE
PE11 .. PE12
PE
PE12 .. PE13
PE
PE13 .. PE14
PE
PE14 .. PE15
PE
51
Port Analyzer
Name
Group
Description
PE15
PE
Port PE15
PF0
PF
Port PF0
PF00 .. PF09
PF
PF1
PF
Port PF1
PF10 .. PF15
PF
PF2 .. PF7
PF
PG00 .. PG03
PG
PH00 .. PH15
PH
PJ00 .. PJ15
PJ
PK00 .. PK15
PK
PL00 .. PL13
PL
Group
Description
PA00
PA
Port PA00
PA00 .. PA01
PA
PA01 .. PA02
PA
PA02 .. PA03
PA
PA03 .. PA04
PA
PA04 .. PA05
PA
PA05 .. PA06
PA
PA06 .. PA07
PA
PA07 .. PA08
PA
PA08 .. PA09
PA
PA09 .. PA10
PA
PA10 .. PA11
PA
PA11 .. PA12
PA
PA12 .. PA13
PA
PA13 .. PA14
PA
PA14 .. PA15
PA
PA15
PA
Port PA15
2*SH7055
Signal 2*SH7055
PB00
PB
Port PB00
PB00 .. PB01
PB
PB01 .. PB02
PB
PB02 .. PB03
PB
PB03 .. PB04
PB
PB04 .. PB05
PB
PB05 .. PB06
PB
PB06 .. PB07
PB
PB07 .. PB08
PB
PB08 .. PB09
PB
PB09 .. PB10
PB
PB10 .. PB11
PB
PB11 .. PB15
PB
PC00
PC
Port PC00
52
Port Analyzer
Name
Group
Description
PC00 .. PC01
PC
PC01 .. PC02
PC
PC02 .. PC03
PC
PC03 .. PC04
PC
PC04 .. PC14
PC
PD00
PD
Port PD00
PD00 .. PD01
PD
PD01 .. PD02
PD
PD02 .. PD03
PD
PD03 .. PD04
PD
PD04 .. PD05
PD
PD05 .. PD06
PD
PD06 .. PD07
PD
PD07 .. PD08
PD
PD08 .. PD09
PD
PD09 .. PD10
PD
PD10 .. PD11
PD
PD11 .. PD12
PD
PD12 .. PD13
PD
PD13 .. PD15
PD
PE00
PE
Port PE00
PE00 .. PE01
PE
PE01 .. PE02
PE
PE02 .. PE03
PE
PE03 .. PE04
PE
PE04 .. PE05
PE
PE05 .. PE06
PE
PE06 .. PE07
PE
PE07 .. PE08
PE
PE08 .. PE09
PE
PE09 .. PE10
PE
PE10 .. PE11
PE
PE11 .. PE12
PE
PE12 .. PE13
PE
PE13 .. PE14
PE
PE14 .. PE15
PE
PF00
PF
Port PF00
PF00 .. PF01
PF
PF01 .. PF02
PF
PF02 .. PF03
PF
PF03 .. PF04
PF
PF04 .. PF05
PF
PF05 .. PF06
PF
PF06 .. PF07
PF
PF07 .. PF08
PF
PF08 .. PF09
PF
PF09 .. PF10
PF
PF10 .. PF11
PF
PF11 .. PF15
PF
PG00
PG
Port PG00
PG00 .. PG01
PG
53
Port Analyzer
Name
Group
Description
PG01 .. PG02
PG
PG02 .. PG03
PG
PG03 .. PG15
PG
PH00
PH
Port PH00
PH00 .. PH01
PH
PH01 .. PH02
PH
PH02 .. PH03
PH
PH03 .. PH04
PH
PH04 .. PH05
PH
PH05 .. PH06
PH
PH06 .. PH07
PH
PH07 .. PH08
PH
PH08 .. PH09
PH
PH09 .. PH10
PH
PH10 .. PH11
PH
PH11 .. PH12
PH
PH12 .. PH13
PH
PH13 .. PH14
PH
PH14 .. PH15
PH
PH15
PH
Port PH15
PJ00 .. PJ15
PJ
PK00 .. PK15
PK
PL00 .. PL13
PL
54
Port Analyzer
Technical Data
Mechanical Dimensions
Dimension
LA-9621
FIRE-M-SH7055
55
Technical Data
Dimension
LA-9562
FIRE-M-SH7040-32
LA-9565
FIRE-M-SH7014
56
Technical Data
Dimension
LA-9563
FIRE-M-SH7050
LA-9564
FIRE-M-SH7051
57
Technical Data
Dimension
LA-9566
FIRE-M-SH7017
58
Technical Data
Dimension
LA-9561
FIRE-M-SH7040-16
Front
14
6
160
SIDE VIEW
ET112QF36
105
52
Pin 1
80
59
Technical Data
Dimension
LA-9626
A-SH7055-S-BGA256
LA-9628
CPU-LASH7055-M
60
Technical Data
Adaptions
CPU
Adaption
SH7011
ET100-QF49
SH7014
SH7016
SH7017
SH7040
SH7042
SH7044
ET112-QF36
61
Technical Data
CPU
Adaption
SH7041
SH7043
SH7045
ET144-QF63
62
Technical Data
Adapters
Socket CPU
Adapter
ET100-QF49
YA-1091 ET100-EYA-QF49
Emul. Adapter for YAMAICHI socket ET100-QF49
SH7011
8
6
56
SIDE VIEW
66
18
14
TOP VIEW (all dimensions in mm)
63
Technical Data
Socket CPU
Adapter
ET112-QF36
YA-1101 ET112-EYA-QF36
Emul. Adapter for YAMAICHI socket ET112-QF36
SH7014
SH7016
SH7017
SH7040
SH7042
SH7044
8
6
56
SIDE VIEW
64
14
10
TOP VIEW (all dimensions in mm)
64
Technical Data
Socket CPU
Adapter
ET112-QF36
TO-1290 ET112-ETO-QF36
Emul. Adapter for TO socket ET112-QF36
SH7014
SH7016
SH7017
SH7040
SH7042
SH7044
2200
2500
PIN1
TOP VIEW
SIDE VIEW
600
ADAPTER
SOCKET
TARGET
ET112-QF36
TO-1291 ET112-STO-QF36
Emul. Adapter TO-surface mount. ET112-QF36
SH7014
SH7016
SH7017
SH7040
SH7042
SH7044
2200
TOP VIEW
PIN1
2500
SIDE VIEW
400
SOLDER
BLOCK
TARGET
ALL DIMENSIONS IN 1/1000 INCH
65
Technical Data
Socket CPU
Adapter
ET120-QF56
YA-1142 ET120-EYA-QF56
Emul. Adapter for YAMAICHI socket ET120-QF56
SH7040
SH7042
ET120-QF56
Adapter/ Target Design
TOP VIEW
2400
2400
2050
2050
32
360
31
775
4 X SAMTEC:
TFM-115-22-S-LC
ICP-120-2
66
Technical Data
Socket CPU
Adapter
ET144-QF63
YA-1111 ET144-EYA-QF63
Emul. Adapter for YAMAICHI socket ET144-QF63
SH7041
SH7043
SH7045
8
6
69
SIDE VIEW
69
17
18
67
Technical Data
Socket CPU
Adapter
LASH7055
LA-9626 A-SH7055-S-BGA256
Emul. adapter for AI-BGA-socket for LASH7055
SH7052
SH7053
SH7054
SH7055
68
Technical Data
Operation Voltage
This list contains information on probes available for other voltage ranges. Probes not noted here supply an
operation voltage range of 4.5 5.5 V.
CPU
Module
Adapter
Voltage Range
SH7011
SH7014
SH7016
SH7017
SH7040
SH7041
SH7042
SH7043
SH7044
SH7045
SH7050
SH7051
SH7052
SH7053
SH7054
SH7055
LA-9566
LA-9565
LA-9566
LA-9566
LA-9561
LA-9562
LA-9561
LA-9562
LA-9561
LA-9562
LA-9563
LA-9564
LA-9621
LA-9621
LA-9621
LA-9621
LA-9629
LA-9629
LA-9629
-
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 3.5 V
3.0 .. 3.5 V
3.0 .. 3.5 V
3.0 .. 5.5 V
69
Technical Data
Operation Frequency
Module
CPU
F-W010
F-W110
S-W010
S-W110
CHIP
TRACE HEAD
RAM
LA-9566
LA-9565
LA-9566
LA-9566
LA-9561
LA-9562
LA-9561
LA-9562
LA-9561
LA-9562
LA-9563
LA-9564
LA-9621
LA-9621
LA-9621
LA-9621
SH7011
SH7014
SH7016
SH7017
SH7040
SH7041
SH7042
SH7043
SH7044
SH7045
SH7050
SH7051
SH7052
SH7053
SH7054
SH7055
20.0
28.7
28.7
28.7
33.0
33.0
33.0
33.0
33.0
33.0
20.0
20.0
40.0
40.0
40.0
40.0
20.0+
28.7+
28.7+
28.7+
33.0+
33.0+
33.0+
33.0+
33.0+
33.0+
20.0+
20.0+
40.0+
40.0+
40.0+
40.0+
17.3
23.5
23.5
23.5
26.3
26.3
26.3
26.3
26.3
26.3
17.3
17.3
30.6
30.6
30.6
30.6
20.0+
28.7+
28.7+
28.7+
33.0+
33.0+
33.0+
33.0+
33.0+
33.0+
20.0+
20.0+
40.0+
40.0+
40.0+
40.0+
20.0
28.7
28.7
28.7
33.0
33.0
33.0
33.0
33.0
33.0
20.0
20.0
40.0
40.0
40.0
40.0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
70
Technical Data
Support
Probes
LA-9560
LA-9566
SH7011
ET100-QF49 3.0..5.5V
LA-9565
SH7014
ET112-QF36 3.0..5.5V
SH7016
ET112-QF36 3.0..5.5V
SH7017
ET112-QF36 3.0..5.5V
LA-9561
SH7040
SH7040
ET112-QF36 3.0..5.5V
ET120-QF56 3.0..5.5V
LA-9562
SH7041
ET144-QF63 3.0..5.5V
LA-9561
SH7042
SH7042
ET112-QF36 3.0..5.5V
ET120-QF56 3.0..5.5V
LA-9562
SH7043
ET144-QF63 3.0..5.5V
LA-9561
SH7044
ET112-QF36 3.0..5.5V
LA-9562
SH7045
ET144-QF63 3.0..5.5V
LA-9563
SH7050
ET168-QF25 3.0..5.5V
LA-9564
SH7051
ET168-QF25 3.0..5.5V
LA-9566
LA-9621
LA-9620
LA-9629
LA-9621
SH7052
LASH7055
3.0..3.5V
SH7053
LASH7055
3.0..3.5V
SH7054
LASH7055
3.0..3.5V
SH7055
LASH7055
3.0..5.5V
71
Support
SH7011
SH7014
SH7016
SH7017
SH7040
SH7041
SH7042
SH7043
SH7044
SH7045
SH7050
SH7051
SH7052
SH7053
SH7054
SH7055
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Compiler Support
Language
Compiler
Company
Option
GCCSH
COFF
C
C
C
GREEN-HILLS-C
ICCSH
SHC
C++
SHC++
C++
D-CC
Free Software
Foundation, Inc.
Greenhills Software Inc.
IAR Systems AB
Renesas Technology,
Corp.
Renesas Technology,
Corp.
Wind River Systems
Comment
COFF
UBROF
SYSROF
ELF/DWARF2
ELF/DWARF
72
Support
Company
CMX-RTX
HI7000
Linux
Linux
Nucleus
OS21
OSEK
ProOSEK
QNX
SMX
ThreadX
uITRON
VxWorks
Windows CE
Windows Mobile
Comment
via ORTI
via ORTI
6.0 to 6.5.0
3.4 to 4.0
3.0, 4.0, 5.x
HI7000, RX4000, NORTi,PrKernel
5.x and 6.x
4.0 to 6.0
4.0 to 6.0
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ATTOL TOOLS
VISUAL BASIC
INTERFACE
Host
Windows
Windows
Windows
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
73
Support
CPU
Tool
Company
Host
ALL
LABVIEW
Windows
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
ALL
ALL
74
Support
Products
Product Information
OrderNo Code
Text
LA-9560
FIRE-SH2-1
supports SH7040/7042/7044
with FIRE CPU Module for SH7040 (16-bit bus)
supports SH7041/7043/7045
with FIRE CPU Module for SH7040 (32-bit bus)
supports SH7014
with FIRE CPU Module for SH7014
supports SH7050
with FIRE CPU Module for SH7050
supports SH7051
with FIRE CPU Module for SH7051
requires FIRE-SRAM
LA-9561
FIRE-M-SH7040-16
LA-9562
FIRE-M-SH7040-32
LA-9563
FIRE-M-SH7050
LA-9564
FIRE-M-SH7051
LA-9565
FIRE-M-SH7014
LA-9566
FIRE-M-SH7017
LA-9620
FIRE-SH2-2
supports SH7055
with FIRE CPU Module for SH7055
requires FIRE-SRAM
LA-9621
FIRE-M-SH7055
LA-9625
A-SH7055-S-QFP256
TO-1395
TO-256RD-EXTENSION
75
Products
OrderNo Code
Text
LA-9626
A-SH7055-S-BGA256
AI-9634
BGA256-AI-SOCKET(SH)
LA-9629
A-SH7055-S-QFP208
LA-9627
CPU-LASH7055
LA-9628
CPU-LASH7055-M
76
Products
Order Information
Order No.
Code
Text
LA-9560
LA-9561
LA-9562
LA-9563
LA-9564
LA-9565
LA-9566
LA-9620
LA-9621
LA-9625
TO-1395
LA-9626
AI-9634
LA-9629
LA-9627
LA-9628
FIRE-SH2-1
FIRE-M-SH7040-16
FIRE-M-SH7040-32
FIRE-M-SH7050
FIRE-M-SH7051
FIRE-M-SH7014
FIRE-M-SH7017
FIRE-SH2-2
FIRE-M-SH7055
A-SH7055-S-QFP256
TO-256RD-EXTENSION
A-SH7055-S-BGA256
BGA256-AI-SOCKET(SH)
A-SH7055-S-QFP208
CPU-LASH7055
CPU-LASH7055-M
Additional Options
LA-9547
BGA256-CPU-ADAPTER
LA-7216
BGA357-CPU-ADAPTER
YA-1142
ET120-EYA-QF56
LA-2036
MCON320
LA-7526
MON-SH
77
Products