Design a 3X8 decoder

entity decoder is
port(a, b, c: in bit;
y: out bit_vector(0 to 7));
end entity;
architecture decoder_arch of decoder is
begin
process(a, b, c)
variable abar, bbar, cbar: bit;
begin
abar:=not a;
bbar:=not b;
cbar:=not c;
y(0)<= abar and bbar and cbar;
y(1)<= abar and bbar and c;
y(2)<= abar and b and cbar;
y(3)<= abar and b and c;
y(4)<= a and bbar and cbar;
y(5)<= a and bbar and c;
y(6)<= a and b and cbar;
y(7)<= a and b and c;
end process;
end decoder_arch;
--Test Bench
entity decoder_tb is
end entity;
architecture decoder_tb_arch of decoder_tb is
component decoder is
port(a, b, c: in bit;
y: out bit_vector(0 to 7));
end component;
signal a, b, c: bit;
signal y: bit_vector(0 to 7);
begin
inst: decoder port map(a, b, c, y);
process
begin
a<='0'; b<='0'; c<='0';
wait for 100 ns;
a<='0'; b<='0'; c<='1';
wait for 100 ns;
a<='0'; b<='1'; c<='0';
wait for 100 ns;
a<='0'; b<='1'; c<='1';
wait for 100 ns;
a<='1'; b<='0'; c<='0';
wait for 100 ns;
a<='1'; b<='0'; c<='1';
wait for 100 ns;
a<='1'; b<='1'; c<='0';
wait for 100 ns;
a<='1'; b<='1'; c<='1';

wait for 100 ns;

end process;
end decoder_tb_arch;

Design a D flip flop

entity flipflop1 is
port( d,clk:in BIT;
q:out BIT);
end entity;
architecture flipflop_arch of flipflop1 is
begin
q<=d when clk<='1';
end flipflop_arch;
--Test Bench
entity flipflop_tb is
port (d,clk:in BIT;
q:out BIT);
end entity;
architecture flipflop_tb_arch of flipflop_tb is
component flipflop1 is
port (d,clk:in BIT;
q:out BIT);
end component;
signal t1,t2,t3:BIT;
begin
inst1:flipflop1 port map(t1,t2,t3);
process
begin
t1<='1';
t2<='1';
wait for 200 ns;
t1<='1';
t2<='0';
wait for 200 ns;
t1<='0';
t2<='1';
wait for 200 ns;
end process;
end flipflop_tb_arch;

Design a 4x1 Mux

entity mux4 is
port(i: in bit_vector(0 to 3);
s: in bit_vector(0 to 1);
dd: out bit);
end entity;
architecture arch_mux4 of mux4 is
begin
dd <= ( (i(0)and (not s(0)) and (not s(1))) or (i(1)and s(0) and (not
s(1))) or (i(2)and (not s(0)) and s(1)) or (i(3)and s(1) and s(0)) );
end arch_mux4;

--Test Bench
entity mux4_tb is
end entity;
architecture arch_mux4_tb of mux4_tb is
component mux4 is
port (i:in BIT_vector(0 to 3);
s:in BIT_vector(0 to 1);
dd:out BIT);
end component;
signal in1:BIT_vector(0 to 3);
signal in2:BIT_vector(0 to 1);
signal o1:BIT;
begin
inst: mux4 port map (in1,in2,o1);
process
begin
in1<="1001"; in2<="00";
wait for 100 ns;
in1<="1001"; in2<="01";
wait for 100 ns;
in1<="1001"; in2<="10";
wait for 100 ns;
in1<="1001"; in2<="11";
wait for 100 ns;
end process;
end arch_mux4_tb;

Design an 8x1 Mux using 4x1 Mux

entity mux8 is
port (a:in BIT_vector(0 to 7);
sel:in BIT_vector(0 to 2);
d:out BIT);
end entity;
architecture arch_mux8 of mux8 is
component mux4 is
port (i: in BIT_vector(0 to 3);
s:in BIT_vector(0 to 1);
dd:out BIT);
end component;
signal o1,o2:BIT;
begin
inst1:mux4 port map(a(0 to 3), sel(0 to 1),o1);
inst2:mux4 port map(a(4 to 7), sel(0 to 1),o2);
d<= o1 when sel(2)='0' else
o2 when sel(2)='1';
end arch_mux8;

--Test Bench
entity mux8_tb is
end entity;
architecture arch_mux8_tb of mux8_tb is
component mux8 is
port (a:in BIT_vector(0 to 7);
sel:in BIT_vector(0 to 2);
d:out BIT);
end component;
signal in1:BIT_vector(0 to 7);
signal in2:BIT_vector(0 to 2);
signal o1:BIT;
begin
inst: mux8 port map (in1,in2,o1);
process
begin
in1<="10010101"; in2<="000";
wait for 100 ns;
in1<="10010001"; in2<="001";
wait for 100 ns;
in1<="10011100"; in2<="010";
wait for 100 ns;
in1<="10010010"; in2<="011";
wait for 100 ns;
end process;
end arch_mux8_tb;

Design a 4 bit comparator

entity compare is
port(a,b: in bit_vector(3 downto 0);
f1,f2,f3: out bit);
end entity;
architecture arch_compare of compare is
begin
process(a,b)
begin
if(a>b) then
f1<='0';
f2<='0';
f3<='1';
elsif(a<b) then
f1<='1';
f2<='0';
f3<='0';
else
f1<='0';
f2<='1';
f3<='0';
end if;
end process;
end arch_compare;
entity compare_tb is
end entity;
architecture arch_compare_tb of compare_tb is
component compare is
port(a,b: in bit_vector(3 downto 0);
f1,f2,f3: out bit);
end component;
signal ina,inb: bit_vector(3 downto 0);
signal of1,of2,of3: bit;
begin
inst: compare port map(ina,inb,of1,of2,of3);
process
begin
ina <="0000";
inb <="0000";
wait for 100 ns;
ina<="1111";
inb<="1111";
wait for 100 ns;
ina<="0101";
inb<="1010";
wait for 100 ns;
ina<="1010";
inb<="1011";
wait for 100 ns;
ina<="1011";
inb<="1010";
wait for 100 ns;
ina<="0010";
inb<="0011";
wait for 100 ns;
end process;

end arch_compare_tb;

Implement all 6 basic gates

entity gate is
port(x,y:in BIT; outa,outb,outc,outd,oute,outf:out BIT);
end entity;
architecture gate_arch of gate is
begin
outa<=x and y;
outb<=x or y;
outc<=x xor y;
outd<=x nor y;
oute<= not x;
outf<=x nand Y;
end gate_arch;
entity gate_tb is
end entity;
architecture gate_arch_tb of gate_tb is
component gate is
port(x,y:in BIT; outa,outb,outc,outd,oute,outf:out BIT);
BI
end component;
signal in1,in2,o1,o2,o3,o4,o5,o6:BIT;
begin
inst:gate port map(in1,in2,o1,o2,o3,o4,o5,o6);
process
begin
in1<='0';
in2<='0';
wait for 100 ns;
in1<='0';
in2<='1';
wait for 100 ns;
in1<='1';
in2<='0';
wait for 100 ns;
in1<='1';
in2<='1';
wait for 100 ns;
end process;
end gate_arch_tb;

Design a half adder

entity half_adder is
port(x,y:in BIT; s, c: out BIT);
end entity;
architecture fun1 of half_adder is
begin
s<=x xor y;
c<=x and y;
end fun1;
entity half_adder_tb is
end entity;
architecture fun2 of half_adder_tb is
component half_adder is
port(x,y:in BIT; s, c :out BIT);
end component;
signal in1,in2,s,c:BIT;
begin
mapping : half_adder port map(in1,in2,s,c);
map(in1,in2,s,
--inst:gate
inst:gate port map(in1,in2,o1,o2,o3,o4,o5,o6);
process
begin
in1<='0';
in2<='0';
wait for 100 ns;
in1<='0';
in2<='1';
wait for 100 ns;
in1<='1';
in2<='0';
wait for 100 ns;

end fun2;

in1<='1';
in2<='1';
wait for 100 ns;
end process;

Design a full adder using half adders

entity full_adder is
port(s, c, z:in bit; s2, c2:out bit);
end entity;
architecture fun1 of full_adder is
component half_adder is
port(x, y: in bit; s, c: out bit);
end component;
begin
s2<= s xor z;
c2<= (s and z) or c;
end fun1;

entity full_adder_tb is
end entity;
architecture fun2 of full_adder_tb is
component full_adder is
port(s, c, z:in bit; s2, c2:out bit);
end component;
signal in1,in2,in3,s2,c2 :bit;
begin
inst:full_adder port map(in1,in2,in3,s2,c2);
process
begin
in1<='0';
in2<='0';
wait for 100 ns;
in1<='0';
in2<='1';
wait for 100 ns;
in1<='1';
in2<='0';
wait for 100 ns;
in1<='1';
in2<='1';
wait for 100 ns;
end process;
end fun2;

Implement 8 bit shift register

entity shift8 is
port(i,clk2: in bit;
o: out bit);
end shift8;
architecture arch_shift8 of shift8 is
signal output: bit_vector (6 downto 0):="0000000";

begin

component dff is
port(d, clk: in bit;
q: out bit);
end component;

d0: dff port

d1: dff port
d2: dff port
d3: dff port
d4: dff port
d5: dff port
d6: dff port
d7: dff port
end arch_shift8;

map(i, clk2, output(0));

map(output(0), clk2, output(1));
map(output(1), clk2, output(2));
map(output(2), clk2, output(3));
map(output(3), clk2, output(4));
map(output(4), clk2, output(5));
map(output(5), clk2, output(6));
map(output(6), clk2, o);

--Test Bench
entity shift8_tb is
end entity;
architecture arch_shift8_tb of shift8_tb is
component shift8 is
port(i,clk2: in bit;
o: out bit);
end component;
signal outp,inp,clk:bit;
constant clk_period: time:=100 ns;
begin
inst: shift8 port map(inp, clk, outp);
clk_process:process
begin
clk<='0';
wait for clk_period/2;
clk<='1';
wait for clk_period/2;
end process;
stim_process:process
begin
inp<='1';
wait for clk_period;
inp<='0';
wait for clk_period;
inp<='1';
wait for clk_period;

inp<='0';
wait for clk_period;
inp<='1';
wait for clk_period;
inp<='0';
wait for clk_period;
inp<='1';
wait for clk_period;
end process;
end arch_shift8_tb;