Development of Multichannel Real-time Hardwarein-the-Loop Radar Environment Simulator for

Missile-borne Synthetic Aperture Radar

Ting Shu, Bin Tang, Kejun Yin, Qingyang Sun, Yangchun Chen, and Wenxian Yu
Shanghai Key Laboratory of Intelligent Sensing and Recognition, Shanghai Jiao Tong University,
Shanghai, 200240, P. R. China
Email: tingshu@sjtu.edu.cn
AbstractRadar target/environment simulators are usually
developed for testing and evaluating various radar systems. In
this paper, we present a novel implementation of real-time radar
environment simulator with four channels for missile-borne
Synthetic Aperture Radar (SAR). By using wideband Digital
Radio Frequency Memory (DRFM) technique and parallel
computing technique based on the Field Programmable Gate
Array (FPGA), the simulator can provide real-time computation
capability for raw SAR echo signal generation of extended scenes
with a very small computational delay, which is essential for the
missile-borne radar Hardware-in-the-Loop (HIL) simulation.
Based on the multichannel and multi-DRFM architecture, the
simulator is able to simultaneously generate multichannel SAR
echo signals together with jamming signals. Moreover, the
simulator is highly scalable and reconfigurable, and is able to
meet a various kinds of radar simulation requirements.
Keywordsmultichannel SAR echo signal simulator; DRFM;
missile-borne SAR; FPGA

I.

INTRODUCTION

Missile-borne Synthetic Aperture Radar (SAR) [1] is

typically used for modern terminal guidance weapon systems.
By using SAR and scene-matching guidance techniques, the
SAR seeker can realize accurate positioning on the target [2].
To quantitatively support the design of missile-borne SAR
system and to evaluate the processing algorithms, the raw
signal simulation is required [3], especially when the real raw
signal of the SAR seeker is not available. In practical
application, it is common for the designers to use the low-cost
ground-based Hardware-in-the-Loop (HIL) simulation [4]
technique in the stage of missile-borne SAR system integration,
testing, and verification.
Unlike conventional radar simulator [4-6], the R&D of HIL
SAR simulator for SAR seeker application is very difficult.
The designers and engineers have to face various kinds of
challenges. First, since the SAR seekers always work at a
relative high pulse repetition frequency (PRF), e.g., 10kHz ~
50kHz [7], the raw signal simulation algorithm must be
implemented in real-time condition without losing any radar
pulses. Second, the raw signal simulation of an extended scene
(e.g., a 40 km 40 km scene with 1m ~ 5m resolution) requires
huge computational resources, and the parallel computation
technique must be considered in real-time condition. Third, the
correction of channel amplitude and phase characteristic is

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Fig. 1. The real-time Hardware-in-the-Loop simulator system.

difficult for a wideband multichannel radio frequency (RF)

system. Fourth, a various kinds of errors [3] (e.g., radar system
error, beam pointing error, the error due to track jitter) must be
simulated to evaluate the performance loss of missile-borne
SAR system.
Recently, a real-time wideband missile-borne SAR target
and environment simulator with four channels is developed in
the Shanghai Key Laboratory of Intelligent Sensing and
Recognition of Shanghai Jiao Tong University (SJTU). The
resulting design of the real-time SAR HIL simulator is shown
in Fig. 1. The key point of this system is the wideband Digital
Radio Frequency Memory (DRFM) subsystem which has a
typical instantaneous bandwidth (IBW) of 1000MHz. The
simulator system provides four independent channels for
different use in the HIL simulation. That is two SAR echo
channels, one radar altimeter echo channel, and one jammer
signal channel, respectively. These signals can be generated
simultaneously. Like other radar target simulators [4-6], this
HIL SAR simulator is capable of simulating raw-signal at

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Suppose that the transmitted pulse of the SAR is

S ( ) = a ( )exp( j k 2 )exp( j 2 f c )

(2)

where is the fast time, a() is the envelope of the linear

frequency modulation (LFM) pulse, k is the chirp rate, and fc is
the carrier frequency. Then, the received baseband signal from
a point target locate in (xm, yn, 0) is [8]

d
un
ro
G

S ( , t ) = m, nWa (t )Wr ( ) a Rm , m (t )
c

exp j k Rm , m (t )

Rm , m (t )
exp j

e
ng
ra

where m,n is the reflectivity coefficient of the target, c is the

speed of light, is the wavelength, Wa(t) and Wr(t) is the twoway antenna beam pattern in the azimuth direction and range
direction, respectively.
The total received baseband SAR echo signal of an
extended scene is given by

Fig. 2. Missile-borne SAR geometry.

baseband, intermediate frequency (IF) and radio frequency (RF)

levels. Meanwhile, by using a large scale FPGA-based parallel
computing technique, the simulator can provide real-time
computation capability for raw SAR signal generation of
extended scenes with a very small computational delay. This
capability is critical for the missile-borne radar HIL simulation.
Moreover, with the capability of scalable and reconfigurable,
this simulator system is able to work in a variety of modes and
functions. In other words, engineers can define and change the
function of each DRFM channel by modifying the FPGA and
DSP code, without changing the hardware platform. This
brings great convenience to the users.
The remainder of this paper is organized as follows.
Section II introduces geometric configuration and the data
model for missile-borne SAR echo simulation. Section III
provides the system description and realization for SAR
simulator. Section IV summarizes some key techniques in the
system development. Section V presents the simulation and
experimental analysis. Section VI concludes this paper.
II.

GEOMETRY CONFIGURATION AND SIGNAL MODEL

In this section, we introduce the geometric configuration of

missile-borne SAR, and then give the data model of SAR echo
signal of extended scene.
A. Geometry Configuration
The geometry configuration for missile-borne SAR is
shown in Fig. 2. Suppose at the slow time t, the missile-borne
SAR is diving along Y axis at an altitude of h with the
instantaneous velocity v. The point target (xm, yn, 0) denotes a
point scatter in the SAR footprint. Therefore, the relative slant
range Rm,n(t) from the radar to this point scatter at ta is given by
Rm , n =

( xt xm )

+ ( yt yn ) + h 2
2

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(3)

Sscene ( , t ) =

M ,N

m =1, n =1

2
c

m , nWa (t )Wr ( ) a Rm , m (t )

exp j k Rm, m (t )

Rm , m (t )
exp j

(4)

B. Equivalent Signal Model

The 2-D data model for SAR echo signal generation is
time-consuming, and is difficult for real-time implementation.
By using equivalent data model based on equal range ring, we
have the following convolution expression [9]
4rm , n , p (t )
S ( ) = a ( )exp( j k 2 ) p exp j

2 R p (t )
(t
)
c

(5)

where denotes the convolution operatorrm,n,p(t) denotes

the difference of slant range between the target and the center
of the pth equal range ring, and can be expressed as
1

rm, n , p (t ) = Rm , n (t ) Rmin (t ) + ( p ) r p
2

(6)

where Rmin(t) is the nearest slant range at the slow time t, r is

the spacing of each equal range ring.
It means that the echo signal of SAR is the output response
of convolution between the baseband LFM signal and the scene
modulation signal. It is noted that, in digital signal processing
theory, the fast convolution can be realized by using FFT/IFFT
method in the frequency domain [8].

(1)

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Fig. 3. The block diagram of single channel SAR simulator system.

III.

SYSTEM DESCRIPTION

Recently, our laboratory succeeded in developing the realtime HIL simulator for missile-borne SAR system.
The SAR simulator in Fig. 1 mainly consists of four
subsystems, that is, one master control subsystem, two digital
subsystems, and one RF subsystem. The four subsystems are
integrated in a 32U cabinet.
A. Block Diagram
The block diagram of the SAR simulator is shown in Fig. 3.
The real-time simulation host plays a role of master control
subsystem. It sends the activating signal to the simulator and
the SAR seeker when starting the HIL simulation. During the
HIL simulation, it updates the information of missile position,
radar beam steering, and error information every 1 millisecond
(ms) in the real-time Local Area Network (LAN) environment.
In the digital subsystem, the two key components are the
scene processing boards and the wideband DRFM boards. The
scene processing boards are mainly used for parallel computing
for the scene modulation signal of extended scenes. During the
HIL simulation, each scene processing board synchronously
receives the updated information from the real-time simulation
host through the optical fiber with nanosecond delay. Then, the
DSPs on the board divide the reference SAR image of extended
scene into several small sub-scene images, and send out the
corresponding calculation task for each FPGA. Each FPGA
read the respective sub-scene image from the local DDR-3
SDRAM, and calculate the slant range for each scattering point,
the amplitude weighting for each range gate, the Doppler phase,
and the range gate index, etc. After that, the scene modulation
signals calculated by different scene processing boards are

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gathered and connected in one board, and it will be sent to the

wideband DRFM board to perform the fast convolution.
The wideband DRFM boards are mainly used for real-time
SAR signal acquisition and SAR echo signal generation. Two
large-scale FPGAs are used on each board to perform real-time
convolution on the SAR signals captured by the high-speed
analog to digital converter (ADC). During the HIL simulation,
the high-speed ADC captures each SAR pulse, and performs
the fast convolution with the scene modulation signal in
frequency domain. Then, the digital echo signal of the
convolution output is sent to compensate the delay, the
amplitude and the phase with different channel. After that, they
are temporarily stored in the dual block rams. Finally, the
synchronization pulse from the SAR seeker triggers the FPGA
to transmit SAR echo signal through the high-speed digital to
analog converter (DAC) at IF level.
The RF subsystem performs the frequency conversion
between RF and IF. It contains one RF down-conversion chain
and four independent RF up-conversion chains. To guarantee
the coherency of the radar and simulator, a common local
oscillator (LO) is used in the RF subsystem.
The system has a modular design that allows the number of
boards to be easily upgraded. In the SAR simulator system as
illustrated in Fig. 1, there are ten scenes processing boards and
four wideband DRFM boards. They are installed in two digital
subsystems with two independent motherboards.
B. The Scene Processing Board
The scene processing board as shown in Fig.4 (a) plays the
role of calculating the scene modulation signal. The board is a
6U CompactPCI (CPCI) format FPGA processor solution. It
contains two Stratix-IV Altera FPGAs and two TMS320C6678
(multicore architecture) Ti DSPs for real-time calculation of

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(a) The scene processing board.

(b) The wideband DRFM board.

Fig. 4. Some boards in the digital subsystem.

(c) The Reflective Memory Carrier Board.

connection make it ideal for radar and electronic counter

measure (ECM) simulator applications.

Fig. 5. Typical SFDR performance of the wideband DRFM board.

the scene modulation signal. Four independent DDR-3

SDRAM banks are configured with each FPGA and DSP. In
order to store the reference SAR image of extended scene in
the HIL simulation, each DDR-3 SDRAM banks is designed
up to 1GB deep. Each DSP has a 4 Serial RapidIO (SRIO)
interface to connect the corresponding FPGA at a data rate of
12.5Gbps. The board also provides high-speed I/O for the data
communication between boards. Four InfiniBand connectors
are available on the front panel, and each supports a data rate of
12.5Gbps by using the high-speed transceivers of FPGAs.
With a large number of high performance computing
resources and the high bandwidth connection, this board is
applicable to all kinds of advanced signal processing algorithm.
C. The Wideband DRFM Board
The wideband DRFM board as shown in Fig.4 (b) plays the
role of real-time SAR signal acquisition and SAR echo signal
generation. The board is also a 6U CPCI format. It contains
two large scale Stratix-V Altera FPGAs, one 10-bit high-speed
ADC sampling at 2.8GHz, and two 12-bit high-speed DAC
sampling at 2.8GHz. Two independent QDR SRAM banks are
configured with each FPGA. Eight InfiniBand connectors are
available on the front panel, and each supports a data rate of
12.5Gbps by using the high-speed transceivers of FPGAs.
The wideband DRFM board has a 1GHz instantaneous
bandwidth (IBW) with 10-bit ADC and 12-bit DAC sampling
at 2.8GHz. Fig. 5 shows the typical spurious free dynamic
range (SFDR) measurement on the DAC output of the
wideband DRFM. The SFDR measured over 1GHz IBW for all
input signals can achieve about -40dBc. The high performance
FPGA, high-speed ADC and DAC, and high bandwidth

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D. The Reflective Memory Carrier Board

The reflective memory carrier board in Fig.4 (c) is a 6U
CPCI board which provides two PMC sites with 32-bit/33MHz
PCI bus to connect the GE PMC-5565PIORC reflective
memory board. The CPU on this carrier board is the Freescale
MPC8313E PowerPC with 333MHz frequency. During the
HIL simulation, the PowerPC reads the memory of the
reflective memory board every 1ms, and broadcast the updated
information to all scene processing boards through the Serial
Peripheral Interface (SPI) bus.
IV.

KEY TECHNIQUE SOLUTION

For a multichannel wideband real-time SAR simulator, the

system design and realization of is challenging. In this section,
some key techniques are summarized.
A. Real-time convolution realization
The SAR echo signals are sent out from the wideband
DRFM board by using frequency domain convolution method.
Since the SAR seekers always work at a relative high PRF, e.g.,
10kHz ~ 50kHz, the convolution of SAR signal and the scene
modulation signal should be implemented within 20
microsecond (us) in the worst case.
In SAR application, it is noted that the length of the scene
modulation signal of an extended scene is often much longer
than the pulse wide (PW) of SAR signal. Thus, the operation
can be considered as a convolution of a short sequence and a
long sequence. In this situation, one can use the partitioned
convolution method and frequency domain algorithm for realtime calculation. The basic concept during development is to
take advantage of parallel and pipeline of FPGA.
For example, considering the situation where the length of
the scene modulation signal is 4096 and the frequency of
FPGA system clock is 200MHz. The direct convolution
method based on 4096-points FFT/IFFT need more than 50us
system delay according to the Altera FFT IP core [10]. By
using the partitioned convolution based on 1024-points
FFT/IFFT in Fig. 6, the total system delay of the wideband
DRFM board in Fig. 4 (b) is 41.5us.
In the worst case when the PRF is 50kHz, more processing
pipelines are needed to meet the requirement of 20us system
delay. Thats the reason why the wideband DRFM board in Fig.

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Fig. 6. The partitioned convolution method.

Fig. 8. The external calibration diagram.

Fig. 9. Typical time delay performance of the four channel output.

Fig. 7. The multiple pipelines strategy for real-time convolution.

4 (b) uses two large scale Stratix-V Altera FPGAs. In Fig. 7,

four 4096-points convolution pipelines are designed by using
these two FPGAs. The interfaces between them are four 4
SRIO interfaces to connect with each other at a data rate of
50Gbps. It is important to adjust the input/output delay (latency)
of adjacent pipelines to be smaller than the 20us pulse
repetition interval (PRI).
It should be noted that the maximum length of the real-time
convolution in this HIL simulator system is 64k-point, which is
corresponding to large SAR incidence angle or wide PW
(hundreds of us) situation.
B. The calibration of channel
The channel calibration is essential to both multi-channel
SAR and multichannel SAR simulator. The purpose of
calibration is to minimize the unbalance of delay, amplitude
and phase among channels. In this SAR simulator, we apply
the external calibration for the RF subsystem and digital
subsystem. Then, we use the digital compensation of the delay,
amplitude and phase in the FPGA on the DRFM board.
In external calibration, calibration signal is injected from
the SAR seeker. As shown in Fig. 8, the IF output signal of the
DRFM board is injected to a 1 to 4 power splitter. Then, the
four IF signals are injected to the four IF input ports of RF
subsystem. By calculating the value of delay, amplitudes and
phases of four output signals, the calibration values are
obtained. After that, the real-time digital channel compensation

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module which consists of the delay control, the inverse-Sinc

filter and the complex Chebyshev digital FIR filter [11] are
used after the fast convolution module. The time delay
precision of four channel output is smaller than 50 picoseconds
(see Fig. 9). The peak-peak value of channel amplitude and
phase mismatch can be corrected to a level of 1dB/3.
C. Real-Time Networking with Reflective Memory Solution

Fig. 10. The real-time network architecture for the HIL SAR simulation.

The reflective memory network is a real-time LAN in

which each computer node always has a local, up-to-date copy
of the network's shared memory set. It can be designed to
provide the highly deterministic, tightly timed performance for
a variety of distributed simulation applications.
In our missile-borne SAR simulation application, the realtime simulation host, the HIL SAR simulator, and the real-time
visual simulation system are the three nodes in the reflective
memory network. Each node has a reflective memory node
board. The real-time simulation host is the main node in the
network. During the simulation, it updates the information of

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azimuth

range

(a) The profiles of range and azimuth of the FPGA generated signal
range

azimuth

Fig. 12. The HIL SAR simulation results.

(b) The profiles of range and azimuth of the floating-point algorithm
Fig. 11. The compression of the imaging results for a point target.

missile position, radar beam steering, and error information

every 1ms. By using the optical fiber cable, the delay of update
in each node is only several hundred nanoseconds.
V.

EXPERIMENTAL RESULTS

In this section, the performance of the SAR simulator is

evaluated. In order to verify the accuracy of the SAR simulator,
the experiment results of point target and extended scenes are
analyzed.
A. Point Target Verification
The echo signal of a point target generated by the SAR
simulator with fixed-point calculation is imaged using the
Chirp Scaling (CS) algorithm [8]. The comparisons with the
floating-point algorithm generated echo signal are studied. The
profiles of range and azimuth compression are shown in Fig.
11. The resolution, peak side-lobe ratio (PSLR) and integrated
side-lobe ratio (ISLR) are summarized in Table I. From Table
I, it is clear that the point targets measured parameters of the
two methods are comparable, which indicates the echo data
generated by the HIL SAR simulator is valid.
TABLE I.

THE MEASURED RESULTS OF POINT TARGET IMAGE

fixed-point algorithm

Resolution (m)
PSLR (dB)
ISLR (dB)

floating-point algorithm

range

azimuth

range

azimuth

2.118
-15.22
-12.15

3.215
-18.13
-14.61

2.113
-15.24
-12.18

3.209
-18.25
-14.6

B. HIL Simulation Results

The HIL simulation experiments are carried out to test the
performance of SAR simulator. A Ku-band SAR system with
3m resolution is used in this experiment. The PRF of SAR
system is selected to be 20 kHz. After two seconds continuous
simulation for the stripmap mode, four strips of extended scene
are imaged in the tested SAR system. Fig. 12 gives the HIL
simulation results. It is shown that the SAR simulator provides
a reliable echo signal generation performance.
VI.

CONCLUSION

A real-time wideband missile-borne SAR simulator with

four channels is developed in our laboratory of SJTU. By using

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wideband DRFM and the FPGA based parallel computing

technique, the simulator can provide real-time computation
capability for SAR echo signal generation of extended scenes.
Based on the multichannel and multi-DRFM architecture, the
system is able to simultaneously generate multichannel SAR
echo signals together with jamming signals. Moreover, with the
capability of scalable and reconfigurable, this simulator is able
to work in a variety of modes and functions. The experiment
results show that the simulator provides excellent and reliable
performance for SAR echo signal generation, and it is also well
suited for SAR and ECM test, verification and evaluation [12].

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