You are on page 1of 119

# Power IC Design

## Chapter 7. Switched-Inductor Regulators

7.1. Power Stages
7.2. Output Ripple
7.3. Power Losses
7.4. Frequency Response
7.5. Feedback Control
A. Switched Inductor: i. Continuous Conduction (CCM)
Objective: Inductor transfers energy from vIN to vO.
Characterizing Feature: Inductor conducts continuously.
!
\$
Inductor:
diL
dt
diLvL
2
=
And i
=
L
EL
=
0.5LX

#
"
&
%
v
L
X
L

dt
LX
. iL and EL rise with a positive voltage and fall with a negative voltage.
Operation: Energize LX from vIN iL rises.
Drain LX into vO iL falls in alternating phases.
Duty Cycle dE = Fraction of switching period energizing switches are on tE/tSW.
1 dE = Fraction of switching period energizing switches are off tD/tSW.
(Signer's identity unknown) Signed by Preflight Ticket Signature Time: 2016.10.2
1 00:43:32 Z
Page 1

Power IC Design
ii. Discontinuous Conduction (DCM)
Characterizing Feature: Inductor conducts discontinuously.
Operation: Energize LX from vIN iL rises to iL(PK).
Deplete LX into vO iL falls to zero.
Open- or short-circuit LX until next tSW vL and iL remain zero.

## . LX delivers discrete energy packets to vO.

Duty Cycle dE = Fraction of conduction period energizing switches are on tE/tC.
1 dE = Fraction of conduction period energizing switches are off tD/tC.
B. Basic Topologies: i. Buck or Step-Down DC DC Converter
Feedback loop around vO keeps vO near target . vO is nearly constant.
Insightful (intuitive) Analysis: Inductor LO is a low-frequency short.
. vSW(AVG) = vO and iL(AVG) = iO(AVG) = iLD.
!
tE
tSW
\$
&
%
=
vINdE
. vO is a fraction of vIN.
vO
=
vSW(AVG)
=
vIN
#
"
Operation:
SI energizes LO from vIN . vL = vIN vO > 0 iL rises.
Open SI . iL lowers vSW until DG forward-biases.
DG drains LO into vO . vL
vO < 0 iL falls.
Assume
Ideal Diode:
vD(ON) 0.

## SI conducts a dE fraction of iL(AVG) . iIN < iL(AVG) = iO(AVG) = iLD.

Page 2

Power IC Design
Example
Objective: Determine dE and .iL for a buck dc dc converter when
vIN = 4.0 V, vO = 1.8 V, LO = 22 H, and tSW = 1 s.
Solution:
vO
1.8
=
=
45%
vO = vINdE
dE
=
4
vIN
tE
tE = dEtSW = 450 ns
dE
=
tSW
!
diL
dt
\$
&
%
vL
=
LO
#

"
"%"
%"
vE
vIN
vO
'
4-1.8%
.
.iL
=
\$\$
'\$
'450n
=
45
mA
'tE
=
\$
#
LO
&#
LO
&#
22
&
'tE
=
\$
ii. Boost or Step-Up DC DC Converter
Insightful Analysis: Inductor LO is a low-frequency short.
DO CO is a positive peak detector . vO
vSW's positive peak vSW(PK):
!
tO
tSW
\$
&
%

=
vOdDO
=
vO
(1dE
)
vIN
=
vSW(AVG)
=
vSW(PK)
#
"
vIN is a fraction of vO.
Operation: SG energizes LO from vIN . vL = vIN > 0 iL rises.
Open SG . iL raises vSW until DO forward-biases.
vIN
vO < 0 iL falls.
DO drains LO into vO . vL
DO duty-cycles iL .
iO

iL(AVG)dDO

## < iL(AVG) = iIN.

iLD discharges CO across tE.
. vO ripple can be high.
Page 3

Power IC Design
iii. Non-Inverting Buck Boost DC DC Converter
=vSWO(AVG)=vSWO(PK)
tOtSW!
"#
\$
%&
=vOdDO=vO1-dE()vO=vINdE1-dE"
#\$
%
&'
Insightful Analysis: Inductor LO is a low-frequency short.
DO CO is a positive peak detector . vO
vSW's positive peak vSW(PK):
. If dE < 0.5 vO < vIN.
If dE > 0.5 vO > vIN.
Operation: SI and SGO energizes LO from vIN . vL = vIN > 0 iL rises.
Open SI and SGO . iL lowers vSWI until DGI and DO forward-bias.
DGI and DO drains LO into vO . vL
vO < 0 iL falls.
Non-inverting buck or boost.
Note SI DGI LO buck feeds LO SGO DO boost to perform buck boost function.
!
\$
&
%
tE
=
vINdE
vSWI(AVG)
=
vIN
#"
tSW
iv. Inverting Buck Boost DC DC Converter
Insightful Analysis: Inductor LO is a low-frequency short.
DO CO is a negative peak detector . vO
vSW's negative peak vSW(PK):
. If dE < 0.5 |vO| < vIN.
If dE > 0.5 |vO| > vIN.
Operation: SI energizes LO from vIN . vL = vIN > 0 iL rises.
Open SI . iL reduces vSW until DO forward-biases.
DO drains LO into vO . vL
vO < 0 iL falls.
Note: iO iL(AVG)dDO < iL(AVG) = iGND and iIN
iL(AVG)dE < iL(AVG) = iGND.
Inverting buck or boost.
+vSW(PK)
tOtSW!
"#
\$
%&
=vINdE+vOdDOdE1-dE%

&'
!
\$
tE
0
=
vSW(AVG)
=
vIN
#
"
&%
tSW
Or
"
dE
%"
vO
=
-vIN
\$
'
=
-vIN
\$
#
dDO
&#
Page 4

Power IC Design
C. Power Switches: i. Synchronous Non-Blocking Options
Ideal Switches: Drop 0 V, leak 0 A, respond instantly, and occupy no space.
MOSFETs:
Require a synchronizing gate signal to switch Synchronous switches.
Can drop 10 200 mV when conducting current Low ohmic power PR.
Can respond in nanoseconds Fast. Substrate MOSFET
Either terminal can be the source.
Current can flow in both directions.
Gate signals can crisscross.
Well MOSFET
to keep them from shorting their inputs.
Body diodes can conduct currents in the off state.
Substrate FET: Substrate current iSUB.
Well FET: Bulk current iB.
Examples
Synchronous Buck
Synchronous Buck:
Bulks connect to supplies.
DN conducts outgoing iL.
DP conducts incoming iL (when iL reverses).
Synchronous Boost:
Synchronous Boost
Bulks connect to ground and output vO.
DP conducts outgoing iL.
DN conducts incoming iL (when iL reverses).
Page 5

Power IC Design
Operation
Synchronous switch can conduct negative current.
. LO is never in DCM Negative conduction draws (dissipates) CO power.
Body diodes conduct across tTD:
MN's DN when iL > 0 toward vO.
MP's DP when iL < 0 from vO.
Synchronous Buck
Body diodes induce or conduct substrate current iSUB.
. Body-diode conduction generates substrate noise.
For lower losses, avoid synchronous operation when loads are light.
ii. Synchronous Blocking Options
Isolate body and block body diodes with opposing body diodes.
In-Line Dual-Well Pair:
2(2RMOS) with CGATE or RMOS with 2(2CGATE).
Separation between wells increases silicon area ASI.
In-Line Shared-Well Pair:
Off State: Body diodes connect bulk to highest potential.
2(2RMOS) with CGATE or RMOS with 2(2CGATE).
Off-Line Bulk-Selected Transistor:
Cross-coupled FETs connect bulk to highest potential.
v RMOS with CGATE.
On State: MX12 is off . Body diodes may not charge
CBULK as quickly as terminal voltages rise.
Page 6

Power IC Design
iii. Asynchronous (Diode) Options
PN-Junction Diodes and Diode-Connected FETs:
Currents "open" and "close" diodes automatically
Asynchronous switches.
Drop 0.6 0.9 V when conducting current High ohmic power PR.
. Replace diodes with FETs when possible.
Can respond in nanoseconds Fast.
Drop vD or vGS, leak 0 A, and respond quickly.
vT-Shifted Diode-Connected FETs:
Drop vGS vS 100 200 mV.
vS requires quiescent power PQ and delays response.
Comparator-Synchronized FETs:
Drop iDRTRIODE 10 200 mV.
Comparators draw quiescent power PQ and delay response.
Comparator-Synchronized PFET
High-Side Switch: Non-blocking MOS MSW.
PMOS bulk to N side vN so the body diode conducts current
across dead time between switches and comparator's reaction time.
Comparator: Operate on demand to eliminate standby power Bias with iIN.
When vP nears zero,
Circuit shuts IQ is zero.
When vP > vSG + VIB, MB biases vG.
MD1, MM1, and MM2 mirror IB.
When vP < vN, MD2 overwhelms IB.
. vO rises and MSW opens.
When vP > vN, MD2 shuts.
. IB pulls vO low quickly and MSW closes.
Page 7

Power IC Design
Operation
Asynchronous switch blocks negative current .
When iO = iL(AVG) = 0.5.iL: LO conducts continuously in CCM.
When iO = iL(AVG) < 0.5.iL: LO conducts discontinuously in DCM.
Asynchronous Buck
DG opens when ELO = 0 J and vL =

(vO + vD).

## . LO and vSW's CSW draw energy from CO.

LO and CSW exchange drawn energy.
Until LO's equivalent series resistance RL ESR consumes energy and
vSW settles to vSW(AVG)
vO Remnant energy produces resonance noise.
7.2. Output Ripple
Page 8

Power IC Design
A. Continuously Supplied Outputs
When LO connects to vO directly, like in a buck: iCO = iL
LO's ripple .iL flows through CO and CO's RESR and LESL.

iO = iL

.
.iL into CO produces a parabola in vCO.
.iL into RESR reproduces iL's triangular ripple in vESR.
Constant diL/dt's into LESL produce a square in vESL.
"
%
"
diL
%
.iL
.v=
v+
v+
v=
.\$
''
dt+
R.i+
L\$
'
O
CO
ESR
ESL
\$
ESR
L
ESL
C
dt
&
#
O
&#

Switching Noise
Parabola in vCO mostly produces a quasi-sinusoidal tone at fSW.
Triangle in vESR and square in vESL produce harmonic noise.

iLD = .iL.

## Removing RESR and LESL eliminates nearly all harmonic noise.

Connecting low-ESR and low-ESL capacitors in parallel also helps.
Page 9

Power IC Design
B. Duty-Cycled Outputs
When DO disconnects vO from LO, like in a boosting circuit: iCO = iDO
iLD.
.iL is usually a tiny fraction of DO's iDO.
iDO is discontinuous
Wide and abrupt iCO variations . High output ripple .vO.
iDO iLD and iLD and their di/dt's are nearly constant.
. iLD discharges and iDO
iLD charges CO Nearly triangular vCO.
iLD and iDO
iLD into RESR drop nearly constant voltages Pulsing vESR.
Abrupt iCO into LESL produces substantial spikes Spiked vESL.
Switching Noise
Triangular vCO, spiked vESL, and pulsing vESR produce substantial noise.
Removing RESR and LESL reduces, but does not eliminate harmonic noise.
Root cause for high harmonic noise and output ripple .vO
is that DO disconnects the load from its source LO.
Page 10

Power IC Design
CO supplies or absorbs sudden load dumps .iLD until the system recovers.
"
%"
%
\$
.iLD
diLD
'
+\$
'dt
.vO
=
.vCO
+
.vESL
+
.vESR
=
.\$
'LESL
+
.iLDRESR
#
CO
&#
dt
&
CO Dominant
LESL Dominant
RESR Dominant
Buck Response
Lowest .vO
when:
CO and f0dB
are high
and
RESR and LESL
are low.
Boost .vESL and .vESR can be less noticeable than .vCO because .iDO is very high
.

D. Small-Signal Simulations
Challenge: The steady-state bias of a switched-inductor circuit is a ripple,
not a dc signal . ac SPICE simulations do not work.
Fix: Break loop at measurable analog feedback point like sO.
Reproduce rippling bias SO' with a closed-loop replica of the system.
Feed bias SO' to the system.
Inject a small sinusoid ssin at fi, where ssin << SI and fi << fSW.
Loop gain ALG at fi is so/ssin.
Repeat at other fi's to reproduce response across frequency.
Page 11

Power IC Design
Buck Example
Break Loop: At vO.
Bias Loop: Produce rippling steady-state bias VO' with a replica
of the system and feed bias VO' to feedback point.
Stimulate: Inject sine vsin at fi into the reference vREF.
Signal Flow: vsin de il vo.
Loop Gain: vo/vsin .vO(PP)/vsin(PP) at fi with .vO-to-vsin's phase shift.
Note: vsinALG < vsin above f0dB .
To decipher vO variations, raise vsin
as fi rises, but only as long as vsin produces small-signal variations.
7.3. Power Losses
Page 12

Power IC Design
A. Power-Conversion Efficiency
Fraction of input power PIN that reaches the output vO as PO.
PO
PIN
PLOSS
PLOSS
=
=1.C
=
PIN
PIN
PIN

## Fractional power losses PLOSS/PIN determine power-conversion efficiency .C.

Switches drop mV's . Loss is low.
Inductors drop mV's on average . Loss is low.
Capacitors conduct nA's on average . Loss is low.
. Fractional losses are low .
.C is high at 80% to 98%.
.C can be much higher than in linear regulators.
Possible because
iL cannot change instantaneously . vL does vSWITCH(AVG)
0 V.
vC cannot change instantaneously . Output ripple .vO is low
Accurate.
B. Loss Mechanisms
In practice, parasitic components dissipate power.
Synchronous Buck
Series Resistances: Ohmic conduction power iL(RMS)
2RPAR.
Switching Gates: Gate-drive power required to charge gates qCvINfSW.
Ground Current: Controller power iGNDvIN . Speed . fSW.
Other Losses: Switch-node power to charge parasitic capacitance.
Transitional power to deliver iL when vDS transitions.
Transitional shoot-through power in gate drivers.
Large transistors leak power when off.
Page 13

Power IC Design
C. Buck Losses: i. CCM DC Conduction Losses
Useful Relation: PR = iR(RMS)
2RX = iR(AVG)
2RX + .iR(RMS)
2RX.
Equivalent Power Circuit:
iL flows through MP and MN in alternating cycles.
. iL almost always flows through an equivalent resistance RSW.
RCH
1.
.
.
tD
2tDT
2tDT
.
.
.
.
.
tE
RSW
=
RMI
+
RMG
.
.
.
.
.
.

.
.
..
tSW
tSW
tSW
2iLDRSW+RLESR()=2iORDCiL(AVG) = iLD = iO and flows through RSW, LO, and RL ESR .
Synchronous Buck
And although not always equal, RMI and RMG are on the same order.
ii. CCM Ripple Conduction Losses
.iL flows through RSW,
LO, RL ESR, RC ESR, and CO .
.iL=
vELO#\$\$
%
&''
tE=
vEdELOfSW2.iLttE"
#\$
%
&'
2dt005tE.+
.iLttD"
#\$
%
&'
2dt005tD.
)
*
++,22.iLtE23+tD0.5.iL3PR(AC)=2.iL(RMS)RSW+RLESR+RCESR()=2.iL(RMS)RAC.i L
2"
. iRMS of a positive triangular current is iPK/v3 and
RAC dissipates power when iL is greater and less than iL(AVG) . Derive iL(RMS):
+ and
qC + qC
+ qC
qC
2
=
PR(DC)
=
iL(AVG)
(RSW
+
RL
ESR
)

"
"
%
.iL(RMS)
=
\$
'
=
.
=
23
3tSW
tSW
#
&
.
2
'
RAC
%
%
RAC
=
KRMS
"
0.5.iL3
0.5vEdELOfSW3
&
\$

#
2
fSW
'
&
"
%
'
RAC
=
2PR(AC)
=
.iL(RMS)
RAC
=
\$
\$
#
&
#
Raising fSW reduces ripple .iL and ripple-conduction losses PR(AC).
Page 14

Power IC Design
iii. DCM Conduction Losses
iL(AVG) is no longer a dc offset in DCM . PR = PR(DC) + PR(AC) = iL(RMS)
2RDCM.
iL(RMS) flows through RSW and RL ESR and iL
iO flows through RC ESR.
.
PR
=
iL(RMS)
2(RSW
+
RL
ESR
)+(iL(RMS)
2RC
ESR
iO
2RC
ESR
)
Energy packets (and conduction losses) drop when iO falls and frequency rises.
2
2
=
iL(RMS)
!
#
"
iL(PK)
3
!
tC
tSW
\$
&
%

\$
#
"
&
%
iL(PK) and tC rise with iL(AVG):
"%
"%
qL
Area
0.5titSW
tSW
CL(PK)
.i=
i=
2i\$
'
=
2iO
\$
'
=
=

L
L(PK)
L(AVG)
\$
'
iL(AVG)
=
#
tC
&
'
#

\$
tC
&
tSW
tSW
tSW
4
15
dE
()
.
.
2
iL(AVG)vIN
vO
tE
iL(PK)LO
2iL(AVG)tSWLO
iL(RMS)
3
E
.
.
=
=
=
.
05
.
dE
=
t
tC
=
.
fSW

..
2LO
tC
dE
dE
(vIN
vO
)
dE
(vIN
vO
)
iv. Gate-Drive Losses
Controller draws vIN energy every cycle to charge gate capacitances.
EG = qC.vC = (CG.vC).vC = CG.vC2
PG = EG/tSW = EGfSW.
vIN supplies EG after each dead time.
CGDG and CGSI charge across vIN:
COL = COX"WCHLOL across vIN.
CCH = COX"WCHLCH across vIN
|vT|.
CGSG starts with vD and ends with vIN.
.vGSG = vFIN
vINI = vIN
vD.
CGDI starts with vIN + vD and ends with
.vGDI = ( vIN)
222
2
S
.
EG
=
CGDG
vIN
+
CGSI
vIN
+
CGSG
(vIN
vD
)+
CGDI
(2vIN
+
vD)and PG
=
CG.vC

(vIN + vD).

vIN.

fSW
Note vIN delivers CG.vC2, CG stores 0.5CG.vC2, and drivers dissipate
0.5CG.vC2 when charging and CG's 0.5CG.vC2 when discharging.
Page 15

Power IC Design
v. Switch-Node Losses
Switch burns power PSW when charging vSW's parasitic capacitance CSW.
. PSW climbs with capacitance CSW, swing .vSW, and frequency fSW:
Charge Energy ECHG = qCvIN = (CSW.vSW)vIN.
Stored Energy EC = 0.5CSW.vSW2.
Energy Lost ESW = ECHG
EC.
Power Lost PSW = ESWfSW = CSW(.vSWvIN
0.5.vSW2)fSW

0.5CSW.vSW2fSW.

## Gate-drive power PG accounts for switches' CGD's.

. CSW = CDBI + CDBG + CBOND-PAD + CPIN + CBOARD.
Buck: MP charges CSW from vD to vIN to burn ESW.
LO drains CSW from vIN to vD into vO to recover CSW's EC.
MG charges to 0 V to burn (some) ESW and LO drains to vD to recover EC.
vi. Transitional iL vDS Losses
Power switches consume power to iL when vDS transitions.
MI 's .vSD before and after dead time is vIN + vD Power can be substantial.
MG 's .vDS before and after dead time is vD Often a negligible fraction.
MI's Transitions:
vSW falls and vSDI rises as soon as iDI falls below iL(PK)+.
vSW rises and vSDI falls after iDI surpasses iL(PK) .
Transitional Loss: CSW's tV reduces PIV(PK)+ and raises PIV(PK) .
0.5tI.vSWiL(PK)+
0.5tI.vSWiL(PK)-

+
PIV
tV<<tI
tSW
tSW
=
0.5tIvIN+vD()iL(PK)++iL(PK)-()
tSW
0.5tIvIN+vD()2iL(AVG)()
tSW
\$
tI
'
=

)
%
tSW
(
=(vIN
+
vD)iL(AVG)
&

Drivers current-limit CG to set tI and iL and iDI current-limit CSW to set tV.
Page 16

Power IC Design
vii. Dead-Time Conduction and viii. Shoot-Through Losses
iL(PK)++iL(PK)-(
=2vDiL(AVG)
tDTtSW.
..
.
..
Shoot-Through:
.Transistors short supplies momentarily.
Two drivers transition twice:
PST (2)(2).vGRP+RN.
..
.
..
.vGtSTtSW.
..
.
..
=42.vGRST.
..
.
.
tSTtSW.
..
.
..
iSHOOTvIN
.
.
.
.
.
.
.
.
.
.
.
.
..
.

.
.
.
.
..
.
..
.
ix. Leakage Losses
Large transistors leak power PLK when they are off.
Off current iOFF climbs with channel area ACH and temperature TJ.
Example: WCH = 10000 m and LCH = 0.18 m.
iOFF = 1 Aat TJ = 25 C.
iOFF = 40 Aat TJ = 125 C.
Synchronous Buck:
PLK
=
iP(OFF)
vPD
+
iN(OFF)
vNE
..
+
vNDT
.
.
.
.
.
.
tSW
tE

..
.
+
iN(OFF)
vIN
2tDT
.
..
tSW
tDT
.
..
)
.
.
.
.
.
tSW
tE
tSW
..
.
.
.

+
vD
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
..
tSW
.
.
.
.
.
.
.
.
.
.

..
.
.
+
vPDT
..
tSW
.
.
.
.
.
.
.
.
.
2tDT
tSW
..
.
.
.
+
vD
.
.
.
.

+
vD
2tDT
tSW
2tDT
tSW
tSW
tE
2tDT
tSW
2tDT
tSW
+(vIN
+
vD)
tD
2tDT
tD
2tDT
tSW
tD
PDT
vD
..
.

+
iN(OFF)
vIN
tE
.
.
.
.
.
.
.
.
.
...
..
.

iP(OFF)
vIN
=
iP(OFF)
vIN

iP(OFF)vIN
.
.
.
tD
tSW
+
iN(OFF)vIN
tSW

Page 17

Power IC Design
x. Example
Objective: Determine .C for a synchronous buck converter in CCM when vIN = 4.0 V
,
vO = 1.8 V, vD
0.7 V, vTN = |vTP| = 0.6 V, iO = 250 mA, tSW = 1 s, tDT
15 ns,
tI 1.5 ns, tST
1.5 ns, RDRV = 5 O, RCH = 250 mO, iOFF = 1 A, CCH = 280 pF,
COL = 70 pF, CDB = 80 pF, LO = 22 H, RL ESR = 100 mO, and RC ESR = 25 mO.
Solution: From last example, dE = 45%, tE = 450 ns, and .iL = 45 mA.
2tDT
PR(DC)
=
iL(AVG)
2
.
.
.
.
RON1.
..
0.5.iL3=
0.5(45m)
3
.
=
(250m)2(235m+100m
+
RL
ESR
)
=
20.9
mW
.
.

..
tSW
Since
.iL(RMS)
=
13
mA
=
2..
2tDT
..PR(AC)
.iL(RMS)
.RCH
.1.+
RL
ESR
+
RC
ESR
.
=
(13m)2(235m+100m+
25m
)=
61
W
..
tSW
..
222
2CGDG
vIN
+
CGSI
vIN
+
CGSG
(vIN
vD)+
CGDI
(2vIN
+
vD
)

tSW
2
22
2(70p)42
+
280p
40.6
+
70p(40.7)2
+
280p
40.60.7
+
70p
2(4)+
0.7
()()[]
1
13.6
mW
PG

=
=
2
.
.
.
.
.
.
4+0.7()
2
2
.

CDBG+CDBI().vSWvIN.vSW2..
.
tSW
2
80p
.
(
.
4+
0.7)
4
()
)
.(
.
PSW
=
=
1.24
mW

.
(1)
.
.
.
.
tI
tSW

PIV
PIVP
(vIN
+
vD)iL(AVG)
4+
0.7
1.76
mW
=(
.
.
.
.
=
.
..
)(250m)
1.5n
1
.
.
.
tDT
tSW
.
.
PDT
2vDiL(AVG)

=
5.25
mW
.
.
.
.
.
.
.
=
2(0.7)(250m)
15n
1
2
2
1.5n
42
.
.
.
.
.
tST
tSW
.
.
.

.
.
.
.
.
tST
tSW
.
.
.
.vG
vIN
PST
4
=
4
=
4
=19.2
mW
.
.
.
.
.
.
.
.

.
.
.
.
.
.
.
.
..
RST
RDRV
5
1
.
2tDT
2tDT
.C=POPIN=POPO+PLOSS=vOiOvOiO+PR(DC)+PR(AC)+PG+PSW+PIV+PDT+PST+PLK (1.8)(250m)
(1.8)(250m)+20.9m+61+13.6m+1.24m+1.76m+5.25m+19.2m+4=87.9%
PLK=iP(OFF)vIN.
..
+iN(OFF)vIN.
..
.
.
.
.
.
..
.

..
tD
tE
=
2.2+1.8=
4
W
+
vD
+
vD
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
..
tSW
tSW

tSW
tSW
Page 18

Power IC Design
Synchronous Boost
0 vO
.iL(RMS) = 0.5.iL/v3
(vO + vD)
0
D. Boost Losses
Trace iL(AVG) and .iL and their fractions.
MPO conducts dO fraction of iL.
. iO = iL(AVG)dDO = iLD. 0 vO
PLK
iN(OFF)vO
.
.
.
tD
tSW
.
.
.
+
iP(OFF)vO
.
.
.
tE
tSW
.
..
2
)

=
!
#
"
iO
dDO
\$
22
PR(DC)
=
iL(AVG)
RDC
=
iL(AVG)
RL
ESR
+
RSW
(
RL
ESR
+
RSW
)
(
&
%
2
.
22.PR(AC)
.iL(RMS)
(RL
ESR
+
RSW
)+{iO
2dE

+(iL(AVG)
iO)+
.iL(RMS)
dDO
}RC
ESR
.
.
fSW
=
22
)+
CGSO
)+
CGDO
2
2
2
.
.
..
PG
=
CG
CGSG
+
CGDG
2vO+vD
fSW
(
(vO-vD
.vC

vO
vO
S
PSW
0.5
CDBG
+
CSBO
LO charges CSW and MG burns CSW's EC .
(
)(vO
+
vD
)2fSW
tI
%"
tI
%"
iO
%PIV
PIVN
0.5\$
"
'
=(vO
+
vD)\$
'.vSW
(iL(PK)+
iL(PK)+
)=(vO
+
vD
)iL(AVG)
\$
'tIfSW
#
tSW
&#

tSW
&#
dDO
&
tDT
tSW
&
(
'
=
vD
(
2iL(AVG)
)
#
%
\$
tDT
tSW
&
(
'
=
2vD
#
%

\$
iO
dDO
&
(
'
tDTfSW
#
PDT
vD
iL(PK)+
+
iL(PK)(
)
%
\$
E. Power Dominance
PLOSS in CCM: PR(DC) + PR(AC) + PG + PSW + PIV + PDT + PST + PQ + PLK
. 1/fSW
2 . fSW..vSW
2fSW . vDiL(AVG)fSW
2
. iL(AVG) .
.vG2fSW .
.vSWiL(AVG)fSW .
.vG2fSW .
.vSW
1 5/fSW0 5
DCM: . iL(AVG)
iL(AVG) and fSW Groupings:
. iL(AVG)

2: PR(DC)
. iL(AVG)
1fSW1: PDT, PIV
. 1/fSW2: PR(AC)
. iL(AVG)
1 5/fSW0 5: PR(DCM)
x terms vanish . fSW dominates.
2 and iL(AVG)
1 5 terms dominate.
. fSW1: PG, PSW, PST, PQ
2 term dominates.
Page 19

Power IC Design
Conversion Efficiency
fSW and iOfSW losses rise and
PR(DCM,AC) falls with higher fSW.
. Raise fSW until rise in fSW losses
cancels fall in PR(DCM,AC).
When iO is low, .iL should be low in CCM.
. fSW or LO (volume or ESR) is excessive . DCM is more efficient.
F. Low-Power Design: i. Low-Loss MOSFET
Longer channels LCH reduce leakage and raise resistance and capacitance.
Wider channels WCH reduce resistance and raise capacitance and leakage.
vDS
LCH
WCH
.
PR(MOS)
.
RMOS
=
PG(MOS)
.
CMOS
=
COX"LCHWCH
PLK(MOS)
.iD(TRI)
WCH
LCH
. If PLK is negligible, use LMIN and raise WCH until rise in PG + PLK cancels fa
ll in PR.
PMOS = PR(MOS) + PG(MOS) + PLK(MOS) and PMOS(MIN) when:
.
.
.PMOS
.PR(MOS)
.PG(MOS)
.PLK(MOS)
=
.

+
+
.
=
0
.WCH
WOPT
..WCH
.WCH
.WCH
.
WOPT
Optimize: At half the rated power.
At the power that yields the highest peak efficiency.
At the power that yields the highest mean efficiency across rated range.
Or At most probable power level
This setting can save the most energy.
If RL ESR >> RMOS, PR(MOS) is negligible in .C .
Shorten WCH to save area.
PR = PC
PG = PD
PG, PSW, PST, and PQ are constant over iO.
PG falls with less switching gates.
PR(DC) falls quickly when iO falls.
PIV and PDT fall when iO and fSW fall.
PR(AC) falls quickly when fSW rises.
Page 20

Power IC Design
Design Example
Objective: Determine WOPT for MG in a synchronous buck in CCM when
vIN = 4.0 V, vO = 1.8 V, vD
0.7 V, iO = 250 mA, VTN0 = 0.6 V, LO = 22 H,
RL ESR = 100 mO, RC ESR = 25 mO, tDT = 15 ns, tSW = 1 s, KN' = 100 A/V2,
iOFF = 1 A/10k m at LMIN, COX" = 5 fF/m2, L = 0.25 m, LOL = 50 nm,
Solution:
From previous examples, dE = 45%, tE = 450 ns, .iL = 45 mA,
and .iL(RMS) = 13 mA . dD = 55% and tD = 550 ns.
For minimum PMOS, LCH = LMIN = 0.25 m.
Gate drive vGS for MG is vIN = 4 V.
MG only conducts during tD
REQ
=
RMG
.
.
.
tD
2tDT
tSW
.
.
.
=
RMG
.
.
.
dD
-

2tDT .

2tDT
tSW
..
.
.
And RMG LCHWCHKN'vGS-VTN0()
=0.25WCH(100)4-0.6()
=11360WCH
2(250m)+2(13m)
1360WCH
.
.
.
tD
2tDT
tSW
1
(41.7k)WCH
.
.
..
.
22
+
PR(MG)
(iL(AVG)
.iL(RMS)
)RMG
(52%)

.
.
.
.
=
=
5f
!
\$
CCH
=
0.67COX"WCHLCH
=
WCH(0.25)=
(838p)WCH
#
"
&%
2

"
5f
%
2
'WCH(50n)=
(250p)WCH
=
CGD
#
&
COL

COX"WCHLOL
=
\$
CCH2vIN-VTN0()+COL2vIN+CGD2vDtSW
WCH
72.4
PG(MG)

=
=
WCH
5.49k
tE
tSW
..
.
.
+
vD
.
.
2tDT
tSW
1
10k
.

.
.
.
.
.
.
.
.
.
.
.
PLK(MG)
iOFF
WCH
vIN
.
.
.
.
.
.
.
.
.
.
.
.
.
.

.
.
.
.
=
.
.
.
4
450n
1
.
.
.
+
0.7
30n
1
.PMG
.PR(MG)
.PG(MG)
.PLK(MG)
1
1
1
=
+
+
=
+
2
.WCH
.WCH

.WCH
.WCH
(41.7k)WCH
72.4
+
5.49k
=
0
at WCH = 41.4 mm = 41.4k m . RMG
18 mO and PMG(MIN) 1.1 mW.
. MG can comprise eighty-three 500-m0.25-m gate fingers.
Page 21

Power IC Design
Design Notes
MOS Power: PR(MOS)
.
RCH
.
1
.
TJ
K'(vGS(MAX)
vT
)
vGS(MAX)
vT
2
PG
.
vGS(MAX)
fSW
TJ
PLK
.
X
vT
. Raise gate-drive voltage vGS(MAX) when ohmic loss PR dominates.
Reduce gate-drive voltage vGS(MAX) when gate-drive loss PG dominates.
Reduce switching frequency fSW when ripple ripple loss PR(AC) is negligible.
Use low-vT MOSFETs when leakage loss PLK is negligible.
Use high-vT MOSFETs when leakage loss PLK dominates.
Limit junction temperature TJ Add heat sinks and limit market.
ii. Low-Loss Controller
22
Controller Power: PQ
=
iQvDD
.
fBWvDD
PDIG
=
CEQ
.vG
fCLK
.
vDD

fBW
gm
.
vGS
vT
or
evGS
/nVt
.
iQ
oriQCPAR
pPAR

## . Reduce power supply vDD.

Reduce quiescent current iQ and clock frequency fCLK.
Limit bandwidth fBW Reduce load dump .iLD.
Raise output capacitance CO.
Keep parasitic poles pPAR's within 10fSW pPAR's = 10fBW.
Raise pPAR with low-vT MOSFETs To process analog signals.
Reduce bias iBIAS, but keep above and track Max{iNOISE, iLEAK}.
Suppress noise iNOISE and reduce leakage iLEAK.
Power-down (duty-cycle) blocks when possible May require fast wakeup.
Page 22

Power IC Design
iii. Process Technology
Electric field intensifies with a shorter LMIN . |VGS(MAX)| and |VDS(MAX)| drop.
VTH0 is independent of LMIN.
Process engineers reduce TOX with lower LMIN . COX" and K' rise.
LMIN
0.5 m 0.35 m 0.18 m
N/P-MOS N/P-MOS N/P-MOS
|VGS(MAX)|
|VDS(MAX)|
|VTH0|
TOX
COX"
K' = N/PCOX"
4.5 V
0.86/0.8 V
151
2.3 fF/m2
47/12.5 A/V2
3.3 V
0.5/0.6 V
74
4.5 fF/m2
89/24 A/V2
1.8 V
0.65/0.58 V
45
7.7 fF/m2
135/36 A/V2
Channel resistance RMOS, gate capacitance CG, and gain gm depend on LMIN and COX
".
. Conduction, gate-drive, and quiescent losses and efficiency vary with process
node.
Conduction Loss PR:
Rise in COX" partially offsets drop in |VGS(MAX)| . PR falls with LMIN/WOPT.
LMIN
.
LMIN
PR

.
RMOS
.
COX"WOPT
VGS(MAX)
VTH0
WOPT
Gate-Drive Loss PG:
Rise in COX" offsets drop in LMIN . PG falls with WOPTLMIN2.
2
22
PG
.
CGVGS(MAX)
.
COX"WOPTLMIN
VGS(MAX)
.
WOPT
LMIN
Quiescent Loss PQ:
At-speed circuits (fT > fBW): WCH and LCH fall with LMIN . PQ(BW) with LMIN3.
2
gm(MOS)
.
fBW
.

iQ(BW)
.
LMIN
.
PQ(BW)
=
iQ(BW)vIN
CPAR
.
Slow bias circuits (fT << fBW): iQ(B) is low . PQ(B) falls with LMIN. LMIN
2VDS(MAX)

3
.
LMIN
PQ(B)
=
iQ(B)vIN
.
VDS(MAX)
.
LMIN
iQ(BW)WCH/LCH()
COX"WCHLCH.
iQ(BW)
LMIN
Page 23

Power IC Design
Optimum Width WOPT:
Fall in PR should balance rise in PG .
WOPT climbs with fall in vLMIN.
.
.
.
.
2
.LMIN
.PG
.
.PR
.
.
.=
(COX"WCHLMIN
VDS(MAX)
)
.
.WCH
.WCH
.
COX"WCH
VGS(MAX)
VTH0
..WCH
.WCH
WOPT.1COX"2VGS(MAX)-VTH02VDS(MAX)
.1VGS(MAX)-VTH0.1LMIN
. PR and PG fall with LMIN1 5.
1.5
LMIN
PR

.
.
LMIN
WOPT
2
1.5
PG
.
WOPT
LMIN
.
LMIN
Efficiency improves
with reductions in LMIN,
but breakdown voltages also drop.
G. Other Power Considerations
Power-Supply Example
Power is ultimately lost as heat .
Junction Temperature TJ . PLOSS.
If losses are great,
TJ(MAX) can be excessive.
If necessary, use a heat sink or a cooling fan.
Thermal Effect: Resistances and leakage climb with TJ . PLOSS(MAX) at TJ(MAX).
High-Frequency Operation (for high bandwidth):
Dead time tDT can be significant fraction of period tSW.
. Low-PR benefits of vDS diminish.
PG can surpass diode's iDvD Asynchronous diode can be more efficient.
Page 24

Power IC Design
Channel Lengths: Should be long enough to limit leakage and sustain peak voltage
s.
Light-Load Operation: Synchronous switches conduct negative currents.
. Higher ohmic losses PR
Asynchronous diodes block negative currents.
Skin Effect: iL flows through skin at high frequency.
. RL ESR(HF) > RL ESR0 PR(L ESR) climbs with frequency.
For similar power in a buck, higher vO reduces iO Lower iL(AVG).
Lower
PR
For similar power in a boost, higher vIN reduces iIN Lower iL(AVG).
Controller Ground Current:
Climbs with bandwidth requirements.
Climbs with parasitic capacitance . Depends on process technology.
Buck Boost Circuits: Save gate-drive energy PG
When bucking by keeping SGO open.
When boosting by keeping SI closed.
Configuration:
Energizing into intended receiver and draining from source
conduct power that LO need not store . iL and related PR are lower.
Overlap length LOL is roughly 4 8 lower than LMIN . CGD
CCH/6.
Input Capacitance CIN: Often required because vIN is resistive and slow.
CIN's RIN ESR carries .iIN . RIN ESR consumes ohmic power.
Page 25

Power IC Design
7.4. Frequency Response
A. Small-Signal Concepts
Basics
Bias point (from steady-state response): Averaged signal across cycle SA.
Small-signal response: Determine small-signal variation in SA sa.
Small-signal approximation:
Small-signal variations cause linear changes in SA.
The State of the Art
State-space averaging (SSA): Average electrical equations (e.g., LOdiL/dt).
Circuit averaging: Model averaged equations.
Flow graph: Display flow of averaged equations graphically.
Signal-flow graph (SFG): Average time-domain operation (i.e., waveforms)
and display flow of averaged signals graphically.
Page 26

Power IC Design
B. Continuous Conduction
Non-inverting buck boost stage incorporates all small-signal dynamics:
Switched inductor LO, output capacitor CO, and duty-cycled output.
. General case:
Filter:
CO shunts vO . vO falls with frequency CO pole pC.
CO's RC ESR limits iC .
Arrests effects of pC In-phase LHP zero zLHP.
LO's rising impedance reduces iL . vO falls LO pole pL.
Together, LO and CO introduce a pair of complex poles pLC2 at
Power stage must wait a switching cycle tSW to respond.
. Switching frequency fSW limits closed-loop bandwidth f0dB: f0dB = fSW.
Inductor current iL depends on the voltage across inductor vL: iL = vL/ZL.
vEdE+vD1-dE()
sLO+RLESR
(vE
vD
)dE
+
vD
vL
=
=
sLO
+
RL
ESR
iL
=
sLO
+
RL
ESR
Two-port small-signal Norton-equivalent (short-circuit) current:
vo = 0 and vIN has no small-signal component in vE or vD . ve
vd
#.iL
&
#.iL

0.

&#
&#
&
.iL
.iL
(
=
de
(VE
VD
)
deVL
(+
ve
%
(+
vd
%
(
=
de
%
\$.dE
'\$.vE
'\$.vD
'\$.dE
'sLO
+
RL
ESR
=
sLO
+
RL
ESR
And il
=
de
%
il is the duty-cycled inductor voltage vl = de(VE
. 12pLOCO
. Pole when sLO surpasses RL ESR past pLESR.
Norton-equivalent impedance (when de = 0) is ZLO.
Page 27

## VD) over inductor impedance.

Power IC Design
i. Duty-Cycled Output
DO duty-cycles iL . vo receives fraction of il iDO = iLDDO = iL(1
DE).
Undelivered charge growth .qO(FF) opposes delivered charge growth .qO(FB).
. Out-of-phase (right-half-plane RHP) zero when ido(FF) = ido(FB) = ilDDO.
f >> pLESR
qO(FF)
iL(PK)
(detSW
)
=
ido(FF)
=
sLO >> RL.ESR
tSW
tSW
de
(VE
VD
)
(2pzRHP
)LO
.
.

=
ilDDO
=
.
.
.
vl
ZL

.
.
.
DDO

DDO
.
..
.
..
\$
'\$
'
VLDDO
Past zRHP
&&
VE
VD
&
TO
Small-Signal Variation
%
2pLOiL(PK)
(
)
))
%
TSW
(
)
=
2pLOiL(PK)
When tSW is constant: .dE = de =

.dDO =

ddo.

## LEFF carries with ido what LO carries with il ( > ido).

2
2
LO
LEFF
=
Higher L: EL
=
0.5LO
il
2
=
0.5LO
!
#
"
ido
DDO
\$
&
%
=
0.5LEFF
ido

2
DDO
ii. Signal Flow
Generalized signal flow across feedback path:
vo '
de
ddo

il
ido vo
sLEFF||1sCO+RCESR!
"#
\$
%&
||RODDO AFB
iL(PK)
zRHP
zLESR, pLC
2, zCESR
pLESR
1
VLZL=VE-VDsLO+RLESRSmall-Signal
Equivalence
Controller
DDO in LEFF = LO/DDO
2 is 1
when not duty-cycled.
Page 28

Power IC Design
iii. Frequency Response: Buck
VL = VE
VD = (VIN
VO)
(0 VO) = VIN
CCM
LO is not duty-cycled . No zRHP and ZLO = sLO.
vo '
de
il vo
sLO||1sCO+RCESR!
"#
\$
%&
||RO AFB
Signal-Flow Graph:
zESR = 1/2pRC ESRCOpLC
2 = 1/2pvLOCO
zLESR pLESR
VLZL=VINsLO
Boost
If iL(AVG) >> .iL . iL(PK)
iL(AVG).
If RO
vO/iLD, where iLD = iL(AVG)DDO.
VL = VE VD
= (VIN 0)
(VIN VO)
= VO
zRHP=VLDDO2pLOiL(PK)
=VODDO2pLOiL(PK)
vo '
de
ddo
il
ido vosLEFF||1sCO+RCESR!
"#
\$
%&
||RODDO AFB
iL(PK)
Signal-Flow Graph:
zESR = 1/2pRC ESRCO
pLC
2 = 1/2pvLEFFCO
zLESR
pLESR
1
VLZL=VOsLODuty-cycled LO . zRHP and LEFF = LO/DDO
2.
RO2DDO2pLO
Page 29

Power IC Design
Buck Boost
VL = VE
VD = (VIN
0) (0
VO)
=VIN+VOsLODuty-cycled LO . zRHP and LEFF = LO/DDO
2.
Signal-Flow Graph:
pLC
2 = 1/2pvLEFFCO
zLESR
VLZL
zRHP=VLDDO2pLOiL(PK)
=
VIN+VO()DDO2pLOiL(PK)
vo '
de
ddo
il
ido vo
DDO AFB
iL(PK)
sLEFF||1sCO+RCESR!
"#
\$
%&
||ROpLESR
1
zESR = 1/2pRC ESRCO
C. Discontinuous Conduction
Duty Cycle:
ttTt
EE
Ee
dE
=
.
DE
=
=
tC
tSW
TC
tc
LO delivers all charge .qL before tSW ends.

.qL
io
=
TSW

iL(PK)tc
iL(PK)
=
TSW
TSW
#
%
\$
deTC
DE
&
(
'
Small-Signal Variation
tE and tD both rise or fall proportionately . vl = vEte + vDtd = 0 because vD <
0.
.
il
=
vl
=
0
No inductor pole pL LO behaves like a resistor.
sLO
LO loads io only when LO conducts, across tLO's portion of tC and tSW.

!
'
*
\$
vT
LO
%
"
%"
vT
tSW
tSW
qT
=
0.5tLO
=
vT
\$
'
=
LO
\$
2
tLO
ZLO
=

=
RL(DCM)
=
fi(
LD)
#"

)
(
&
%
'
,+
iT
0.5tLO
#
qT
&
#
&
diLdt=
vTLO
Page 30

Power IC Design
Signal Flow
vo '
de
ido vo
AFB
RL(DCM)||1sCO+RCESR!
"#
\$
%&
||ROiL(PK)
TSW!
"
##
\$
%
&&
TCDE!
"##
\$
%&&
tc
vl = 0 in DCM . No pL, ZLO
RL(DCM), and all of ql reaches vo . No zRHP.
Generalized signal flow across feedback path: pC = 1/2pREQCO
zESR = 1/2pRC ESRCO
DCM
RL(DCM)=LOtSW0.52tLO!
"#
\$
%&
=LO2DDO!
"#
\$
%&
tSW20.5tC!
"#
\$
%&
Not Duty-Cycled: tLO = tC and DDO = 1. Duty-Cycled Output: tLO = tDO = tCDDO.
!
tSW
=
LEFF
#"
0.5tC
2
D. Summary
Circuit must wait tSW to respond f0dB = fSW.
RO is not always vO/iO, but can be close.
LOCO introduces complex pair of poles pLC2:

## CO shunts vO . vO falls with frequency CO pole.

LO's rising impedance reduces iL . vO falls with frequency LO pole.
RC ESR current-limits CO .
Arrests pC's effects In-phase LHP zero.
In DCM, tevE and tdvD both rise with de . vl = tevE + tdvD = 0 No LO Pole.
Duty-Cycled Output
In CCM: DO duty-cycles iL io = ilDDO.
.qO(FF) counters +.qO(FB) Out-of-phase RHP zero.
In DCM: All of .qL reaches vO .
.qO(FF) = 0 ido = il and no zRHP.
\$
&
%
Page 31

Power IC Design
7.5. Feedback Control
A. Context
Objective: Regulate vO about vREF with shunt negative feedback.
Compensation:
Ensure loop gain ALG has a dominant low-frequency pole,
Challenges:
LO's pole, CO's pole, and a possible RHP zero.
Keep all parasitic poles above f0dB.
Typical Control Method:
Compare vO and vREF and amplify error vE.
.ALG reaches unity-gain frequency f0dB with less than 180 of phase shift.
Regulating loop processes analog vO and vE and digital pulse train dE.
Loop must wait one cycle to respond Closed-loop bandwidth = f0dB = fSW.
Page 32

Power IC Design
B. Duty-Cycle Modulation
Fixed Frequency:
.
Times tD and tE change by same amount.
Popular because switching noise is fairly predictable at fSW.
Popularly known as pulse-width modulation (PWM).
When adjusting peak iL(PK+) or iL(PK ), tE and tD also change.
Popularly known as peak-current control.
Fixed Energizing Time:
. Switching period tSW changes by same amount.
Popularly known as constant on-time control.
Fixed Drain Time:

## . tSW changes by same amount.

Popularly known as constant off-time control.
Fixed Current Ripple:
Shift both peaks iL(PK+) and iL(PK ).
. tE, tD, and to a lesser extent, tSW change.
Popularly known as hysteretic control.
If vO rises and falls with iL:
Ripple voltage .vO or peak voltages vO(PK+) or vO(PK ) can set tE and tD.
Page 33

C. Voltage Mode
Compensation Strategies
Add very low-freq. pole: pLF << f0dB' < pLC
2, zRHP . Low f0dB'.
Add low-freq. pole and zero: pLF << f0dB", zLHP, pLC
2 < zRHP . f0dB'' > f0dB'.
Add zero to recover phase: pLC
2, zLHP < f0dB''' < zRHP . f0dB''' > f0dB''.
Use RC ESR: High f0dB, but with higher output ripple .vO.
Operate in DCM: No pL and no zRHP . pC << f0dB'''' > f0dB'''.
But, output current iO is low or .iL is high.
In pseudo DCM (PDCM): Short LO (i.e., vL = 0) to emulate DCM.
vL . diL/dt = 0 .
.iL = 0, but iL . 0.
SL conducts iL(PK ) . Lossy Lower .C.
Power IC Design
i. Fixed Frequency
Pulse-Width Modulation (PWM):
Error modulates duty cycle dE with a constant switching period TSW.
AERR compares vO to vREF to generate error signal vERR.
RC network establishes low-frequency pole pLF and maybe a zero zLHP.
CPPWM pulse-width modulates switching network according to error vERR.
ALG=ARCAPWMAPWR=verrvo!
"#
\$
%&
deverr!
"#
\$
%&
vode!
"#
\$
%&
pLF << f0dB, pLC
2, zLHP < zESR << zRHP.
ARC0, pLF, zLHP
APWM0, APWR0, pLC
2, zESR, zRHP
.vO and therefore .vERR are small in steady state.
Page 34

Power IC Design
Pulse-Width Modulator
vERR changes slowly across several cycles because pLF << f0dB < fSW.
Comparator CPPWM compares vERR with a sawtooth vSAW clocked at fSW.
Output vCPO is high when the period TSW begins tE starts.
vCPO falls when vSAW surpasses vERR tE ends.
Clock fSW resets vSAW below vERR . vCPO rises and cycle repeats.
CPPWM's propagation delay tP << tE and TSW APWM's pPWM > fSW >> f0dB.
te
dtE
.tE(MAX)
TSW
.dEde
te
1
=
=

.
APWM0
=
v
err
dvSAW
.vSAW
VSAW(PP)
.vERR
verr
verrTSW
vSAW(PP)
Constant On Time:

## ii. Fixed Energizing Time

ALG=AERRAPWR=devo!
"#
\$
%&
vode!
"#
\$
%&
AERR0
APWR0, pLC
2, zESR, zRHP
pLC
2, zESR < f0dB << zRHP.
zESR recovers phase after pLC
2 . RC ESR > RC ESR(MIN) > 0 vO . iL.
SR flip flop decouples energizing (set) from drain (reset) commands.
Feedback sets dE and vO(MIN) and "one shot" resets dE and vO(MAX).
CPERR senses vO(MIN) to generate an error vERR that ends drain time tD.
Page 35

Power IC Design
One-Shot Control
RC ESR > RC ESR(MIN) > 0.
. vO falls with iL until vO drops to vREF.
CPERR ends tD to start another TE.
vT is zero when vQ is low across tD.
CPERR sets vQ to start "one shot" and TE.
IB charges CT until vT reaches vREFT.
CPT ends TE to start tD.
.
td
dtD
dtD
LO
=
=
vo
dvO
diLRC
ESR
vDRC
ESR

!
\$
&&%
TE
TE
=
tSW
TE
+
tD
vREF
TE
=
C

T
dE
=
##"
I
B
de
ddE
=
dtD
dvO
!
\$
dtSW
&%
!
\$
dtD
ddE
dtSW
LO
vDRC
ESR
\$
&
%
1
()

-TE
!
\$
!
!\$
&
%
=
#
"
AERR
=
#
"
&
%
#
"
#
"
#
"
&
%
=
2
vo
dvO

TSW
D. Current Mode
Concept: Regulate iL past f0dB to perceive LO's iL as current source up to f0dB.
Feature: Eliminates small-signal dynamics in iL Removes LO's pole pL.
Loops: Inner loop regulates iL(LF) up to inner loop's bandwidth fI 0dB.
Outer loop regulates vO up to outer loop's bandwidth f0dB.
Feature: No pL . zESR can be high RC ESR and therefore .vO can be low.
Requirements: fI 0dB constitutes a pole in system's loop gain ALG.
. fI 0dB > f0dB and CO's pole pC << f0dB = fI 0dB = fSW < zRHP.
Inner loop must be stable.
Page 36

Power IC Design
%
&'
+ilZO.vLZL.vO"
#\$
%
&'
=
deVE-VD()
ZL-ZO.vL.vO"
#\$
%
&'
RL ESR, RC ESR << RO: CO shunts RO (zCO), ESR's then current-limit CO (pCESR), a
nd
LO overwhelms ESR's (pLESR) AI LG reaches f0dB at 20 dB/dec. . Stable.
IFBAVDVLZL-ZO.vL.vOIFBAVDVE-VD()
sLO+RLESR+1sCO+RCESR"
#\$
%
&'
||RO*
+,
./
DDOvIN does not carry feedback signals vin in vE and vD disappears.
LO may not energize to vO (like in boost), but always drains to vO . vL = f( vO).
ilde:
ZO fraction
when duty-cycled.
.vL.vO=
-1Buck-DDODuty-CycledOutput...
..
...
..
=-DDOvL=vEdE+vDdD
i. Current-Loop Stability
Loop Gain:
"
il
%
=
'
AI
LG
=
I
FBAVD
\$
=

de
#
&
"
vL
.iL
%
".iL
%"
VE
VDiL
=
'
=
de
\$ZL
#.dE
&
vo=0
#.vO
&
de=0
#
ZL

il
=
de
\$
'
+
vo
\$
ii. Closed-Loop Response
Loaded Voltage Gain vo/verr = AERRAG CLDDO[(ZL CL/DDO
ilde%
&'
=AVDVLZL"
#\$
%
&'
=AVDVE-VDsLO+RESR"
#\$
%
&'
1IFB 1IFBWhen ALG >> 1 Up to fI 0dB.

ZLCL=sLO+RLESR()1+ALG()
I FBAVDVL up to fI 0dB Resistor
sLO + RL ESR
sLO past fI 0dB Inductor
CO shunts ZL CL's I FBAVDVL/DDO
2 and RO at
Two-Port Equivalent:
Feedback effects disappear past fI 0dB ALG FBAVDAI.LG = 10 =FBAVDVL
pC = 1/2p(10)(40F) = 400 Hz
fI.0dB = 10/2p(1H) = 1 6 MHz
Current Loop's
Closed-Loop
"
de
%"
'
AGOL
vo=0
=
\$
\$
#
verr
&#
AG
CL
=
AG
OL
||
2) || ZCO || RO].
1
pC

.
2
2p
\$%
(I
FBAVDVL/
DDO

||RO
&'
CO
)
#
&
(=1.
%
VL
\$sLO
'FBAVDVL
fI.0dB
2pLO
Page 37

Power IC Design
iii. Average Current Mode
Regulate LO's average current iL(AVG) and adjust dE with a constant TSW.
Average Current Mode:
AERR compares vO and vREF to generate error vERR that adjusts iL(AVG).
RC network converts and averages iL to a voltage vI
iL(AVG)REQ.
AI compares iL(AVG)REQ and vERR to generate an error vIE that adjusts dE.
ALG=AERRAGCLDDOAZO=verrvo!
"#
\$
%&
ilverr!
"#
\$
%&
ioil!
"#
\$
%&
voio!
"#
\$
%&
RC's pole pI slows fI 0dB . Slows f0dB.pC << f0dB = fI 0dB < fSW < zRHP.
AERR0, 1/I FB0, fI 0dB
RO EQ, pC, zESR, zRHP
Closed-Loop Response
("
1
%+
vIE
=
*vERR
iL
\$RS
||
'-AI
)#
sCF
&,
Operation:
RS senses and CF averages iL Feedback only processes average.
AI shifts and adjusts vIE according to vERR and vI(AVG).
CPPWM adjusts dE according to vIE.
fCLK ends tD to set TSW and start another tE.
Current loop reduces error vERR
il
1

## vI(AVG) towards 0 up to fI 0dB .

1
=
vERR
vI(AVG)
=
iL(AVG)RS
and
verr
I
FB0
RS
Page 38

Power IC Design
iv. Peak Current Mode
Peak Current Mode:
Loop delay plus iL's slew time << TSW . Loop regulates iL(PK+) within TSW.
pC << f0dB = fI 0dB
fSW < pCP, pLESR, zRHP f0dB can be higher.
ALG=AERRAGCLDDOAZO=verrvo!
"#
\$
%&
ilverr!
"#
\$
%&
ioil!
"#
\$
%&
voio!
"#
\$
%&
AERR0, 1/I FB0, fI 0dB
RO EQ, pC, zESR, zRHP
Regulate LO's positive peak current iL(PK+) and adjust dE with a constant TSW.
AERR compares vO and vREF to generate error signal vERR that adjusts iL(PK+).
SR flip flop decouples energizing (set) from drain (reset) commands.
Feedback resets dE and iL(PK+) and clock fCLK sets dE and iL(PK ).
RS converts iL to voltage vI and CPI compares iL(PK+)RS and vERR to end tE.
!
#
"
Closed-Loop Response
vI = iLRS . vI rises and falls with iL.
vI(PK+) = iL(PK+)RS and vI(PK ) = iL(PK )RS.
Operation:
vI(PK+) feedback into CPI resets dE.
fCLK sets dE and starts another cycle.
Current loop reduces CPI's error vERR
Constant TSW
Energize Slope

Drain Slope
1
LO
1 VD
%

## vI(PK+) towards 0 within TSW.

"
%"
il(pk+)
+
il(pk-)
il(pk+)
VD
'\$1te td
'
verr RSVE
LO
il(pk ) il
=il(pk+)
2
=
#
\$
2
&#
VE
&
1-

iL(PK+)RS
il(pk+)
\$
&
%
&
il
il
1
1

vERR

VD
!
#
"
=
.
il(pk+)
RS
2
VE
verr
verr
\$
!
!
\$
&
%
#
"
##"
&
%
,
\$
\$

!
)
.

&
%
&
%
#
"
+
*
Page 39

Power IC Design
Sub-Harmonic Oscillations
Load dumps to vIN or vO can vary diL/dt enough to produce an imbalance .i0 in LO
.
With peak-current control and a constant period TSW,
tE variations cause equal, but opposite changes in tD
.tE = .tD.
.i0 varies tE, which changes tD to produce another imbalance .i1 .
Buck
"%"
%"%
vD
-vO
dE
.i1
=
.i0
\$
'
=
.i0
\$
'
=
-.i0
\$
'
\$
'\$
'
TSW = Constant #
vE
&#
vIN
vO
&#1dE
&
dE = vO/vIN

'\$
.
When dE = 50% vO = 0.5vIN
.i1 = .i0.
Each cycle reproduces an opposing imbalance that sustains oscillations.
LOvE.i0 .tE .tD
1 vDLODrain SlopeEnergize Slope
Boost: vD = vIN
vO, vE = vIN, vIN = vO(1 dE) Same .il and issues at dE = 50%.
iL(PK+) is
stable and accurate,
but not iL(PK ).
When dE < 50% vO < 0.5vIN in buck and vIN < 0.5vO in boost |.i1| < |.i0|.
. Imbalance diminishes across cycles Oscillations fade.
When dE > 50% vO > 0.5vIN in buck and vIN < 0.5vO in boost |.i1| > |.i0|.
. Imbalance grows across cycles Oscillations grow.
.i1=-.i0dE1-dE#
\$%%
&
'((
Page 40

Power IC Design
Slope Compensation
Fix: Reduce .i0-to-.tE translation by accelerating energizing rate.
How: Subtract offset .iOS and vD/2LO slope
Add .iOS and vD/2LO to vERR/RS.

## Compensating iL(PK) slope projects .tE.

#.i0
&#
vD
&
.iE
=
-%
(%
(
((
"-1
.tE
vD2LO
\$
2
'\$
%
vE
0.5vD
'
vE
vD
%
.tD
'
.i0
vD
#
&
-\$
#
LO

2LO
&
1
vD
TSW = Constant L.iD
=
.i0
%%
(
((
Combined Slope O
\$
vE
0.5vD
'Drain slope projects .tD.
.
".i0
%"
vD
%
"-dE
%
.i1
=
.iE
+
.iD
=
\$
'
=
.i0
\$
'
<
.i0
Because 2
#
2
'&
\$
#
vE
0.5vD
&#
2-

dE > 1.

dE
&

. Imbalance diminishes.
For buck, boost, and Buck Boost.
Circuit Realization
Dampen iL(PK )'s sub-harmonic oscillations with slope compensation.
Slope-Compensated Peak Current Mode:
AERR compares vO and vREF to generate error signal vERR that adjusts iL(PK+).
SR flip flop decouples energizing (set) from drain (reset) commands.
Feedback resets dE and iL(PK+) and clock fCLK sets dE and iL(PK ).
RS converts iL to voltage vI.
Summing CPI adds vD/2LO slope to iL(PK+)RS and compares vI and vERR to end tE.
Slope compensation is only needed when dE = 50%.
Page 41

Power IC Design
Approximating
Linear Response
v. Hysteretic Current Mode
ALG=AERRAOSCDDOAZO=verrvo!
"#
\$
%&
ilverr!
"#
\$
%&
ioil!
"#
\$
%&
voio!
"#
\$
%&
pC << f0dB = pI BW = fOSC = fSW < zRHP.
AERR0, AOSC0, pI BW
RO EQ, pC, zESR, zRHP
pI BW
fOSC = fSW is possible . High.
f0dB
A hysteretic (relaxation) oscillator sets a constant current ripple .iL.
The voltage loop adjusts LO's average current iL(AVG).
Hysteretic Current Mode:
AERR compares vO and vREF to generate error vERR that adjusts .iL's iL(AVG).
RS converts iL to voltage vI.
CPI keeps iL within hysteresis limits to set oscillating ripple .iL.
Closed-Loop Response
Hysteretic Comparator CPI: iL rises until iLRS reaches vERR + 0.5VHYS to reset d
E.
iL falls until iLRS reaches vERR

VHYS
iL(AVG)
il
1
=
.iLRS
VHYS
.
.iL
iL(AVG)RS
vERR
.
AOSC0

## 0.5VHYS to set dE.

=
RS
vERR
verr
RS
CPI responds to vERR within one clock cycle,
but iL's diL/dt slews and delays the response, like a pole would.
Bandwidth limited.
Page 42

Power IC Design
Modeled Response
Bandwidth Model: REQCEQ time-constant models delay.
Time required for iL to slew to its target depends on load dump .iO(LD):
%"
"
%"
%
.iL(AVG)
LO
.iLD
LO
tL
=
'
=
\$
'\$
'
=
.iL(AVG)
\$
diL/dt
#
vL
&#
DDO
&#
vL
&
REQCEQ requires four time constants to reach 98% of its target:
"
%
14
t=
RCln\$

'
=
4RC=
RC
EQEQ
#10.98&
EQEQ
2ppI.BW
REQCEQ pole models the oscillator's bandwidth pI BW.

## Since rising time tL+ differs from falling time tL ,

pI BW should reflect the worse of the two tL(MAX) = Max(tL+, tL ).
#
&
&*Min
vE,vD
.
pI
BW
=%
#
4
&
1
#
4
&#
DDO
()
=
%
(,
\$
2p'\$
tL(MAX)
(
(('
\$
2p'(

\$
%
.iLD
'+
LO
./
(%%
Lowest vE and vD and highest .iLD and LO limit response.
Compact Realization
Reduce AERR to 1 and feed vO directly into CPERR.
Remove current-loop interference from voltage loop Reduce current's ALG I0.
Operation:
At low frequency, vI(LF)
vI(AVG)
0
ALG I0 << 1.
. CPERR compares vO and vREF to adjust iL's low-frequency component iL(AVG).
As CF shunts past zF, vI vI(AVG) rises
ALG I climbs past zF.
ALG V should drop to f0dB before the oscillator's pI BW, which is below fOSC.
. Near fOSC, vREF(HF)
vO(HF) 0 and oscillator's ALG I is undiminished.
CPERR fixes iL's ripple .iL about iL(AVG). VHYS
.iL

RS
||RF
vI(AVG)
iL(LF)RS
iL(AVG)RS
zF, pC << f0dB = pI BW = fOSC < zRHP.
1
<<
fOSC
zF
=
2p(RS
+
RF
)CF

Page 43

Power IC Design
E. Digital Control
Replace analog front end with an analog-to-digital converter (ADC).
Use digital-signal processor (DSP) to adjust dE according to vO's error.

## Feature: DSP can program modes, process multiple outputs, and

compensate response with less dc quiescent power.
Drawbacks: DSP occupies substantial silicon area.
Switching gates in DSP require considerable gate-drive power.
DSP requires many clock cycles to process an output.
f0dB = fSW << fCLK . Load-dump response is usually slow.
For a faster response, DSP should only adjust the loop variables,
not be in the feedback path.
F. Summary
Control Objective: Establish dominant low-frequency pole.
Voltage Mode: Adding a dominant pole slows loop response.
zESR recovers phase, but requires RC ESR
.vO is usually higher.
DCM and PDCM exclude pL and zRHP,
but DCM limits PO or PDCM burns additional power.
Pulse-width modulation (PWM) fixes fSW,
but responds after several switching cycles f0dB << fSW.
Current Mode: Regulates iL . LO behaves like a current source up to fI 0dB.
Splits pLC2: pC < pLC2 < f0dB = fI 0dB = pL = fSW < zRHP.
. Usually faster than voltage-mode converters.
No need for RC ESR's zESR, but must sense iL Higher power losses.
Hysteretic and peak currents respond within one or two cycles,
but .iLD, vL, and LO limit pI BW and peak requires slope compensation.
Digital Control: Flexible, but also often slow and area intensive (costly).
Page 44