Libraries

Input data Required for Physical Design

File Format
Technology file (.tf in synopsys format and
.techlef in cadence format)
Physical Libraries (In general Lef of GDS file
for all design elements like macro, std Cell, IO
pads etc., and in synopsys format .CEL,
.FRAM views for the above)
Timing, Logical and Power Libraries (.lib
(liberty file) or
LM view
-.db or
for.io)
all design elements)
TDF
file (.tdf

Constraints (.sdc)
Physical Design Exchange Format PDEF
(optional)
Design Exchange Format DEF (optional)
Output data from Physical Design Tool
File Format
Standard delay format (.sdf)
Parasitic format (.spef, .dspf)
Standard parasitics Exchange Format
Verilog/VHDL simulation libraries (.v)
Physical Layout (.gds)
Library Exchange Format (.lef)
Design Excahnge format (.def)

File Content
It describes the units, drawing patterns, layers
design rules, vias, and parasitics resistance and
capacitance of the manufacturing process
Contains complete layout information and
Abstract model for placement and routing like
pin accessibility, blockages etc.,
Contains Timing and Power info
Contains pad or pin arrangements like order
and location of the same. For full chip the
instantiation of VDD and VSS pads Power Cut
diode etc., (Whichever is not available in
verilog netlist)
Contain all design related constraints like Area,
power, timing
Contains, row, cell placement locations etc.,
Contains, row, cell placement locations etc.,

File Content
Timing Details (Except load info)
Resistance and Capacitance info of cells and
nets (used in STA analysis)
Contains connectivity info of all cells
Physical Layout info
Contains design rules, row, cell, net placement
locations
etc.,

Libraries in Physical Design

Technology libraries are integral part of the ASIC backend EDA tools. Important two libraries are
briefly explained below.
1. Technology File Libraries
Technology file defines basic characteristic of cell library pertaining to a particular technology node.
They are units used in the design, graphical characteristics like colors, stipple patterns, line styles,
physical parameters of metal layers, coupling capacitances, capacitance models, dielectric values,
device characteristics, design rules. These specifications are divided into technology file sections.

2. Standard Cell Libraries, I/O Cell Libraries, Special Cell Libraries

A standard cell library is a collection of pre designed layout of basic logic gates like inverters,
buffers, ANDs, ORs, NANDs etc.
All the cells in the library have same standard height and have varied width.
These reference libraries are technology specific and are generally provided by ASIC vendor like
TSMC, Artisan, IBM etc. Standard cell height for 130 TSMC process is 3.65 M.
In addition to standard cell libraries, reference libraries contain I/O and Power/Ground pad cell
libraries. It also contain IP libraries for reusable IP like RAMs, ROMs and other pre-designed,
standard, complex blocks.
The TSMC universal I/O libraries include several power/ground cells that supply different voltages
to the core, pre-drivers and post drivers. Internal pull-up or pull-down is provided to some cells in
I/O libraries