Professional Documents
Culture Documents
DFT Compiler(Synopsys)
level description or netlist to the target design library and optimizes for speed, area or power
consumption.
In Appendix- A a list of major EDA tools vendors is given. The objective is to provide a tool set for FPGA
/ ASIC design such that the number of vendors to design and build the ASIC /r FPGA is minimized. Each
vendor brings a new set of learning curves, maintenance and interfaces that eventually end up spending
more time and money. Tool maturity is another important factor. New tools almost always come with
certain number of bugs and issues.
Virtuoso(Cadence) - IC Layout