1) Different ASIC flow in details

2) Scope of various tools in whole ASIC flow

3) concept of libraries used at various stages and their purpose
4) Synthesis of RTL codes
5) Various timing aspects used during Synthesis
6) DFT basics

1) there are mainly two asic flows top down flow and bottom up flow. You can get n number of documents from
web. What u need to know here is the difference between these two flows and advantage of one over other.
You are also required to study when one is preferred over other

2) If you search for EDA tools in Wikipedia you will get a page where all the tools are listed. Go through them.
The intent here is you should know what are different tools available for different stages of IC design. For
example; for circuit design you have tanner, eldo, virtuoso for Synthesis you have RTL compiler, DC etc

3) here the intention is you should know libraries used in different stages of IC designing and what are there
contents. For example when you are designing circuit you need bsim transistor libraries where as for Synthesis
you need .lib

4) for this you can read Synthesis chapter from any RTL (vhdl or verilog ) book. The intention here is you
should know how your RTL codes produces circuit. How circuit is impacted when there is a change in RTL. For
example how if else is different from case statement in terms of Synthesis

5) solve timing example from web. The intent here is given a circuit you should be able to predict clock period,
when setup violates etc. Read about skew slew jitter etc

6) study DFT basics like what is scan chain and how it helps in testing. What is controllability and what is
observability. What is struck at 0 and struck at 1