entity moorey1 is

Port ( reset : in STD_LOGIC;

clk: in std_logic;
seq_in : in STD_LOGIC;
seq_out : out STD_LOGIC);
end moorey1;

architecture Behavioral of moorey1 is

begin

(remove it)

type state_type is (a,b,c,d,e,f,g);

signal state: state_type :=a;
begin
process(clk)
begin
if(reset='1')then
seq_out<='0';
state<=a;
elsif(rising_edge(clk))then
case state is
when a=>
if(seq_in='0')then
seq_out<='0';
state<=c;
else
seq_out<='0';
state<=b;

end if;
when b=>
if(seq_in='0')then
seq_out<='0';
state<=d;
else
seq_out<='0';
state<=b;
end if;
when c=>
if(seq_in='0')then
seq_out<='0';
state<=c;
else
seq_out<='0';
state<=e;
end if;
when d=>
if(seq_in='0')then
seq_out<='0';
state<=f;
else
seq_out<='0';
state<=e;
end if;
when e=>

if(seq_in='0')then
seq_out<='0';
state<=g;
else
seq_out<='0';
state<=b;
end if;
when f=>
if(seq_in='0')then
seq_out<='1';
state<=a;
else
seq_out<='0';
state<=e;
end if;
when g=>
if(seq_in='0')then
seq_out<='0';
state<=c;
else
seq_out<='0';
state<=e;
end if;
when others=>
null;
end case;

end if;
end process;

end Behavioral;