8085 P

Architecture and Pin details

1.

Memory :

14.

Ready : For Handshaking withSlow Peripherals

8Data Lines

Ready : Ready=1 NormalOperatio n

Ready=0 Wait State

16 Address Lines

Memory ( 216 8 ) bits=26 210 8 bit

15.

64 1024 1 Byte=64 1 K B

IO/ M

10

Memory 64 KB1 KB=2 8 bits

2.
3.

Frequency of Crystal=6.144 MHz

Frequency of P=

Frequency of Crystal
=3.072 MHz
2

4.
8bit Registers : B , C , D , E , H , L, FR ( Flag Reg ) , A ( Accumulator )
5.

16bit Registers : PC , SP , PSW

6.

Register Pairs ( 16bit ) : B ( BC ) , D ( DE ) , H (HL)

7.

Registers not accessible Programmer :W , ZTemp Reg

8.

Read Only Register : PSW

9.

Special Purpse Register : PC , SP(Ordinary data can t be stored )

10.

HL Pointer Present Memory Location

11.
12.
S

Status Lines : S 0 , S 1
S1

M /C

S0

Memory Write

Memory Read

Opcode Fetch

I /O Write

I /O Read

Interrupt Acknowledgement

Halt

16. Simultaneous operationidle condition of RD WR are Invalid

IO/ M

WR
3:8 Decoder
RD
O/ P

'

Invalid

MEMR

Program Status Word ( PSW 16 ) : ACC 8 Flag Reg 8

MEMW

Flag Register : Affected by only ALU Result

Invalid

Invalid

IOR

AC

CY

ALU Result
ve (Signed Nos)

MSB=1(Unsigned Nos)
00 H
CarryBorrow occurs

one nibble another nibble

Even Parity

CarryBorrow occurs

13.

IOW

S=1

Invalid

Z =1

17.

FLAG

AC=1

Interrupt

P=1

TRAP

CY =1

DMA ( Direct Memory Access ) : I / p Devices with DMA

controller uses AddressData buses directly accessmemory

HOLD=1 Request
HLDA =0 acknowledgement
Device P P Input Device
Input

Hardware Interrupts :
Vector

Masking

Triggering

0024 H

NMI

( +ve edge ) +level

RST 7.5

003 C H

Maskable

+ve edge

RST 6.5

0034 H

Maskable

level

RST 5.5

002C H

Maskable

level

NVI

Maskable

level

( RST 4.5 )

INTR

Priority

Highest

Lowest

Address

INTA : Acknowledgement P the interrupt

MemoryI /O

2.

1.

Memory Expansion : Decoder isused

Given
Required
No. of Memory I C' s required=

Memory Description :

e . g . N KB isexpanded M KB i. e . 2 B 2 B then ,
1 Byte=1 memory location

No. of Memory I C' s required=2mn

10

1 KB=2 Bytes=1024 memory locations

i

10

N KB=2 2 Bytes=2

i+10

Decoder Used=( mn ) 2m n Decoder

memory locations

n=i+10 no . of Address Lines

3.

Memory Mapping : Decoder is used

Chip Select should be enabled first

If Starting Address ( SA )=00 000H

Foldback Memory : ( Duplicate Address )

n

then, Ending Address ( EA )=11 111H =( 2 1 )10

Due Decoding , naddress lines are unused

Offset=EA

which results2 foldback memories

Offset =( 2n1 )10

4.

Memory Mapped I /O Mode : I /O Device is considered as Memory .

If SA 00 000 H

16 Address Lines are shared by both Memory I /O Device .

then EA=SA +Offset

Total Memory is distributed among Memory DeviceI /O Device .

Offset =EASA
5.

SA=EAOffset

I /O Mapped I /O Mode : I /O Device can be used as a Memoryan I /O

Device itself . 16 Address Lines are given Memory , out of which 8 LSB
Address Lines areshared by I /O Device . Here memory is not distributed .

Using Decoder either Memory can be used I /O device can be used .

Memory Mapped I / O
Parameters
No. of Address Lines

Memory

16 ( A15 A 0 )

I /O Device

I /O Mapped I /O
Memory

I /O Device

16 ( A15 A 0 )

8 ( A7 A 0 )

Decoder is not required :

Control Signals

=Unused
IO/ M

RD= MEMR
MEMW

WR=

MEMR

MEMW
Memory

Memory Memory + I / O Device Memory

NO . of I /O Devices

64 KB

Instructions Set Basics

3 :8 Decoder is required

MEMR

MEMW

IOR

IOW
8

Memory 64 KB

No. of I /O Devices=2 =256

Memory 256 Bytes

1.

Von Newman Architecture: DataProgramboth is stored

4.

the Memory

2.

Fetch Cycle ( F /C ) : No. of Memory access (No. of F , S , R , W , I , O)

5.

Address of a

Opcode of an Instruction

Memory Location

8 bit Data

ExecutionCycle ( E/C ) : No .of Memory access ( No . of F , S , R , W , I , O )

at the time of Execution inside P

6.

M /C=F /C + E /C

7.

1 Byte Instruction :Only Opcode ( No Intermediate Data )

InstructionCycle ( I /C ) :Time required execute an Instruction

Represented Machine Cycle ( M /C ) : I /C=1 M /C 5 M /C

1 Byte 1 F /C 1 M / C
3.

E . g . MOV C , A

Machine Cycle(M /C) :Time required complete one operation

of accessing memory accessing IOsending

Address

Opcode

an Acknowledge ( DMANVI)

8250 H

4 F H ( Opcode of MOV )

Represented T States : M /C=3 T 6 T

Machine Cycle

POperation

Symbol

8.

2 Byte 2 F /C 2 M / C

States

E . g . MVI B , 2C H

Opcode read
Memory (3 T )

4T

+Opcode Decode (1T )

Opcode Fetch M /C

Opcode read

Memory (3 T )
+Opcode Decode ( 1 T )

6T

Memory Read M /C
Memory Write M /C

Memory
8 bit data Write

9.

Address

Opcode/8 bit Data

8250 H

4 F H Opcode of MVI

8251H

2C H 8 bit Data

3 Byte Instruction:Opcode16 bit Intermediate Data

3 Byte 3 F /C3 M /C

+ Extension(2 T )
8 bit data Read

2 Byte Instruction :Opcode8 bit Intermediate Data

LXI B , 3 F 2 C H
R

3T

Address

Opcode/8 bit Data

3T

8250 H

4 F H Opcode of LXI

8251H

2C H Lower Byte

 Memory

I /O Read M /C

I /O Write M /C

Hold Acknowledge M /C

Acknowledge M /C

8 bit data Read

I /O Device

8 bit dataWrite
I /O Device

Send Ack Signal through

HLDA pin

Send Ack Signal through

INTA pin

8252H
I

3T

10.

3 F H Higher Byte

If No. of PUSH Operations=No .of POP Operations ,

then SP position is intact

O

3T

11.

No. of Opcodes=2No. of Data Lines

12.

P follows Little Endian technique FetchStore 16 bit

Data the Memory respectively . i .e . Lower Byte

is FetchStored first , then Address of the memory is

incremented by 1then Higher Byteis FetchStored

Arithmetic Instructions

1.

Operations happeninside ALU , so all Flags are affected , with few exceptions

2.

If 2 operands are present , then 1 of them must be Accumulator

Legends :

B Bytes
X 16bit RegR p
A Accumulator R P 16bit Reg Pair
M MachineCycles
I 816 bit Immediate Data R 8bit Reg M Data HL R P
T T States

Instructions

Operation

ADD R

A +R A

ADC R

A + R+CY A

ADD M

A +M A

ADC M

A + M +CY A

ADI 8 bit data

A +8 bit data A

ACI 8 bit data

A +8 bit data+ CY A

AR A

SBB R

ARCY A

AM A

SBB M

AM CY A

SUI 8 bit data

A8 bit data A

SBI 8 bit data

A8 bit dataCY A

INR R

R+1 R

DCR R

R1 R

INR M

M + 1 M

DCR M

M 1 M p

M /C

T States

B|M |T

ADD ADC 1 F

4T

1|1| 4

ADD ADC 1 F
M 1R

4T
3T

1|2|7

ADI ACI 1 F
8 bit data 1 R

4T
3T

2|2|7

SBB 1 F

4T

1|1|7

SBB 1 F
M 1R

4T
3T

1|2|7

SUI SBI 1 F
8 bit data 1 R

4T
3T

2|2|7

INRDCR 1 F

4T

1|1| 4

INRDCR 1 F
M 1 R
M 1W

4T
3T
3T

Comments , Registers used

Flags Affected

All Flags are affected

8bit Registers : A , B , C , D , E , H , L

S , Z , P , AC Flags are affected

CY flag isnot afffected

1|3|10

8bit Registers : A , B , C , D , E , H , L

INX RP
INX SP

NO Flags are afffected

RP +1 R P
SP+1 SP

It is a16bit operation which

doesnt happen ALU

DCX R P
DCX SP

RP 1 R P
SP1 SP

INRDCR 1 S

6 T ( S)

1|1|6

( It happens Inc / Dec Latch )

6 T ( S ) FEO is not possible
16bit Registers : B , D , H ,SP
Only CY Flag isafffected
It is a 16 bit operation happens

DAD R P
DAD SP

R P + HL HL
SP+ HL HL

DAD 1 F
Bus Idle 2 B

4T
6T

1|3|10

ALU

Buses are idle for 6 T states as CPU is

busy executing 16bit adition

the form of two 8bit addition

16bit Register pairs : B , D, H

Logic Instructions

1.

Operations happeninside ALU , so all Flags are affected , with few exceptions

2.

If 2 operands are present , then 1 of them must be Accumulator

Operation
Legends : Operation
XOR Operation

T States

Comments , Registers used

Instructions

Operation

M /C

ORA R

A R A

ORA 1 F

4T

1|1| 4

S , Z , P Flags are affected

ORA M

A M A

ORA 1 F
M1 R

4T
3T

1|2|7

CY =0AC =0

B|M |T

Flags Affected

ORI 8 bit data

A 8 bit data A

ORI 1 F
8 bit data 1 R

4T
3T

2|2|7

XRA R

A R A

XRA 1 F

4T

1|1| 4

XRA M

A MA

XRA 1 F
M 1R

4T
3T

1|2|7

8bit Registers : A , B , C , D , E , H , L

XRI 8 bit data

A 8 bit data A

XRI 1 F
8 bit data 1 R

4T
3T

2|2|7

XRA A A=00 H CY =0

ANA R

A R A

ANA 1 F

4T

1|1| 4

ANA M

A M A

ANA 1 F
M 1 R

4T
3T

1|2|7

ANI 8 bit data

A 8 bit data A

ANI 1 F
8 bit data 1 R

4T
3T

2|2|7

RAL

RAR

MSB CY
CY LSB
MSB CY
MSB LSB
LSB CY
CY MSB

RRC

LSB CY
LSB MSB

CMP R

AR

CMP 1 F

4T

1|1| 4

CMP M

AM

CMP 1 F
M 1 R

4T
3T

1|2|7

CPI 1 F
8 bit data 1 R

4T
3T

RLC

CPI 8 bit data

A8 bit data

Program is started with this Instruction

S , Z , P Flags are affected

CY =0AC =1

8bit Registers : A , B , C , D , E , H , L
Only CY Flag isafffected

Operationdoesnt happenALU
1F

4T

1|1| 4

Operationoccurs Accumulator
RLC= A 2
A Condition : Unitl MSB=1
RRC=
2

All Flags are affected

Result is not strored Accumulator

only Flags are affected

2|2|7

CMA 1 F
CMA

A< R ( M ) ( 8bit Data ) CY =1 Z=0

A > R ( M )( 8bit Data ) CY =0 Z=0
A=R ( M ) ( 8bit Data ) CY =0 Z=1
NO Flag is afffected

4T

A A

Operationdoesnt happenALU

1|1| 4

Operationoccurs Accumulator
CMC

CY
CY

CMC 1 F

4T

1|1| 4

STC

CY =1

STC 1 F

4T

1|1| 4

Only CY Flag isafffected

DataTransfer Instructions

Between 2 Registers
Between RegistersMemory
Immediate Data

Immediate Data
Data Transfer is POSSIBLE : { Memory
NO FLAGS ARE AFFECTED
DataTransfer is IMPOSSIBLE : { Between 2 Memory Locations
Instructions

Operation

M /C

MOV R d , R s

Rs R d

F /C : { MOV 1 F

4T

1|1| 4

MOV R d , M

M Rd

F /C : { MOV 1 F
E /C : { M 1 R

4T
3T

1|2|7

MOV M , R s

Rs M

F /C : { MOV 1 F
E /C : { M 1W

4T
3T

MVI Rd ,8 bit data

8 bit data R d

F /C :

1F
{8 bitMVIdata
1R

T States

4T
3T

B|M |T

1|2|7

2|2|7

CommentsRegisters used
No. of F /C=

No. of
Bytes of Instruction

No. of M /C

No. of
Bytes of Instruction

8bit Registers : A , B , C , D , E , H , L

F /C :
MVI M , 8 bit data

8 bit data M

{8 bitMVIdata1 F1 R

E/C : { M 1 W
LXI RP , 16 bit data

16 bit data R P

LXI SP , 16 bit data

16 bit data SP

Instructions

LDA 16 bit address

4T
3T
3T

M /C

( 16 bit address ) A

LDA 1 F
F /C : Lower Byte 1 R
Higher Byte 1 R

4T
3T
3T

E/C : {8 bit data 1 R

3T

A ( 16 bit address )

{
{

2|3|10

3T

Operation

8 bit data A

STA 16 bit address

LXI 1 F
F /C : Lower Byte 1 R
Higher Byte 1 R

4T
3T

T States

STA 1 F
F /C : Lower Byte 1 R
Higher Byte 1 R

4T
3T
3T

E/C : {8 bit data 1 W

3T

3|3|10

B|M |T

( 16 bit address ) A

3|4|13

STAX R P

A ( 16 bit address )

8bit data A

16 bit address should not be

considered as an Immediate Data

( 16 bit address ) ismemory location

3|4|13

having 8bit data

This 8bit data is overwritten

by content of A

16bit Registers Pairs :B , D

F/C : { LDAX 1 F
E/C : {8 bit data 1 R

4T
3T

1|2|7

H Register cannot be used because

Similar Instruction for H : MOV A , M

8 bit data A
A ( ( RP ) )

CommentsRegisters used

( 16 bit address ) contains 8 bit data

(( R P ) ) A
LDAX R P

16bit Registers : B , D , H , SP

16bit Registers Pairs :B , D

F /C : { LDAX 1 F
E/C : {8 bit data 1 W

4T
3T

1|2|7

H Register cannot be used because

Similar Instruction for H : MOV M , A

( 16 bit address ) L
LHLD 16 bit address

( 16 bit address+1 ) H

SHLD 16 bit address

L ( 16 bit address )
H ( 16 bit address+1 )

LDA 1 F
F /C : Lower Byte 1 R
Higher Byte 1 R

4T
3T
3T

E/C : Lower Byte 1 R

Higher Byte 1 R

3T
3T

LDA 1 F
F /C : Lower Byte 1 R
Higher Byte 1 R

4T
3T
3T

E/C : Lower Byte 1W

Higher Byte 1 W

3T
3T

First Lower Byte is fetchedthen

3|5|16

Higher Byte is fetched

16 bit address should not be

considered as an Immediate Data

First Lower Byte is stored then , the

3|5|16

address is increaseby 1then

Higher Byte is stored

(Unlike )

XCHG

HL DE

F /C : { XCHG 1 F

4T

1|1| 4

PCHL

HL PC

F /C : { PCHL 1 S

6 T ( S)

1|1|6

Fetch Execute overlap ( FEO ) is not

possible here , so F /C is extended
6 T states , so that F /C of next

SPHL

HL SP

F /C : { SPHL 1 S

6 T ( S)

1|1|6

instruction doesnt start until these

instructions get executed

Top of the TempRegWZ

HL Top of the
XTHL

L ( 16 bit address )
H ( 16 bit address+ 1 )

4T
3T
3T

3T
3T

XTHL 1 F
F /C : Lower Byte 1 R
Higher Byte 1 R
E/C : Lower Byte 1W
Higher Byte 1 W

HL Top of WZ HL
1|5|16

FEO is possible as SP is not altered .i .e

only ( 16 bit address ) specified by SP
is altered

Instructions

Operation

M /C

PUSH R P

RP H ( ( SP1 ) )

F /C : { PUSH 1 S

T States

6 T ( S)

B|M |T

CommentsRegisters used

1|3|12

First SP is decreased by 1,then the

Higher Byte is stored then , SP is

RP L ( ( SP2 ) )

PUSH PSW

A ( ( SP1 ))

again decreased by 1then

Lower Byte is stored

3T
3T

E/C : Higher Byte 1 W

Lower Byte 1W

(UnlikeSHLD operation)

Flag Byte ( ( SP2 ) )

Latest Position of SP2

16bit Registers Pairs :B , D , H

POP RP

POP PSW

( ( SP ) ) R PL

First Higher Byte is stored , thenSP is

( ( SP+ 1 ) ) RP H

increased by 1, then Lower Byte is

( ( SP ) ) FlagByte

F /C : { PUSH 1 F

4T
1|3|10

3T
3T

E/C : Lower Byte 1 R

Higher Byte 1 R

stored then, SPis again

increased by 1
Latest Position of SP+2

( ( SP+ 1 ) ) A

16bit Registers Pairs :B , D , H

Branching Instructions

PC Register is AFFECTED
Instructions

Operation

M /C

JMP 16 bit address

16 bit address PC

JMP 1 F
F /C : Lower Byte 1 R
Higher Byte 1 R

4T
3T
3T

JC 16 bit address

If CY =1

JMP 1 F
F /C : Lower Byte 1 R
Higher Byte 1 R

4T
3T
3T

16 bit address PC
If CY =0
16 bit address PC

{
{

F /C :

JC 1 F
Lower Byte 1 R

T States

4T
3T

B|M |T

CommentsRegisters used

3|3|10

Unconditional Jump

|32| 107

16 bit address Address of a

subroutineaddress at which

the program is jumping on

During Read Cycle of Lower Byte

JNC 16 bit address

JZ 16 bit address
JNZ 16 bit address

JM 16 bit address
JP 16 bit address

JPE 16 bit address

JPO 16 bit address

Instructions
CALL 16 bit address

If CY =0

J 1 F
F /C : Lower Byte 1 R
Higher Byte 1 R

If Z=1
If Z=0

Other

If S=1

wise

If S=0

16 bit

If P=1

J 1 F
F /C :
address PC Lower Byte 1 R

4T
3T
3T

the

4T
3T

F /C P checks CY Flag . If CY =1 ,then Higher By

If P=0

otherwise , only 1 st two M /C occur

16 bit addr PC

After F /C PC =PC+3

Operation

M /C

PC H ( ( SP1 ) )

CALL 1 S
F /C : Lower Byte 1 R
Higher Byte 1 R

PC L ( ( SP2 ) )
16 bit address PC

Latest SP=SP2

T States

6 T (S)
3T
3T

3T
3T

E/C : Higher Byte 1 W

Lower Byte 1W

B|M |T

CommentsRegisters used

3|5|18

After F /C PC =PC +3

( fetch new instruction)

PC H ( ( SP1 ) )
PC L ( ( SP2 ) )
i. e . PC Top of the

i. e . PC value for the Next Instruction

is stored

After Execution 16 bit addr PC

i. e . PC value for the Next Instruction

is overwrittenby 16 bit addr ess

But still , PC value for the Next

Instructionis stored the so

that whenthe called subroutine is

executed it returns the main

programit POPs the Top of the

store it PC so that again the

main program is executed

If CY =1
PC H ( ( SP1 ) )
PC L ( ( SP2 ) )
CC 16 bit address

16 bit address PC

6 T (S)
3T
3T

3T
3T

CALL 1 S
F /C : Lower Byte 1 R
Higher Byte 1 R
E/C : Higher Byte 1 W
Lower Byte 1W

PC L ( ( SP2 ) )

F /C P checks CY Flag . If CY =1 ,then the pro

F /C :

CC 1 S
Lower Byte 1 R

CNC 16 bit address

If CY =0

CZ 16 bit address

If Z=1

CNZ 16 bit address

If Z=0

CM 16 bit address

If S=1

CP16 bit address

If S=0

CPE 16 bit address

If P=1

CPO 16 bit address

If P=0

otherwise , only 1 st two M /C occur

6 T (S)
3T

|52| 189

16 bit address PC

C 1 F
F /C : Lower Byte 1 R
16 bit address PC
Higher Byte 1 R

4T
3T
3T

RET

Top of the PC

F /C : { RET 1 F

4T

Unconditional
Return

i. e . ( ( SP ) ) PC L

E/C : Lower Byte 1 R

Higher Byte 1 R

3T
3T

the

If CY =0
PC H ( ( SP1 ) )

During Read Cycle of Lower Byte

1|3|10

Similar POP R P
Latest SP=SP+2

Conditional Return Instructions :

( ( SP+ 1 ) ) PC H

RC , RNC , RZ , RNZ , RM , RP , RPE , RPO

Machine Related Instructions

Instructions
NOP

Operation

M /C

NoOperation4 T states

F /C : { NOP 1 F

HLT

Pis Halted

T States

F /C : { HLT 1 F
Halt Acknowledge M /C

4T

4T
1 T

B|M |T

CommentsRegisters used

1|1| 4

1|2| 5

The P finishes executing the Current

instructionhaltsfurther
execution . The P enters the Halt
Acknowledge machine cycle ,Wait
states are inserted every clock
period . It requires an interrupta
reset get the P out of the Halt state

I /O Related Instructions

( I /O Mapped I /O Mode )
Instructions

Operation

8 bit address

[ 8 bit address ] A

1F
F /C : 8 bit address 1 R
8 bit data 1 I

4T
3T
3T

2|3|10

A [ 8 bit address ]

OUT 1 F
F /C : 8 bit address 1 R
8 bit data 1 O

4T
3T
3T

2|3|10

OUT 8 bit address

M /C

T States

{
{

B|M |T

CommentsRegisters used

[ 8 bit address ] 8 bit data at thelocation

givenby 8 bit address of an I /O device

[ 8 bit address ] 8 bit data at thelocation

givenby 8 bit address of an I /O device

Additional Instructions
Instructions

DI

Operation
Disable Interrupts

M /C

T States

B|M |T

F /C : { DI 1 F

4T

1|1| 4

CommentsRegisters used
DI RST 7.5, 6.5,5.5, INTR are Disabled

( TRAP cannot be Disabled as it not Maskable )

EI

Enable Interrupts

F /C : { EI 1 F

4T

EI All are Enabled

1|1| 4

DAA Decimal Adjust Accumulator

DAA Content of A is converted binary value

F /C : { DAA 1 F

DAA

2 BCD Digit
4T

1|1| 4

i. e . it does BCD Correction when

Lower Nibble 9 10CY =1 AC=1

Operationtakes place ALU .
All Flags are affected

Instructions

Set

Interrupt

Operation

B|M |T

Accumulator Byte setup for beforeInstruction :

SOD

SDE

SOD Serial O/ P Data

Mask
SDE Serial Data Enable

R 7.5 Reset RST 7.5 Flipflop

MSE Mask Set Enable

M 7.5 RST 7.5 Mask Set

M 6.5 RST 6.5 Mask Set

R 7.5

MSE

M 7.5

M 6.5

M 5.5

SOD=0

If SDE=1 0 is sent on SOD Pin of P

SOD=1

If SDE=1 1is sent on SOD Pin of P

SDE =0

SOD bit is not sent on SOD Pin of P

SDE =1

SOD bit is sent on SOD Pin of P for 10 ms

R 7.5=0

RST 7.5 Flipflop remains Set

R 7.5=1

RST 7.5 Flipflop is reset

MSE=0

Mask Set is Disabled for the interrupts M 7.5, M 6.5, M 5.5

MSE=1

Mask Set is Enabled for theinterrupts M 7.5, M 6.5, M 5.5

M 7.5=0

If MSE=1 M 7.5 is Unmasked / Enabled

M 7.5=1

If MSE=1 M 7.5 is Masked/ Disabled

M 6.5=0

If MSE=1 M 6.5 is Unmasked / Enabled

M 6.5=1

If MSE=1 M 6.5 is Masked/ Disabled

1|1| 4

M 5.5 RST 5.5 Mask Set

M 5.5=0

If MSE=1 M 5.5 is Unmasked / Enabled

M 5.5=1

If MSE=1 M 5.5 is Masked/ Disabled

Accumulator Byte after RIM Instruction :

SID

I 7.5

I 6.5

SID Serial I /P Data

I 5.5

IE
SID=0
SID=1

I 7.5=0
I 7.5 RST 7.5 Interrupt Pending Status

I 7.5=1
I 6.5=0

RIM

I 6.5 RST 6.5 Interrupt Pending Status

Read

Interrupt

I 6.5=1

I 5.5=0
I 5.5 RST 5.5 Interrupt Pending Status

Mask

IE Interrupt Enable Flag

M 7.5 RST 7.5 Mask Status

M 6.5 RST 6.5 Mask Status

M 5.5 RST 5.5 Mask Status

I 5.5=1
IE=0

IE=1
M 7.5=0
M 7.5=1
M 6.5=0
M 6.5=1
M 5.5=0
M 5.5=1

M 7.5

M 6.5

M 5.5

0 is present on SID Pin of P

1is present on SID Pin of P

RST 7.5 Interrupt isnot Pending

RST 7.5 Interrupt is Pending

TRAP(Highest priority )is being serviced

RST 6.5 Interrupt isnot Pending

RST 6.5 Interrupt is Pending as

Higher priority Interrupts are being serviced

RST 5.5 Interrupt isnot Pending

RST 5.5 Interrupt is Pending as

Higher priority Interrupts are being serviced

ALL Interrupts are Disabled

ALL Interrupts are Enabled

M 7.5 is Unmasked / Enabled

M 7.5 is Masked/ Disabled( Not Pending )

M 6.5 is Unmasked / Enabled

M 6.5 is Masked/ Disabled( Not Pending)

M 5.5 is Unmasked / Enabled

M 5.5 is Masked/ Disabled( Not Pending )

1|1| 4

Software Interrupts ( Restart Instructions)

Instruction

Operation

M /C

T States

CommentsRegisters used

B|M |T

16 bit address is calcutated as

( n 8 )10=

After F /C PC=PC +1(1 Byte Inst )

( fetch new instruction)

16 bit address=00 H

PC H ( ( SP1 ) )
RST n

Instruction
RST 0

0000 H

C 7H

RST 1

0008 H

CF H

i. e . PC value for the Next Instruction

RST 2

0010 H

D7 H

is stored

RST 3

0018 H

DF H

After Execution 16 bit address PC

RST 4

0020 H

E 7H

Latest SP=SP2

RST 5

0028 H

EF H

RST 6

0030 H

F 7H

RST 7

0038 H

FF H

PC L ( ( SP2 ) )

Similar CALL
( )

Address Opcode

RST 1 S
F /C : Higher Byte 1 W
Lower Byte 1 W

i. e . PC Top of the

6 T ( S)
3T
3T

1|3|12

INTR(NonVector Hardware Interrupt)

Operation: INTR ( NVI ) is converted into1 of the Software Interrupts RST n

1.

Externally
INTR=1 ( Short Duration Pulse ) ( P)

2.

Acknowlegment

INTA=0
(Short Duration Pulse)( P)

3.

INTA=0
8 bit Buffer is Enabled

4.

8 bit Output of Buffer=Opcode of RST n

5.

P Loads PC with the address of respective RST n instruction

Addressing Modes
Addressing Mode

Operand

Operations

Examples

A + R R , R P + RP R P

ADD B , DAD B

RP

RR

MOV C , A

Direct

Memory Address

( H ) R

LDA H , LDA H

Register Indirect

RP

(( R P ) ) R

LDAX B , PUSH B , POP B , MOV C , M

8 bit data

8 bit data+ R R ,16 bit data+ R P RP

16 bit data

16 bit data R ,16 bit data R P

Register

Immediate

Implied

( Implicit )

Unique Operand

Instructionis Uniquecan beany

addressing mode

Instructions Icluding ' I '

JMP H ,CALL H

CMA , DAA , RAL , RAR , XTHL , PCHL, XCHG , RET etc

Delay Programs

Delay

Program

Time Delay Formula

Loop Delay Formulae

T D =T O + ( Count T L ) Correction

T O = T states of each instructions outside theloop

T L = T states of Non Decision making instructions inside the loop

Simple

Delay

T D Total Delay

Program

T O Delay Outside the Loop

T L Delay Inside the Loop

+T states of True case of Decisionmaking instruction inside the loop

Correction=Difference of T states of FalseTrue Cases of Decision

making instruction
T O = T states of each instructions outside both the loops

T D =T O + {Count 2 [ ( Count 1 T L1 ) +T L 2 ] }
Correction
Nested Loop

Delay
Program

T D Total Delay
T O Delay Outside the Loop
T L1 Delay Inside the Loop 1( Inner Loop)
T L2 Delay Inside the Loop 2(Outer Loop)
Count 1 Count of Loop 1( Inner Loop)

Count 2 Count of Loop2(Outer Loop)

T L1= T states of Non Decision makinginstructions inside loop 1

+T states of True case of Decisionmaking instruction inside loop 1

T L2= T states of Non Decision makinginstructions inside loop2

+T states of True case of Decisionmaking instruction inside loop 2

Count 2 Difference of T states of False True Cases of Decision m

inside loop1
Correction=
+ Difference of T states of FalseTrue Cases
of Decisionmaking instruction inside loop 2