Wed Oct 12 19:36:55 2016

seq_detector_mealy.vhd
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----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
00:27:56 10/05/2015
-- Design Name:
-- Module Name:
seq_detector_mealy - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
---------------------------

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Wed Oct 12 19:36:55 2016

seq_detector_mealy.vhd
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entity seq_detector_mealy is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
seq_in : in STD_LOGIC;
detect_out : out STD_LOGIC);
end seq_detector_mealy;
architecture Behavioral of seq_detector_mealy is
type state_type is (A,B,C,D,E);
signal state : state_type := A;
begin
process(clk)
begin
if( reset = '1' ) then
detect_out <= '0';
state <= A;
elsif ( rising_edge(clk) ) then
case state is
when A =>
if ( seq_in = '0' ) then
detect_out <= '0';
state <= B;
else
detect_out <= '0';
state <= C;
end if;
when B =>
if ( seq_in = '0' ) then
detect_out <= '0';
state <= B;
else
detect_out <= '0';
state <= D;
end if;
when C =>
if ( seq_in = '0' ) then
detect_out <= '0';
state <= E;
else
detect_out <= '0';
state <= C;
end if;
when others =>
NULL;
end case;
end if;
end process;
end Behavioral;

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