Lecture 6:

Circuit design
part 1
6.1 Combinational circuit
design
6.2 Sequential circuit design
6.3 Circuit simulation
6.4. Hardware description
language

Combinational Circuit Design

1. Combinational circuit design

Circuit designer must learn to think in terms of
NAND and NOR to take advantage of static CMOS

CMOS stages are inherently inverting, DeMorgans
law helps with this conversion:

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

1. Combinational circuit design

Bubble Pushing
Start with network of AND / OR gates
Convert to NAND / NOR + inverters
Push bubbles around to simplify logic
Remember DeMorgans Law

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

Example

Example: Design a circuit to compute F = AB + CD
using NANDs and NORs.

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

Compound Gates

Compound Gates
AOI21: AND-OR-INVERT-21

AOI22: AND-OR-INVERT-22

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

Logical Effort of compound gates

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

Example

Example:
Calculate the minimum delay, in , to compute F = AB + CD
using the following circuits:
Using
compound
gate

Using
NAND
gate

Each input can present a maximum of 20 of transistor

width. The output must drive a load equivalent to 100 of
transistor width.

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

Example

Solution:
The path electrical effort is H = 100/20 = 5
The branching effort is B = 1
Using
compound
gate

Using
NAND
gate

No. of stages N = 2
Logical effort G = (4/3) (4/3) = 16/9
Parasitic delay P = 2 + 2 = 4
Path efforts
F = GBH = 80/9
Path delays
D = NF1/N + P = 9.96

N=2
G = (6/3) 1 = 2
P = 12/3 + 1 = 5
F = GBH = 215 = 10
D = NF1/N + P = 11.32

=> Using compound gates does not always result in faster circuits;
simple 2-input NAND gates can be quite fast.
Combinational Circuit Design

CMOS VLSI Design

4th Ed.

Input Order

Our parasitic delay model was too simple
Calculate parasitic delay for Y falling
If A arrives latest? 2
If B arrives latest? 2.33
2

DA = R(6C) = 6RC = 2

2x

Combinational Circuit Design

Y
6C
2C

DB = (R/2)(2C) + R(6C) = 7RC =

2.33

CMOS VLSI Design

4th Ed.

Inner & Outer Inputs

Inner input is closest to output (A)

Outer input is closest to rail (B)

2
A

B

If input arrival time is known
Connect latest input to inner terminal

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

2
2

10

Asymmetric Gates

Asymmetric gates favor one input over another

Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance)
A
Boost size of noncritical input
reset
So total resistance is same

gA = 10/9
2
2
Y
A
4/3

gB = 2
4
reset

gtotal = gA + gB = 28/9

Asymmetric gate approaches g = 1 on critical input

But total logical effort goes up
Combinational Circuit Design

CMOS VLSI Design

4th Ed.

11

Symmetric Gates

Inputs can be made perfectly symmetric

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

12

Skewed Gates

Skewed gates favor one edge over another

Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor
HI-skew
inverter

unskewed inverter
(equal rise resistance)

2
A

unskewed inverter
(equal fall resistance)

2
Y

1/2

1
Y

Y
1/2

Calculate logical effort by comparing to unskewed

inverter with same effective resistance on that edge.
gu = 2.5 / 3 = 5/6
gd = 2.5 / 1.5 = 5/3
Combinational Circuit Design

CMOS VLSI Design

4th Ed.

13

HI- and LO-Skew

Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.

Skewed gates reduce size of noncritical transistors
HI-skew gates favor rising output (small nMOS)
LO-skew gates favor falling output (small pMOS)

Logical effort is smaller for favored direction

But larger for the other direction
Combinational Circuit Design

CMOS VLSI Design

4th Ed.

14

Catalog of Skewed Gates

Inverter

NAND2
2

unskewed

A
1

Y
guu = 1
gdd = 1
gavg
avg = 1

A
1/2

Y
guu = 5/6
gdd = 5/3
gavg
avg = 5/4

LO-skew

A
1

Combinational Circuit Design

guu = 5/3
gdd = 5/3
gavg
avg = 5/3

4
4

Y
1/2

guu = 1
gdd = 2
gavg
avg = 3/2

1/2

guu = 3/2
gdd = 3
gavg
avg = 9/4

B
Y

Y
guu = 4/3
gdd = 2/3
gavg
avg = 1

1
1

guu = 4/3
gdd = 4/3
gavg
avg = 4/3

HI-skew

NOR2

Y
guu = 2
gdd = 1
gavg
avg = 3/2

CMOS VLSI Design

guu = 2
gdd = 1
gavg
avg = 3/2

4th Ed.

15

Asymmetric Skew

Combine asymmetric and skewed gates
Downsize noncritical transistor on unimportant
input
Reduces parasitic delay for critical input
A
reset

1
A
reset

Combinational Circuit Design

4/3
4

CMOS VLSI Design

4th Ed.

16

Best P/N Ratio

We have selected P/N ratio for unit rise and fall
resistance ( = 2-3 for an inverter).

Alternative: choose ratio for least average delay

Ex: inverter
P
Delay driving identical inverter
A
1
tpdf = (P+1)
tpdr = (P+1)(/P)
tpd = (P+1)(1+/P)/2 = (P + 1 + + /P)/2
dtpd / dP = (1- /P2)/2 = 0
Least delay for P =
Combinational Circuit Design

CMOS VLSI Design

4th Ed.

17

P/N Ratios

In general, best P/N ratio is sqrt of equal delay ratio.
Only improves average delay slightly for inverters
But significantly decreases area and power

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

18

Observations

For speed:
NAND vs. NOR
Many simple stages vs. fewer high fan-in stages
Latest-arriving input

For area and power:
Many simple stages vs. fewer high fan-in stages

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

19

Review

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

20

10

Pseudo-nMOS

What makes a circuit fast?
I = C dV/dt -> tpd (C/I) V
low capacitance
high current
4
B
small swing
4
A

Logical effort is proportional to C/I
1
1

pMOS are the enemy!
High capacitance for a given current

Can we take the pMOS capacitance off the input?

Various circuit families try to do this
Combinational Circuit Design

CMOS VLSI Design

4th Ed.

21

Pseudo-nMOS

In the old days, nMOS processes had no pMOS
Instead, use pull-up transistor that is always ON

In CMOS, use a pMOS that is always ON
Ratio issue
Make pMOS about effective strength of
pulldown network
1.8
1.5

load
P/2

1.2
P = 24

Ids

Vout 0.9

Vout
16/2
Vin

0.6
P = 14
0.3

P=4

0
0

0.3

0.6

0.9

1.2

1.5

1.8

Vin

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

22

11

Pseudo-nMOS Gates

Design for unit current on output
to compare with unit inverter.

pMOS fights nMOS

Y
inputs
f

Inverter

Y
A

NAND2
gu
gd
gavg
pu
pd
pavg

=
=
=
=
=
=

gu
g
Y gd
avg
pu
pd
pavg

A
B

Combinational Circuit Design

NOR2
=
=
=
=
=
=

CMOS VLSI Design

gu
gd
gavg
Y pu
pd
pavg

=
=
=
=
=
=

4th Ed.

23

Pseudo-nMOS Gates

Design for unit current on output
to compare with unit inverter.

pMOS fights nMOS

Y
inputs
f

Inverter

2/3
Y
A

4/3

NAND2
gu
gd
gavg
pu
pd
pavg

= 4/3
= 4/9
= 8/9
= 6/3
= 6/9
= 12/9

Combinational Circuit Design

gu
g
Y gd
avg
8/3
pu
pd
8/3
pavg
2/3

A
B

NOR2
= 8/3
= 8/9
= 16/9
= 10/3
= 10/9
= 20/9

CMOS VLSI Design

2/3
A

4th Ed.

4/3 B

gu
gd
gavg
Y pu
4/3 pd
pavg

= 4/3
= 4/9
= 8/9
= 10/3
= 10/9
= 20/9
24

12

Pseudo-nMOS Design

Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
Pseudo-nMOS

G = 1 * 8/9 = 8/9
F = GBH = 8H/9
P = 1 + (4+8k)/9 = (8k+13)/9
N=2
4 2 H 8k + 13
D = NF1/N + P = 3 + 9

Combinational Circuit Design

In1

Ink

CMOS VLSI Design

Y
H

4th Ed.

25

Pseudo-nMOS Power

Pseudo-nMOS draws power whenever Y = 0
Called static power P = IDDVDD
A few mA / gate * 1M gates would be a problem
Explains why nMOS went extinct

Use pseudo-nMOS sparingly for wide NORs

Turn off pMOS when not in use
en
Y
A

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

26

13

Ratio Example

The chip contains a 32 word x 48 bit ROM
Uses pseudo-nMOS decoder and bitline pullups
On average, one wordline and 24 bitlines are high

Find static power drawn by the ROM
Ion-p = 36 A, VDD = 1.0 V

Solution:
Ppull-up = VDD I pull-up = 36 W
Pstatic = (31 + 24) Ppull-up = 1.98 mW

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

27

Dynamic Logic

Dynamic gates uses a clocked pMOS pullup

Two modes: precharge and evaluate
2
A

2/3
Y

Static

4/3

Pseudo-nMOS

Precharge

Dynamic
Evaluate

Precharge

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

28

14

The Foot

What if pulldown network is ON during precharge?

Use series evaluation transistor to prevent fight.

precharge transistor

inputs

inputs
f

foot
footed

Combinational Circuit Design

CMOS VLSI Design

unfooted

4th Ed.

29

Logical Effort
Inverter

unfooted

gd
pd

= 1/3
= 2/3

2
2

1
2

gd
pd

= 2/3
= 3/3

Combinational Circuit Design

Y
gd
pd

= 2/3
= 3/3

1
Y

NOR2

1
Y

footed

NAND2

gd
pd

= 1/3
= 3/3

Y
gd
pd

= 3/3
= 4/3

CMOS VLSI Design

4th Ed.

2
gd
pd

= 2/3
= 5/3

30

15

Monotonicity

Dynamic gates require monotonically rising inputs
during evaluation

0 -> 0
A
0 -> 1
1 -> 1
violates monotonicity
But not 1 -> 0
during evaluation
A

Precharge

Evaluate

Precharge

Y
Output should rise but does not

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

31

Monotonicity Woes

But dynamic gates produce
monotonically falling
outputs during evaluation

Illegal for one dynamic gate
to drive another!
A=1

Precharge

Evaluate

Precharge

X
X
X monotonically falls during evaluation
Y
Y should rise but cannot

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

32

16

Domino Gates

Follow dynamic stage with inverting static gate
Dynamic / static pair is called domino gate
Produces monotonic outputs
Precharge

Evaluate

Precharge

domino AND
W

A
B

dynamic static
NAND inverter

A
B

Combinational Circuit Design

CMOS VLSI Design

A
B

X
Z

4th Ed.

33

Domino Optimizations

Each domino gate triggers next one, like a string of
dominos toppling over

Gates evaluate sequentially but precharge in parallel

Thus evaluation is more critical than precharge

HI-skewed static stages can perform logic

S0

S1

S2

S3

D0

D1

D2

D3
H

S4

S5

S6

S7

D4

D5

D6

D7

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

34

17

Dual-Rail Domino

Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR

Dual-rail domino solves this problem
Takes true and complementary inputs
Produces true and complementary outputs
sig_h

sig_l

Meaning

Precharged

invalid

Combinational Circuit Design

Y_l

Y_h

inputs

CMOS VLSI Design

4th Ed.

35

Example: AND/NAND

Given A_h, A_l, B_h, B_l

Compute Y_h = AB, Y_l = AB

Pulldown networks are conduction complements

Y_l

A_h

= A*B
A_l

B_l

Y_h
= A*B

B_h

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

36

18

Example: XOR/XNOR

Sometimes possible to share transistors

Y_l
= A xnor B

Y_h

A_h

A_l

A_l

B_l

B_h

A_h

= A xor B

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

37

Leakage

Dynamic node floats high during evaluation
Transistors are leaky (IOFF 0)
Dynamic value will leak away over time
Formerly miliseconds, now nanoseconds

Use keeper to hold dynamic node
Must be weak enough not to fight evaluation
weak keeper

1 k

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

38

19

Charge Sharing

Dynamic gates suffer from charge sharing

A
B=0

Y
CY

Cx

Charge sharing noise

x

Vx = VY =

Combinational Circuit Design

CMOS VLSI Design

CY
VDD
C x + CY

4th Ed.

39

Secondary Precharge

Solution: add secondary precharge transistors
Typically need to precharge every other node

Big load capacitance CY helps as well

Y
A

secondary
precharge
transistor

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

40

20

Noise Sensitivity

Dynamic gates are very sensitive to noise
Inputs: VIH Vtn
Outputs: floating output susceptible noise

Noise sources
Capacitive crosstalk
Charge sharing
Power supply noise
Feedthrough noise
And more!

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

41

Power

Domino gates have high activity factors
Output evaluates and precharges
If output probability = 0.5, = 0.5
Output rises and falls on half the cycles

Clocked transistors have = 1

Leads to very high power consumption

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

42

21

Domino Summary

Domino logic is attractive for high-speed circuits
1.3 2x faster than static CMOS
But many challenges:
Monotonicity, leakage, charge sharing, noise

Widely used in high-performance microprocessors in
1990s when speed was king

Largely displaced by static CMOS now that power is
the limiter

Still used in memories for area efficiency

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

43

Pass Transistor Circuits

Use pass transistors like switches to do logic

Inputs drive diffusion terminals as well as gates

CMOS + Transmission Gates:
2-input multiplexer
Gates should be restoring
S

S
A

A
S

S
Combinational Circuit Design

CMOS VLSI Design

4th Ed.

44

22

LEAP

LEAn integration with Pass transistors

Get rid of pMOS transistors
Use weak pMOS feedback to pull fully high
Ratio constraint

S
A
L

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

45

CPL

Complementary Pass-transistor Logic
Dual-rail form of pass transistor logic
Avoids need for ratioed feedback
Optional cross-coupling for rail-to-rail swing
S
A
S

B
S
A
S
B

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

46

23

Pass Transistor Summary

Researchers investigated pass transistor logic for
general purpose applications in the 1990s
Benefits over static CMOS were small or negative
No longer generally used

However, pass transistors still have a niche in
special circuits such as memories where they offer
small size and the threshold drops can be managed

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

47

Review
1.
2.
3.
4.
5.

What are pseudo-nMOS gates?

What are drawbacks of pseudo-nMOS gates?
What are dynamic gates?
What is the foot of dynamic gates?
Why do we need secondary precharge for dynamic
gates?
6. Why are dynamic gates very sensitive to noise?
7. What are domino gates?
8. What is CPL?

Combinational Circuit Design

CMOS VLSI Design

4th Ed.

48

24

Review
1. Compute logical effort for rising and falling gu and gd
of the following gates
b)

a)

c)

Combinational Circuit Design

e)

d)

CMOS VLSI Design

4th Ed.

49

25