Design and Test Results of a Front-end ASIC for Radiation Detectors

Zhang Yacong*, Chen Zhongjian*, Lu Wengao, Ji Lijiu, Zhao Baoying

Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics
Peking University, 100871, P. R. China
*Email: zhangyacong@ime.pku.edu.cnchenzj@pku.edu.cn

Abstract
A front-end ASIC for semiconductor radiation
detectors is presented. It is composed of a Charge
Sensitive Amplifier (CSA), a pulse shaper, and a Peak
Detect and Hold (PDH) circuit. Poly-resistor is used as
source degeneration component to reduce the noise of
current source in the CSA. The ASIC has been designed
in a 0.5um CMOS DPTM technology and tested with
Verigy 93000. The gain (PDH excluded) is 78.5mV/fC
and the Equivalent Noise Charge (ENC) with detector
disconnected is 800-900e. The power dissipation without
the output buffer is about 2.6mW.

the CSA from saturation. The pulse shaper[5], which is of

a CR-(RC)2 type or called semi-Gaussian shaper, filters
and shapes the CSA output signal to increase the Signalto-Noise Ratio (SNR). Additional gain is also provided
by the shapero The amplitude of the shaper output
voltage is recorded by the peak detect and hold circuit. It
will be further processed by ADC or Multi-Channel
Analyzer (MCA) off chip.

Rf

2. Circuit Description
The topology of the designed circuit is shown in Fig.1.
lin represents the charge pulse generated in the detector
and Cc is for test. The charges are integrated onto a small
capacitor Cf, giving rise to a voltage step at the output of
the CSA. Rf is used to discharge Cf in order to prevent

Rp

RI

'-------',

,!
!

1. Introduction
Radiation detectors are widely used in elementary
particle experiments, nuclear physics, medicine, and
space applications[1][2]. When the radiation interacts with
the detector, a charge pulse is generated. The amount of
the charge, which is proportional to the absorbed energy,
is so small that the noise of the readout circuit must be
minimized. As the number of readout channels is
continually increasing these years, CMOS integrated
circuit becomes the best choice due to its advantages of
high density, low cost and low power[3][4]. However, the
noise performance of MOS transistor is much worse than
that of bipolar transistor and JFET[4]. It is a challenge to
design low noise multi-channel readout ASIC with more
and more function integrated into it.
A front-end ASIC compromising a Charge Sensitive
Amplifier (CSA), a pulse shaper, and a Peak Detect and
Hold (PDH) circuit has been designed and tested. Polyresistor is used as source degeneration component to
reduce the equivalent transconductance of the current
source in the CSA. As a result, the noise contribution of
the current source is reduced. In Section 2, the ASIC
structure and the circuit blocks are described. In Section
3, the test results are given to verify the feasibility of the
ASIC. At the end of the paper is a conclusion.

r---------c1----------i

Cf

'-----

..

CSA

shaper

x2

!Vob

Vout

~l

PDH

Figure 1. Topology of the designed ASIC

2.1 Charge Sensitive Amplifier

Single-ended, folded cascode amplifier is usually
selected for the CSA because of its high DC gain and
large bandwidth. Fig.2 shows the schematic of the CSA
together with the bias circuit.

r--------------------

Vout

Vb4

D--------+-+-~

Figure 2. Schematic of the charge sensitive amplifier

Located at the front end of the readout circuit, the
CSA has the greatest influence on the noise performance.
Since the transconductance of the input transistor M1 is
often large, the noise of M1 dominates. The bias current,
the width and the length of M1 should be optimized
based on noise consideration[4]. Besides, the noise of
other transistors can not be totally neglected, especially

978-1-4244-2186-2/08/$25.00 2008 IEEE

that of M3. In CMOS technology, NMOS has much

more flicker noise than PMOS. In addition, the current in
M3 is even larger than that in MI. Hence, both the
thermal and the flicker noise of M3 are not negligible. To
reduce the noise of M3, poly-resistor is used as source
degeneration component. In this way, the equivalent
transconductance of M3 is reduced, and so is the noise[6].
Without the resistor, the input referred equivalent
noise due to M3 can be expressed as:

J/

V2

2 ( 8kT
Kf
2
(1)
= g m3 X -3- + W L C! g ml
g m3
3 3 ox
With the resistor added, the equivalent input noise due
to M3 and its source resistance Rs3 is given by:
n,3

voltage at the input of the amplifier is fixed. The circuit

is shown in Fig.3, where V c2 and V c3 are the tuning
voltages. VdsVgs-Vth is required to keep enough
linearity for MaS working in triode region. So the
tuning voltages should be big enough and the MaS
resistance should be limited. To compromise between
linearity and tuning range, two MaS's are used in
parallel. One exhibits big resistance to enlarge tuning
range while the other is relatively small to realize good
linearity. They can be selected according to application.
Vc2

r-"-"-"-"

: Rin

gm3
X
(1 + (gm3 + gmb3 )Rs3 )2

Vn~3 = (

8kT
3g m3

Kf
W3L 3C ox !

+ 4kTRs3

) / g;'l

(2)

g~3

2.2 Pulse Shaper

Semi-Gaussian shaper is widely used because it is a
good compromise among noise performance, counting
rate, and circuit complexity. It filters out the high and
low frequency noise and changes the step voltage into a
semi-Gaussian shape to suppress pileup and to facilitate
the record of the pulse height. Referring to Fig. 1, the
transfer function from the output of CSA (Voa) to the
output of the shaper (Vob) can be expressed as follows:

l+---.E..+ s C R
R in

RI

Rin(l+sC1R1)

i.._.. _.. _.. _.._.. _.. _..i

2 X (8kT + 4kTR ) is a
s3
(1 + (gm3 + gmb3)R s3 )
3g m3
descent function of Rs3 , so larger resistance is beneficial
for noise suppression.
The coefficients of resN in each branch of the circuit
scale according to the current passing through it to
guarantee equal voltage drop across each resistor.

I+sCpRp (
H(s) = --R-~-

~ Rina

Notice that the flicker noise is reduced by a factor of

(1 +(gm3+gmb3)*Rs3). As for the thermal noise, it can be
verified that
f(R s3 ) =

)2

Figure 3. Implementation ofR I and RiD

2.3 Peak Detect and Hold Circuit

Since the radiation arrives at the detector at random,
the time when the peak of the shaper output voltage
appears can not be predicted. It is difficult for the track!
hold system to precisely sample the peak voltage. High
speed, accurate Peak Detect and Hold (PDH) circuit is
suitable for this situation. The PDH circuit is usually
composed of an amplifier, a rectifying component, and a
capacitor. Diode is adopted as the rectifying component
in discrete electronics, utilizing the property of unilateral
conductivity. In integrated circuit, however, the big
parasitic capacitance parallel to the diode will deteriorate
the accuracy of the PDH circuit by capacitive coupling.
Instead of the diode, a rectifying current mirror is
preferred[7][8].

Vin

(3)

Cp and Rp are used for pole-zero cancellation, with

CpR p = CfR f required. Let CpR p /(1 + Rp / Rin ) = RIC1 ,
and then a uniform time constant of RIC 1 is achieved for
the denominator.
The time constant is a strong function of process
parameters, because it is related with the absolute value
of passive components. To compensate process variation,
RiD and R 1 are implemented with poly resistors in series
with linear MaS resistors[6]. This is feasible because the

D--I11--------tt-l

Wol
Vout

Figure 4. Schematic of the peak detect and hold circuit

The schematic of the PDH is shown in Fig.4.
Mal-Mall compose a folded cascode amplifier while
Mg1 and Mg2 constitute the current mirror. When the

input signal rises, the Mg1 gate voltage goes down,

tuning on Mg1/Mg2. The hold capacitor Ch is charged,
and Vout follows Yin. Once the peak is reached, Yin
becomes lower than Vout, tuning off the current mirror.
As there is no path to discharge Ch, the peak voltage is
held.
The maximum change rate of the input signal V; 'max
sets a limit for the bias current of the amplifier and the
dimension of the rectifying current mirror. The
maximum current charging the hold capacitor Ch
equals kI Mall' where k is the dimension ratio of Mg2 to
Mg 1. So the maximum change rate of the output signal

DPTM CMOS technology and tested with Verigy 93000.

A pulse with a repetition period of 20us is injected into
the capacitor Cc in Fig.1 to simulate the charge pulse.
Varying the gate voltage Vc of the feedback linear MOS
resistor Mr, the decay time constant of the CSA changes,
as shown in Fig.5, where the input pulse amplitude is set
to be O.IV. As a compromise between decay time and
noise, Vc=1.79V is selected for the following test, just as
the designed value.
Vc=1.70V
1.1 .--------.---.----r-----,

>1
:g-

V~max is kI Mall I Ch , which must be larger than V; 'max to

follow the input signal. The dimension of Mg 1 must
meet the following requirement:
1
W
2
I Mglmax = 2" PpCox I: (VDD - Vgmin -I ~hp I)
(4)

kI Mglmax I C h > V;'max

21r' CG,Mgl

GBW =

m,Mal

50

100

150

200

50

(7)
(8)

21r' Ch

where gm,x ro,x are the transconductance and the output

resistance of the corresponding transistor, respectively.
CG,MgI is the total capacitance at the gate node of Mg1,
and k is the dimension ratio of Mg2 to Mgl as
mentioned above.
When the input signal is rising, the PDH works as a
unity feedback amplifier. To ensure a phase margin
greater than 45, the non-dominant pole should be larger
than GBW. However, fnd is not fixed, since the current in
Mg 1, which determines its transconductance, is
proportional to the change rate of the input signal V;'.
The worst case is when V;' is at its minimum. In this
situation, the current in Mgl is smallest, and so is fnd It
should be ensured the circuit is stable in this worst case.
3. Test Results
The front-end ASIC has been designed in a O.5um

~1
'5

~1
'5

(j

(j

150

200

~ 0.9

~ 0.9
0.80

100

Vc=1.89V
1.1 ,...-------.----.----.-.---..

1.1 .---~---..---------,

(5)

ofMgl.
Stability must be guaranteed. The dominant pole is
located at the hold capacitor and the first non-dominant
pole is at the output node of the amplifier. Their
expressions together with the Gain BandWidth (GBW)
are given below. Ignore all the other poles at higher
frequency.
1
(6)
fd = - - - - 21r . ro ,Mg2 Ch
gm,Mgl

~ 0.9
u

Vc=1.84V

where Vgmin is the minimum value of the gate voltage

I'
_
Jnd -

Vc=1.79V
1.1 ,...-------.----.----.-----.

50

100
t(us)

150

200

0.80

50

100
t(us)

150

200

Figure 5. The CSA output waveform with different Vc

The shaper output waveform is depicted in Fig.6. This
circuit is designed to process current pulse flowing out
of the CSA. Only the positive pulse in Fig.6 is valid. The
negative pulse has exceeded the output swing. A linear
fit of the peak voltage versus the input pulse amplitude
yielded a gain of 78.5mV/fC and a linearity of 99.2%.
The definition of linearity is given by:

. -L Inearlty

(1 - Imax(residual)
IJ x 100
swing(Vout)

10

(9)

where residual is the difference between the measured

value and the linear fit result, while swing(Vout) is the
output voltage range.
Smaller V c2/Vc3 causes bigger resistance, which means
longer peaking time. Due to the difficulty of precisely
reading data on the rough curve, the exact dependence of
the peaking time on V c2/Vc3 was not obtained, but the
trend is correct. For example, Vc2=Vc3=5V corresponds
to O.9us--lus, while V c2=3.5V&Vc3=OV results in l.1us-1.2 us.
The noise performance is usually described by the
Equivalent Noise Charge (ENC), which is defined as the
ratio of the total integrated rms noise at the output of the
pulse shaper to the signal amplitude due to one electron
charge[4J The output rms noise can be gotten by
calculating the standard deviation of a group of output
voltage amplitude with the same input signal. The

calculated ENC is 800-900e when there is no detector

connected. It should be pointed out that this result
includes the noise introduced by the test equipment, the
sampling error and the estimation error due to small
sample space. For the limitation of the test equipment,
only 40 cycles are recorded. Estimating the population
standard deviation from such a small sample space will
result in a larger value than the true one. Reducing the
sampling frequency at which the waveform is captured
can increase the number of cycles saved. This enlarges
the sample space, but it is more difficult to precisely get
the peak of the shaper output voltage, which increases
the sampling error.

4. Conclusion
A readout ASIC for semiconductor radiation detectors
is described. It converts the charges released by the
detector into a voltage, and then amplifies and filters the
voltage. The amplitude of the shaper output voltage,
which is proportional to the energy the radiation loses, is
recorded by the peak detect and hold circuit. The ASIC
has been designed in a 0.5um DPTM CMOS technology
and tested with Verigy 93000. The test results verify the
feasibility of this circuit.
Acknowledgments

shaper output waveform

shaper output waveform in detail

2 ...---..--.....-.....--.--.----.--------.
1.8

~1.6

'5
~ 1.4

We are grateful to Ye Hongfei for his help with the

measurement of the chip.
References

Q.

to
~

0.5
0
0

50

100
t(us)

150

200

1.2

0.86

[1] G Mazza, A. Rivetti, G AneIH, et at. IEEE Transactions on Nuclear Science, 51(5), p.1942 (2004).
8

10 12 14 16 18
t(us)

[2] Xiao Zuo, Zou Jiqing, Zou Hong, et at. Journal

(Natural Science) of Peking University, 39(3), p.361

Figure 6. The shaper output waveform

The output waveform of the PDH circuit is shown in
Fig.7. It follows the shaper output only when it climbs.
After the peak is reached, PDH holds the peak voltage
until the reset signal is valid. A droop rate of 5mVIus is
observed during the hold period. A bigger hold capacitor
may reduce the droop rate.
The performance of the ASIC is summarized in Table
1.

(2003) (in Chinese).

[3] J. Vandenbussche, F. Leyn, G Van der Plas, et at.
IEEE Transactions on Nuclear Science, 45(4), p.2272
(1998).
[4] Willy M. C. Sansen and Zhong Yuan Chang, IEEE
Transactions on Circuits and Systems, 37, p.1375
(1990).
[5] C. L. Britton, G T. Alley, M. L. Simpson, IEEE

PDH output waveform

PDH output waveform in detail

2 ...-------.--~--.-----.

Transactions on Nuclear Science, 41(1), p.352(1994).

[6] Zhang Yacong, Chen Zhongjian, Lu Wengao, et at.

1.5

'5

Q.

Q.

to

Chinese Journal of Semiconductors, 28(2), p.182

(2007).

to

.t:

UJ

1.5

'5

[7] M.W. Kruiskamp, D. Leenaerts, IEEE Transactions

.t:

UJ

0.5
0
0

50

100
t(us)

150

200

0.5
0
0

on Nuclear Science, 41 (1), p.295 (1994).

10

20
t(us)

30

Figure 7. Output waveform of the PDH circuit

1:abliP
e . erfiormance parame er 0 fth e ASIC
Gain
78.5mV/fC(PDH excluded)
Peaking time
About 0.9-1.2us
Power dissipation
2.6mW, 8.1mW including
output buffer
ENC
800-900e
Linearity
99.2%(PDH excluded)
Dynamic range
0-22fC

40

[8] G Geronimo, P. O'Connor, A. Kandasamy, Nuclear

Instruments and Methods in Physics Research
Section A, 484, p.533 (2002).