Create a list of the blocks and bond pads to be used and estimate the area of them.

2 - (In mixed signal) identify the "noisy" blocks.

3 - estimate the total die area and draw a limit die size then insert the blocks estimated in
#1 but take care of placing the "noisy" blocks as far a possible from sensitive analog
blocks... The bondpads must be placed also right now, verifying they are in a correct place
to be bonded out...
4 - Within the digital (or noisy) blocks place them in such a way that clock lines get the
shortest path as possible at toplevel routing.
5 - Draw some lines for TOPLEVEL PWR and GND so you can define where future PWR and
GDN buses will be (where all the blocks will be getting their supply).
6 - Save area for toplevel routing buses (areas where you'll be able to route lines for
toplevel interconnect)
Etc, etc.
As you can see, most of the things are obvious and logical things... As posted before it has
to do A LOT with experience and practice but following the above mentioned list you can
make sure you'll be more than ok.
What is the floor planning flow?
How can we place the blocks in core area (on what basis), how can we place the pads
(power pads & Signal pads)?
1 - BONDING PADS: The pads are one of the very first things to be placed (at least their
relative position between each other) and that preliminar location is based on PACKAGE
PINOUT. At the very beginning of your project you have to make sure that you'll be able to
bond your chip once is finished...
2- Main block location reasons were already included in the former post:
a - Separate as much as possible digital (noisy) blocks from analog ones.
b- ONce the previous is done, place the blocks in such a way the interconnection is
minimized.
c- Put as centered as possible the device you know as the biggest power dissipator
Here are some.
* As much as possible don't put sensitive blocks to location of high stress gradient.
* Consider the signal flow.
* There are blocks that must be placed side by side.
try to re To add to the above points,
The IR drop of Signals connectting to the PAD should be minimum. So those blocks that
have the signals connectiong to pads are placed close to the PAD. ad layout books.
The ideal situation will be to center it, but it's not a must...
The idea behind that is to have an uniform thermal gradient (isothermal lines) across the

chip in order to minimize thermal effects on very sensitive analog circuits.

That's why I say it's not a must. The important thing would be to know where this
component is placed in order to be aware of it and place the sensitive components and
circuits according to it in the rest of the chip. Hope this is clear now.