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Associating PWM and Balancing Techniques for

Performance Improvement of Flying Capacitor
Inverter
Conference Paper October 2013
DOI: 10.1109/COBEP.2013.6785100

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Associating PWM and Balancing Techniques for Performance Improvement of Flying

Capacitor Inverter
W. O. Maia, Z. M. A. Peixoto
Graduate Program in Electrical Engineering
Pontifical Catholic University of Minas Gerais
Belo Horizonte, Minas Gerais - Brazil 30535-610
maia.weol@gmail.com, assiszmp@pucminas.br

AbstractThis paper aims at the reduction of the

harmonic content in sinusoidal signals synthesized from
flying capacitor multilevel inverters for AC electrical drive
systems. In this sense, three distinct voltage-balancing
techniques and pulse width modulation methods are
jointly investigated. Among voltage-balancing techniques,
a new method including restrictions of switching under
charging/discharging and maximum current in the flying
capacitors is presented. The strategies are analysed in a
three-level inverter controlled by space-vector and carrierbased pulse width modulation (PWM). Regarding the
carrier-wave strategy, specifically level shifted - phase
disposition modulation (LSPWM - PDPWM), the authors
propose a redundant switching states controller that
enables the application of this technique to the flying
capacitor topologies including an appropriate portion of
the third harmonic component for greater utilization of
the DC voltage bus. All techniques were validated using
MatLab simulations and, in the SVPWM case, experimentally too. The results obtained have been comproved the
main desired characteristics, namely output voltages and
currents with low harmonic content, low computational
complexity and ease of digital implementation.
KeywordsDSP, Flying Capacitor, Multilevel Inverter,
SVPWM, PDPWM, Harmonics.
I.

INTRODUCTION

Nowadays, a wide range of applications uses multilevel

converters. As these processes require continuously increasing system performance, cost reduction and higher efficiency,
new semiconductor manufacturing techniques have been
developed and, in parallel, several works focused on control
techniques and new topologies of converters have also been
proposed [1]. Many aspects can be highlighted in recent
studies specifically focused on flying capacitor multilevel
topology, among them, capacitor voltage balancing techniques [2][3], harmonic distortion reduction [4], robustness
to the load disturbances and power grid variations, nonlinear modeling and switching losses minimizing methods are
frequently researched [5].
This paper deals with harmonic content reduction of
the output signals in flying capacitor multilevel inverters
focusing, mainly, three-level topologies. Therefore, studies
were carried out in the pursuit of techniques that could be
easily incorporated into modulation methods and voltagebalancing algorithms improving the performance of these

drives with a good cost-benefit ratio. In this context, analyses were performed associating space vector modulation
(SVPWM) and level shifted - phase disposition modulation
(LSPWM - PDPWM) strategies with control techniques for
the intermediate voltage levels, such as the minimizing of
the squared error between measured and reference flying
capacitor voltages, 3 and 2-level comparators.
The main contributions of this work can be summarized
as the following. Firstly, an balancing-voltage algorithm
that includes restrictions of the number of switchings under
conditions of charging/discharging and the maximum current
in the flying capacitors (FC). In this case, the purpose is
to reduce the harmonic distortion of the output signals and,
simultaneously, to reduce the stress of the static switches.
Furthermore, redundant switching states controllers are developed enabling the application of a modified version of
the PDPWM (PDPWM-THI) technique to the 3-level flying
capacitor topologies. The PDPWM-THI method includes an
appropriate portion of the third harmonic component that
increases of maximum voltage value obtained from the DC
bus.
All techniques were analyzed by simulations, in MatLab
environment. Aditionally, an experimental case study involving all voltage-balancing techniques and the SVPWM method
has been shown up good accordance with the simulation
results. Both analyses prove a good performance of the
proposed balancing-voltage method and its suitability to the
PWM methods.
II.

TECHNICAL BACKGROUND

Fig. 1 presents the basic structure of the three-level flying

capacitor inverter (FC). According to Table I, where the
variable x refers to the output phase, x {a, b, c}, there are
four possible switching states indicated as states P , OA , OB
and N , for each inverters leg. In the state P the switches
Sx1 and Sx2 are ON, while the switches Sx3 and Sx4
are OFF. In the state N , these switches are commanded in
opposite conditions. Therefore, the state P (N ) provides the
connection between load and the upper (lower) side of the DC
bus and they do not affect the voltage on the flying capacitors.
The states OA or OB occur when switches Sx1 and Sx3 or
switches Sx2 and Sx4 are turned ON, respectively. If the
flying capacitor voltages are kept constant and equal to half
of the DC bus voltage, VCx = E/2, these configurations
result in a same level of output voltage, i.e., these conditions
provide redundant states.
In the most of the AC drive applications, the main
objective of multilevel voltage inverter is to provide variable

amplitude and frequency output signals, from a few hertz

and voltages until rated values, with low harmonic distortion
levels. In this context, this work addresses pulse width modulation methods and voltage balancing techniques, searching
for solutions that can be easily incorporated to the systems
that demand complex control algorithms, like as sensorless
control systems, among others.

x = px (k) nx (k)
SC
T

(2)

Fig. 2. Voltage vectors of the sector A

Fig. 1. Schematic diagram of a 3-level flying capacitor inverter

TABLE I
Switching states of a 3-level flying capacitor inverter
States
P
OA
OB
N

Sx1
1
1
0
0

Sx2
1
0
1
0

Sx3
0
1
0
1

Sx4
0
0
1
1

m=

2
(van + avbn + a2 vcn )
3

Vm
E

(3)

Where Vm and E represent the maximum magnitude of

the reference voltage and DC bus voltage, respectively.

Vxg
E
E - VCx
VCx
0

A. Space Vector PWM

The space vector pulse width modulation technique was,
originally, developed for two level converters and later
extended for multilevel topologies. This strategy is based on
theory of complex space vector ~vs , composed by three-phase
instantaneous voltages values as [6]:
~vs =

An important parameter of the PWM strategies refers to

the modulation index, which is related to the synthesizing
capability of voltages from the available DC bus voltage. For
SVPWM method, the modulation index is calculated as:

(1)

Where a = ej 3 . From the combination of the switching

states of the three-level inverter, shown in Fig. 1, the threephase output voltages can be calculated and, thereafter,
applying the Clarke transformation, there are obtained 27
space vectors, corresponding to each vertex of the voltage
hexagon in plane.
As shown in Fig. 2 in the most of the SVPWM methods,
the reference voltage vector ~vs is synthesized using the voltage vectors located on the vertices closer to the desired vector,
during time intervals previously calculated [7]. Indicating the
switching time intervals relative to the states P , O, N as
x as the average value of
px , ox , nx , x {a, b, c} and SC
command signal, a generic signal control can be expressed,
i.e.:

B. Phase Disposition PWM

In n-level carrier-based PWM, (n 1) carrier signals
are required in each inverters leg, usually triangular waves
with same frequency and amplitude, that can be aligned
horizontally (phase shifted PWM - PSPWM) or vertically
(level shifted PWM - LSPWM). From comparison with the
reference signal related to each phase, these carriers are
responsible for the control of a complementary pair of static
switches [8].
The LSPWM method is widely used in neutral clamped
and cascaded converters. Based on Fig. 1 and considering
LSPWM strategy, the lowest level carrier must generate the
control signals for the switches Sx2 and Sx4 while the
highest level carrier is responsible by the command of the
switches Sx1 and Sx3. It can be noted that this method only
generates the switching states P , O and N , becoming this
strategy unsuitable for FC inverter topologies [9].
In order to overcome this limitation, this work proposes a
new control scheme for OA /OB states, enabling the application of the LSPWM technique to the 3-level FC inverter.
As shown by Fig. 3, the signals usually generated from
the comparison of the triangular carriers with modulating
signals are (Sx10 , Sx20 , Sx30 e Sx40 ). From these, the States
Controller divides the intermediate state (O) into two (OA e
OB ) states for each leg and applies them to the apropriate
switches. The selection between these two states is based
on measuring of the flying capacitor voltages and the output
currents of the inverter, using the controllers to be presented
in the section III.

III.

VOLTAGE BALANCING TECHNIQUES

In FC multilevel inverters, the control of the output and

flying capacitor voltages can be performed independently,
making this topology attractive and flexible in relation to
the increasing of the number of output levels. Thus, it is
worth emphasizing that the capacitor voltages are sufficiently
close to the reference values, ensuring symmetry and a good
distribution of intermediate levels of output voltages [3] [7].

Fig. 3. Block diagram of modified LSPWM technique

Including these controllers, a modified LSPWM technique

based on PDPWM (phase disposition PWM) strategy and
3rd harmonic injection scheme has been used for controlling
output voltages. This association provides a better utilization
of available DC voltage.
The waveforms, shown in Fig. 4, were obtained from the
application of PDPWM technique to the 3-level FC inverter.
It can be seen that, if the modulating signal is greater
than the both carrier waves, the two upper switches will
be turned ON and the two lower switches will be turned
OFF. During the time interval, in which the reference signal
magnitude is located between instantaneous values of two
carriers, (VCR2 v VCR1 ), the inverter is able to provide
the intermediate voltage values at the outputs or E Vcx .
Similarly to the first case, when the reference signal is smaller
than both carriers, the switches upper are turned OFF and
lower switches are turned ON.

A. Using Voltage Squared Error Minimization and Redundant States

In [7], it is proposed a method that associates a minimization of a cost function based on flying capacitor voltage error,
i.e., the diference between measured and reference flying
capacitor voltages, and the redundant states of the inverter.
For a n-level FC inverter with j = (n 2) capacitors per
phase the cost function Jx , where the subscript x refers to
the output phase, is defined as:

Jx =

n2

2
1X
Cjx VCjx VCjxref ) , x {a, b, c}
2 j=1

(5)

Where Cjx is the capacitance of the flying capacitor j,

VCjx is the voltage instantaneous value of the capacitor j
and VCjxref is the reference voltage of the flying capacitors.
Based on the selection of appropriate redundant vectors, Jx
can be minimized so that voltage across the capacitor is kept
close to the desired value, i.e., E/2. In order to minimize Jx :
dVCx
dJx
= Cx VCx
= VCx iCx 0, x {a, b, c} (6)
dt
dt
In the expression 6, iCx is the current through the capacitor
Cx which depends on the selected switching states and
contribution of the output current through correspondent x
phase.
This control technique was proposed for n-level FC inverters. However, in the specific case of a 3-level converter, this
technique resembles 2-level comparator due to the presence
of only one capacitor per phase and two redundant switching
states [11]. Best results may be achieved for FC converters
with n 4 levels.

Fig. 4. Waveforms generated from ITH-PDPWM method

The modulation index (ma ) is calculated as:

ma =

Vm
, (0 ma 1)
Vcr (n 1)

(4)

Where Vm and Vcr are the maximum values of the modulating signal and carrier wave, respectively, and n is inverters
number of levels. It can be expected maximum values lower
than in other modulation strategies. Alternatively, the adding
of a zero sequence harmonic third term to the sinusoidal
reference signal increases the modulation index, without to
affect the quality of the output signals. An increase around
15 % in the index modulation can be achieved by including a
voltage component with triple frequency and one sixth of the
amplitude reference signal [10].

B. Applying Three-level Comparators

In this type of control technique, each error signal


VCx = VCjx VCjxref , x {a, b, c}, is subjected to
a hysteresis comparator, as ilustrated in Fig. 5. The transition
band is defined around the reference value (VCjxref ).
When the error reaches the upper or lower limit value, the
correspondent phase capacitor will be discharged or charged,
respectively. If the value of the error signal is located
within the range of hysteresis, no change on the capacitor
voltage is required. The range of hysteresis and switching
states should be appropriately selected to ensure the required
oscillation levels. Table II presents the conditions considered
for OA /OB states selection [12].
For this control scheme, the maximum deviation of a FC
voltage in relation to the reference value is defined by [11]:

Fig. 5. Balancing control technique by hysteresis comparator

TABLE II
OA /OB states selection
Input signals
VCjx < VCjxref
VCjx < VCjxref
VCjx > +VCjxref
VCjx > +VCjxref
VCjxref < VCjx < +VCjxref

VCmax =

Ix
Ix > 0
Ix < 0
Ix > 0
Ix < 0
-

Px
-1
1
1
-1
-

ixmax Tox
+ 2 VCjx
Cx

Selected State
B
A
A
B
-

(7)

Where imax is the maximum phase current and Tox is the

time interval of application of the state ox (k).
C. Associating Hysteresis Comparators and Maximum Current Observers
This strategy is seen as an extension of the flying capacitor
balancing methods by comparators, since this technique
includes phase current observers in the structures previously
shown, in way to localize the maximum values of the output
currents.
According to [13], in flying capacitor multilevel inverters,
output signals with lower harmonic content can be obtained if
the choice of switching patterns exclude the flying capacitor
charging and subsequent discharging (or vice-versa) at the
instants of occurrence of the peak currents. This proposal requires the online calculation of the derivatives phase currents
and control actions that allow modifications on the previous
selectec OA/OB state. Among the available methods, the
derivatives was obtained from backward difference approach
due to easy implementation in programmable digital devices.
Fig. 6 shows a phase current waveform and a resultant
profile obtained from the application of the OA /OB states,
where 0 + 10 and 0 10 indicate the states OA and OB ,
respectively. It can be observed, at the ocurrence instants of
positive or negative maximum values (detailed in the green
areas indicated by 1, 2 e 3), that there are not subsequent
switchings between the OA /OB states, what would imply
in charging and subsequent discharging (or discharging and
subsequent charging) of the flying capacitors.

Fig. 6. Phase current ia and resultant profile of the flying capacitor

charging/discharging

IV.

SIMULATION RESULTS

Initially, the performance of all voltage balancing algorithms was evaluated in relation to the harmonic content of
output signals. The PowerGUI Block, a resource available in
MatLab-Simulink Toolbox, was used to perform the spectral
analyses. In these analyses, the magnitudes of harmonics
are calculeted in relation to magnitude of the fundamental
frequency of 60Hz. Although the harmonic frequency range
has been adjusted between 0 to 1M Hz, the results are shown
until the 20st frequency component, highlighting the range
where this load type is more susceptible.Therefore, it is worth
to observe that a large contribution to the THD is located
around the switching frequency, in this case, around 80 times
the machines rated frequency. Other aspect of these spectral
analysis refers to the presence of interharmonic components,
studies more detailed can be found in [14].
These simulations were carried out by a three-level FC
inverter supplying a three-phase induction machine (IM). The
load modeling was developed from the physical parameters
of an actual IM, the same motor used in the experimental
setup. The DC bus voltage was E = 200 VDC , the flying
capacitors were calculated as C = 470F, the frequency of
the reference voltage vector was 60Hz and the switching
frequency (FP W M ) equal to 4.8kHz, corresponding to a
frequency ratio equal to 60. At first, the amplitude modulation
index was adjusted in m = 0, 5.
A. SVPWM Method with Hysteresis Comparators
In this type of comparator, the voltage range or hysteresis
around the flying capacitor reference voltage must be defined
as a function of the estimated noise. For these simulations,
it was chosen a range VCjxref = 1V , x {a, b, c}. The
voltage waveform on the flying capacitor of the phase a is
shown in Fig. 7.
If compared with 2-level controllers, the hysteresis comparators involve a smaller number of commutations between
the states OA and OB and, despite the increased of ripple
voltage on the flying capacitors, the total distortion of output
current and voltage is reduced and the inverters present more
robustness in relation to the measurement noise.

number of state transitions and, consequently, the reduction

of the switching losses.

(a) Voltage waveform

(a) Voltage waveform

(b) Details of the voltage oscillations

Fig. 7. Flying capacitor voltage using SVPWM method.

(b) Details of the voltage oscillations

Fig. 8 shows the frequency espectrum for the phase-tophase Vab . The amplitude of the fundamental component
(V1 = 173.2 V for rated frequency = 60 Hz) was not shown
to emphasize the incidence of other harmonics. The total
harmonic distortion was evaluated as T HD = 20.93%.

Fig. 9. Flying capacitor voltage with Maximum Control Current

Fig. 10. Frequency spectrum and THD of voltage Vab using

Hysteresis Comparators with Maximum Current Observers
Fig. 8. Frequency spectrum and THD of output phase-to-phase
voltage Vab , using 3-level Comparators

B. SVPWM Method with Hysteresis Comparators and Maximum Current Observers

Fig. 9 presents the voltage waveform on the flying
capacitor of the phase a. It can be observed an increasing
of the voltage deviation in relation to the reference voltage
due to maintenance of the O states, near to occurrence of a
maximum of current.
Fig. 10 shows the spectral analysis of phase-phase output
voltage, using this method. The voltage fundamental component (V1 = 172.9 V) and THD value (T HD = 21.08%)
showed slightly less satisfactory results if compared with
hysteresis comparators without maximum capacitor current
control. However, it is important to consider the reduction of

C. PDPWM Method
The simulation of the PDPWM method was performed
using assymetrical sampling, where the reference signals are
sampled twice per PWM period, at their positive and the
negative peak values. This value keeps constant during only
half time. The assymetrical sampling frequency results in
switching frequency twice higher and a better approximation
between the output voltages and the reference signals [8].
Experiments were carried out using simple 2-level controllers for the flying capacitor voltage balancing. Equivalent
results were achieved if compared to the applying of the
SVPWM technique and 3-level comparators. The flying
capacitor voltage of the phase a can be read off from Fig.
11 . As expected, the average value is equal to E/2 and the
oscillations are smaller than previous studied cases.

tion index m = 0.5 for all strategies but with different PWM
switching frequencies.

(a) Voltage waveform

Fig. 13. Frequency spectrum and THD of voltage Vab , including

the third harmonic component

It worth to observe that distinct definitions are used for

the modulation indices in relation to the methods based on
space vector ou carrier-waves. Observing Fig. 14, where the
reference and instantaneous output voltage waveforms are
indicated, it can be to stablish the following expression:

(b) Details of the voltage oscillations

Fig. 11. Voltage across the phase a capacitor (2-level Comparator)

Fig. 12 presents spectrum analysis output phase-to-phase

voltage. The magnitude of the fundamental component is
equal to V1 = 172V and rate T HD = 18.90%. It can
be observed a reduction in the maximum value of the
fundamental component and THD, when compared with
values obtained from the SVPWM strategy.

Fig. 14. Modulation

Vm = ma

E
2

(8)

Replacing (8) in (3), it can be found a relationship between

the modulation indices of SVPWM and LSPWM methods as:
m=

Fig. 12. Harmonic spectrum and THD of voltage Vab , using

PDPWM

The performance of PDPWM can be improved by adding

an appropriate amount of the third harmonic component to
the reference voltage signals. The injection of a portion of
the third harmonic component ensures a higher peak value of
the fundamental component (Vm = 198.6 V or +15%) and a
significative reduction in THD rate in relation to the results
previously obtained. Fig. 13) presents these new results.
D. Comparative Analysis
Aimed at comparative analysis, this section summarizes
the results obtained in relation to the presented techniques .
Initially, simulations were performed with the same modula-

ma
2

(9)

Table III depicts the resultant values for THD and rms
voltage for SVPWM, PDPWM without and includind the 3rd
harmonic component (ITH). It is clear the improvement of
the performance betweeen PDPWM and SVPWM as well as
PDPWM-ITH in relation the these previous methods.
TABLE III
Comparison of the strategies (m = 0.5 / ma = 1)

FP W M (Hz)
600
1200
2400
4800
9600

SVPWM
THD
VRM S
34,70%
127,6
35,08%
129,3
21,92%
129,4
21,08%
128,1
14,77%
129,2

PDPWM
THD
VRM S
36,39%
130,0
33,24%
129,8
25,71%
129,1
18,98%
129,7
19,53%
129,4

PDPWM-ITH
THD
VRM S
27,83%
146,5
25,82%
146,6
20,07%
144,6
15,01%
144,2
16,67%
144,7

The best results as function of the frequencies and

presented in Table III were tested considering different

modulation indices as shown by Table IV (m = 0.35) /

ma = 0.7) and Table V (m = 0.4) / ma = 0.8). It can be
proved that the lowest THD levels are obtained for previous
modulation index, i.e., m = 0.5 / ma = 1.
TABLE IV
Comparison of the strategies (m = 0.35) / ma = 0.7)

FP W M (Hz)
4800
9600

SVPWM
THD
VRM S
21,49%
91,40
14,77%
91,41

PDPWM
THD
VRM S
26,63%
93,21
24,03%
93,17

PDPWM-ITH
THD
VRM S
24,10%
106,5
18,15%
104,9

TABLE V
Comparison of the strategies (m = 0.4) / ma = 0.8)

FP W M (Hz)
4800
9600

V.

SVPWM
THD
VRM S
24,91%
105,3
17,46%
103,4

PDPWM
THD
VRM S
26,28%
105,3
20,57%
104,6

PDPWM-ITH
THD
VRM S
23,31%
118,7
15,32%
119,7

(a) Phase-to-phase output voltage (b) Voltage oscillations across the aphase capacitor
Vab

Fig. 16. Voltage waveforms using the 3-level comparator

Fig. 17 depicts the results of the spectral analysis, where

the amplitude of the fundamental component of phase-tophase voltage Vab is V1 = 176.3 V and the value of
total harmonic distortion T HD = 32.07%. In addition, the
harmonic components with magnitudes from, approximately,
0.5 to 1.5% of the fundamental component, (e.g., 2a to 5a ),
contribute more significantly to the total harmonic distortion.

EXPERIMENTAL CASE STUDY

A 3-level flying capacitor inverter prototype was implemented to drive a three-fase induction motor of 1/4 HP 230V/460V, Model 5K33GN2A, manufactured by Marathon.
The main components of the inverter are Semikron Module
IGBT SKM50GB063D, flying capacitors of 470F/450V and
digital signal processor TMS320F2812 (Texas Instruments
Inc.).The operating conditions were adjusted to the same
parameter settings used in the simulation. The control signals
comprising the three reference voltages, output currents and
flying capacitor voltages were sampled once time by each
modulation period.
Initially, there are presented some results using the traditional 2-level comparators. Fig. 15 shows output phase-tophase voltage waveform and details of the capacitor voltages
where one can be clearly observed the presence and effects of
measurement noise.

The output phase-to-phase voltage Vab and voltage oscillations across the a-phase flying capacitor, using SVPWM
technique associated with hysteresis controllers and current
observers, are presented in Fig. 18. As shown in the 2-level
controller, it can be noted the improvement of distribution
and balancing of the intermediary levels, despite the presence
of noise in signals measured. This demonstrates a greater
robustness in relation to the external disturbances.

(a) Phase-to-phase output voltage (b) Voltage oscillations across aphase flying capacitor
Vab

(a) Phase-to-phase output voltage (b) Voltage oscillations across the aphase capacitor
Vab

Fig. 15. Voltage waveforms using the 2-level comparator

Fig. 18. Voltage waveforms controlling maximum current

The output phase-to-phase voltage Vab and voltage oscillations across the a-phase flying capacitor, using SVPWM
technique associated with hysteresis controllers, are shown in
Fig. 16. It can be noted the improvement of distribution and
balancing of the intermediary levels, despite the presence of
noise in signals measured.

Fig. 19 shows the frequency spectrum of the output voltage

signals including maximum current control technique. If
compared with the results obtained from 3-level controller,
it confirms the increase of the magnitude of the fundamental
component (V1 = 179.9 V) and a lower harmonic distortion
rate (THD = 31.84 %). In this case, it can be observed

Fig. 17. Frequency spectrum and THD of voltage Vab , using

3-level comparator

different harmonic components within of range from 0.5 to

2.5 % of the amplitude of the fundamental component.

Fig. 19. Frequency spectrum and THD of voltage Vab , including

maximum current observers

VI.

CONCLUSION

As initially proposed, this paper presented studies and

comparative analyses involving the space vector and carrierwave pulse width modulation techniques associated with
different methods of balancing of the intermediary voltages
in flying capacitor multilevel inverters.
Among them, the SVPWM associated with hysteresis
comparators showed better indices of total harmonic distortion and rms/DC voltage rates if compared to the traditional
PDPWM. It can be also noticed that PDPWM-ITH showed
best performance in relation to the previous cases except at
the highest switching frequency.
According to the results obtained from the inclusion of
maximum current observers during charging /discharging of
the flying capacitores, it is assumed that more detailed studies
should be performed. Overall, the obtained simulation and
experimental results confirm the good performance of the
presented alternatives.
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