Professional Documents
Culture Documents
ANNA UNIVERSITY
Regulation - 2013
DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
EC6311-Analog and Digital Communication Laboratory
(II Year B.E - ECE, III Semester)
Prepared by,
Mr.K.Sivakumar, AP(SS)/ECE
Ms.V.Subashini, AP/ECE
STAFF-IN CHARGE
Semester 03
of Technology
HOD/ECE
Department of ECE
PRINCIPAL
Rajalakshmi Institute
Page 1
SYLLABUS
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 2
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 3
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 4
LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS
1.
2.
3.
4.
5.
6.
7.
Introduction
- Study of electronic components [Active and Passive].
- Study of Regulated Power supply, Signal Generator, Function Generator
and CRO.
- Study of transistor parameters using Transistor Data Sheets.
Design and Analysis of Common Emitter Amplifier
- To Determine a. DC characters tics, b. AC characteristics, c. Gain,
d. Bandwidth, e. Gain- Bandwidth Product, f. SPICE Simulation of
Amplifier(Additional)
Design and Analysis of Common Collector Amplifier
- To Determine a. DC characteristics, b. AC characteristics, c. Gain,
d. Bandwidth, e. Gain- Bandwidth Product, f. SPICE Simulation of
Amplifier(Additional)
Design and Analysis of Common Base Amplifier
- To Determine a. DC characteristics, b. AC characteristics, c. Gain,
d. Bandwidth, e. Gain- Bandwidth Product, f. SPICE Simulation of
Amplifier(Additional)
Design and Analysis of Darlington Amplifier
- To Determine a. DC characteristics, b. AC characteristics, c. Gain
d. Bandwidth, e. Gain- Bandwidth Product, f. SPICE Simulation of
Amplifier(Additional)
Design and Analysis of Common Source Amplifier
- To Determine a. DC characteristics, b. AC characteristics, c. Gain
d. Bandwidth, e. Gain- Bandwidth Product, f. SPICE Simulation of
Amplifier (Additional)
Design and Analysis of Cascade Amplifier
- To Determine a. DC characteristics, b. AC characteristics, c. Gain
d. Bandwidth, e. Gain- Bandwidth Product, f. SPICE Simulation of
Amplifier (Additional)
Design and Analysis of Cascode Amplifier
- To Determine a. DC characteristics, b. AC characteristics, c. Gain
d. Bandwidth, e. Gain- Bandwidth Product, f. SPICE Simulation of
Amplifier (Additional)
8.
9.
10.
11.
12.
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 5
13.
14.
15.
Introduction
- Study of Digital IC's using IC data sheets
- Study of IC trainer Kit
Study Experiment-Verification of Logic Gates & Boolean Theorems and
Laws
16.
17.
18.
19.
20.
21.
Implementation of SISO, SIPO, PISO and PIPO shift registers using Flipflops
CONTENT BEYOND SYLLABUS
23.
Bridge Rectifier
24.
Seven Segment Display
22.
INDEX
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 6
Date
Page No.
Sign
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 7
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 8
01
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using voltage divider
bias and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
2. REQUIREMENTS:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 9
Requireme
nt
Name
Transistor [Active]
Range
Quantity
BC 107
(0-3)MHz
30MHz
(0-30)V
Resistor [Passive]
2
Component
Watt , + 1%
Tolerence
Capacitor [Passive]
Signal
4
5
Generator[SG]
Equipment
Regulated power
supply
7
8
CRO
Bread Board
Accessories
Connecting Wires
Single strand
as
required
DESIGN PROCEDURE:
Given specifications:
VCC= 10V, IC=1.2mA, AV= 30, hFE= 100
(i) To calculate RC:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 10
3. THEORY:
A common emitter amplifier is type of BJT amplifier which increases the
voltage level of the applied input signal Vin at output of collector.
The CE amplifier typically has a relatively high input resistance (1 - 10 K)
and a fairly high output resistance. Therefore it is generally used to drive
medium to high resistance loads. It is typically used in applications where a
small voltage signal needs to be amplified to a large voltage signal like radio
receivers.
The input signal Vin is applied to base emitter junction of the transistor and
amplifier output Vo is taken across collector terminal. Transistor is
maintained at the active region by using the resistors R1,R2 and Rc. A very
small change in base current produces a much larger change in collector
current. The output Vo of the common emitter amplifier is 180 degrees out
of phase with the applied the input signal V in.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier
using AC analysis.
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 11
MSH
output voltage Vo for at least 20 different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi) dB
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph
taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
where f1 lower cut-off frequency
f2 upper cut-off frequency
a.
DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
ii)
iii)
iv)
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
Department of ECE
Rajalakshmi Institute
Page 12
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
the
amplitude
MSH
of
the
input
signal
find
MSH
= _________ volts
MODEL GRAPH:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 13
S. NO
/2) =____________V
MSH
FREQUENCY
OUTPUT VOLTAGE
[Hz]
[ VO] in Volts
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 14
With Feedback :
Input voltage (Vin=V
S. NO
/2) =____________ V
MSH
FREQUENCY
OUTPUT
[Hz]
VOLTAGE [ VO] in
Volts
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 15
WORKSHEET
5. RESULT:
INFERENCE:
The Common Emitter Amplifier was constructed and the following results
were determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 16
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 17
MODEL GRAPH:
Department of ECE
Rajalakshmi Institute
Page 18
DATE:
1. OBJECTIVE:
To Design and Construct a Common collector Amplifier and to determine
its:
a.
b.
c.
d.
e.
2.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product using frequency response curve
REQUIREMENTS:
Requiremen
S.No
Name
Components
Transistor [Active]
Resistor [Passive]
Capacitor [Passive]
Signal Generator
Equipment
[SG]
CRO
Range
Quantity
BC 107
0-3MHz
0-30MHz
0-30 V
Single strand
as required
Regulated power
supply
Accessories
Bread Board
Connecting Wires
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 19
(ii)
3.
THEORY:
A common collector amplifier is a unity gain BJT amplifier used for
Department of ECE
Rajalakshmi Institute
Page 20
2.
3.
Determine Maximum input voltage that can be applied to CE amplifier
using AC analysis.
3. Set the input voltage Vin=V MSH /2 and vary the input signal frequency
from 0Hz to 1MHz in incremental steps and note down the corresponding
output voltage Vo for at least 15 different values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vin)
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph
taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
Where f1 - lower cut-off frequency
f2 - upper cut-off frequency
a. DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
i)
Set Vin = 0 by reducing the amplitude of the input signal
from signal generator
ii)
Open circuit the capacitors since it blocks DC voltage
iii)
Set VCC= +10v and measure the voltage drop across the
Resistor VRC, voltage across Collector- Emitter Junction VCE
and Voltage drop across base emitter junction. V BE
iv)
Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 21
(forward bias)
2. VRC
= ____________
3. VCE
Procedure:
i.
Apply input signal Vin = 1 V of 1Khz frequency to the CC
amplifier using the signal generator between base emitter
junction of the transistor. Find the sinusoidal output using
CRO across RL.
ii.
By increasing the amplitude of the input signal find
maximum input voltage V MSH across VBE at which the
sinusoidal signal gets distorted during the process which can
be seen in the CRO. The amplitude obtained at this point is
maximum voltage that can be applied to the transistor for
efficient operating of transistor.
V
MSH
= _________ volts
5. TABULATION
Input voltage (Vin=V
S. NO
Semester 03
of Technology
MSH
FREQUENCY
[Hz]
[ VO] in Volts
Department of ECE
Rajalakshmi Institute
Page 22
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
WORKSHEET
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 23
6. RESULT:
INFERENCE:
The common collector amplifier was constructed and input resistance and gain
were determined. The results are found to be as given below
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 24
CONCLUSION:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 25
MODEL GRAPH:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 26
DATE:
1. OBJECTIVE:
To Design and Construct a Common Base Amplifier and to determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Transistor [Active]
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
power (0-30)V
1
1
Accessories
8
Connecting Wires
Single strand
as required
DESIGN PROCEDURE:
Given Transistor specifications:
hie = 2.1k ; hfe = 75 ; hfb =0.987
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 27
3. THEORY:
A common base amplifier is type of BJT amplifier which increases the
voltage level of the applied input signal Vin at output of collector.
The Common base amplifier typically has good voltage gain and relatively
high output impedance. But the Common base amplifier unlike CE amplifier has
very low input impedance which makes it unsuitable for most voltage amplifier. It
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 28
a. DC ANALYSIS:
Semester 03
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Department of ECE
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Page 29
iv)
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
MSH
= _________ volts
5. TABULATION
Input voltage (Vin=V
Semester 03
of Technology
MSH
/ 2) =____________V
Department of ECE
Rajalakshmi Institute
Page 30
S. NO
FREQUENCY
[Hz]
17.
18.
100
19.
500
20.
600
21.
800
22.
900
23.
1 KHz
24.
100 KHz
25.
500 KHz
26.
600 KHz
27.
OUTPUT
VOLTAGE
[ VO] in Volts
700 KHz
28.
800 KHz
29.
900 KHz
30.
1 MHz
31.
1.1 MHz
32.
1.5 MHz
WORKSHEET
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 31
6. RESULT:
INFERENCE:
The Common base amplifier was constructed and input resistance and gain were
determined. The results are found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 32
CONCLUSION:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 33
MODEL GRAPH:
DARLINGTON AMPLIFIER
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 34
EXPERIMENT:04
DATE:
1. OBJECTIVE:
To Design and Construct a BJT amplifier using Darlington pair and to
determine its:
a.
b.
c.
d.
e.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product using frequency response curve
2. REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Transistor [Active]
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
power (0-30)V
Bread Board
1
1
Accessories
8
Connecting Wires
Single strand
as required
DESIGN PROCEDURE:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 35
(iv) To Find CO :
3. THEORY:
The Darlington transistor (often called a Darlington pair) is compound
structure consisting of two bipolar transistors connected in such a way that the
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 36
a. DC ANALYSIS:
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 37
iv)
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
Semester 03
of Technology
MSH
= _________ volts
Department of ECE
Rajalakshmi Institute
Page 38
FREQUENCY
[Hz]
/2) =____________ V
MSH
OUTPUT
VOLTAGE
[ VO] in Volts
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
0
100
500
600
800
900
1 KHz
100 KHz
500 KHz
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 39
WORKSHEET
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 40
6. RESULT:
INFERENCE:
The Darlington amplifier was constructed and the results are found to be
a. Gain of the amplifier :
b. Bandwidth of the amplifier :
c. Gain-Bandwidth product :
CONCLUSION:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 41
MODEL GRAPH:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 42
DATE:
1. OBJECTIVE:
To Design and Construct a Common source
bootstrapped gate resistance and to determine its:
a.
b.
c.
d.
e.
2.
amplifier
using
the
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Transistor [Active]
Quantity
BFW10
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
power (0-30)V
1
1
Accessories
8
Semester 03
of Technology
Connecting Wires
Department of ECE
Single strand
as required
Rajalakshmi Institute
Page 43
DESIGN ANALYSIS :
Given :
VDD = 20 V, IDSS = 5mA, ID = 1.5 mA,
i) To Find the voltage across the Gate-source region (V GS)
VGS = ID RS
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 44
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 45
a. DC ANALYSIS:
iv)
To verify dc condition
1. VGS
= ____________
2. VDS
= ____________
3 ID
= _______
ii.
Semester 03
of Technology
MSH
= _________ volts
Department of ECE
Rajalakshmi Institute
Page 46
5. TABULATION
Input voltage (Vin=V
S. NO
/2) =____________V
MSH
FREQUENCY
[Hz]
OUTPUT
VOLTAGE
[ VO] in Volts
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
0
100
500
600
800
900
1 KHz
100 KHz
500 KHz
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 47
1 MHz
15.
1.1 MHz
16.
1.5 MHz
WORKSHEET
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 48
6. RESULT:
INFERENCE:
The common Source amplifier was constructed and input resistance and gain
were determined. The results are found to be as given below
a) Gain of the amplifier (in db) :
b) Bandwidth of the amplifier (in HZ) :
c) Gain-Bandwidth product (GBWP) :
CONCLUSION:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 49
MODEL GRAPH:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 50
CASCADE AMPLIFIER
EXPERIMENT:06
DATE:
1. OBJECTIVE:
To Design and Construct a Cascade Amplifier and to determine its:
a.
b.
c.
d.
e.
2.
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
REQUIREMENTS:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 51
Requirement
Name
Range
Transistor [Active]
Quantity
BC 107
Components
2
Resistor [Passive]
Capacitor [Passive]
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Equipment
power (0-30)V
Bread Board
1
1
Accessories
8
Connecting Wires
Single strand
as required
DESIGN PROCEDURE:
Given specifications:
VCC= 14 V, IC1=1.2mA, RL = 40K hFE= 100
(i) To calculate R5 :
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 52
(ii) To calculate R6 :
3. THEORY:
A cascade is type of multistage amplifier where two or more single stage
amplifiers are connected serially. Many times the primary requirement of the
amplifier cannot be achieved with single stage amplifier, because Of the
limitation of the transistor parameters. In such situations more than one
amplifier stages are cascaded such that input and output stages provide
impedance matching requirements with some amplification and remaining
middle stages provide most of the amplification. These types of amplifier circuits
are employed in designing microphone and loudspeaker.
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 53
a. DC ANALYSIS:
viii)
To verify dc condition
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 54
(forward bias)
2. VRC
= ____________
3. VCE
MSH
= _________ volts
5. TABULATION
Input voltage (Vin=V
S. NO
1.
2.
Semester 03
of Technology
MSH
FREQUENCY
[Hz]
OUTPUT
VOLTAGE
[ VO] in Volts
0
100
Department of ECE
Rajalakshmi Institute
Page 55
500
600
800
900
1 KHz
100 KHz
500 KHz
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
WORKSHEET
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 56
6. RESULT:
INFERENCE:
The Cascade amplifier was constructed and input resistance and gain were
determined. The results are found to be as given below
a) Gain of the amplifier :
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 57
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 58
MODEL GRAPH:
CASCODE AMPLIFIER
EXPERIMENT: 07
Semester 03
of Technology
DATE:
Department of ECE
Rajalakshmi Institute
Page 59
DC Characteristics
Maximum Signal Handling Capacity
Gain of the amplifier
Bandwidth of the amplifier
Gain -Bandwidth Product
2. REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Quantity
Transistor [Active]
BC 107
Resistor [Passive]
Capacitor [Passive]
10f, 100f
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Components
1,1,1,2
2,1
Equipment
power (0-30)V
Bread Board
1
1
Accessories
8
Connecting Wires
Single strand
as required
DESIGN PROCEDURE:
Given specifications:
VCC= 20V, IC =1.2mA, AV= 30, , RL = 90K ;
Transistor Parameters: hFE= 50 , hie = 1.2K and hib= 24
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 60
To Find C2 :
To Find C3 :
To Find C4 :
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 61
THEORY:
The cascode configuration has one of two configurations of multistage
amplifier. In each case the collector of the leading transistor is connected to the
emitter of the following transistor. The arrangement of the two transistors is
shown in the circuit diagram. The cascode amplifier consists of CE stage
connected in series with CB stage. The arrangement provides a relatively high
input impedance with low voltage gain for the first stage to ensure the input
miller capacitance is at a minimum, whereas the following CB stage provides an
excellent high frequency response.
Features:
1. It provides high voltage gain and has high input impedance.
2. It provides high stability and has high output impedance
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the CE amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to CE amplifier
using AC analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency
from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage V o for
atleast 20 different
values for the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph
taking frequency on xaxis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1
where
a. DC ANALYSIS:
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 62
xii)
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
Semester 03
of Technology
MSH
= _________ volts
Department of ECE
Rajalakshmi Institute
Page 63
S. NO
/2) =____________ V
MSH
FREQUENCY
[Hz]
OUTPUT
VOLTAGE
[ VO] in Volts
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
0
100
500
600
800
900
1 KHz
100 KHz
500 KHz
600 KHz
700 KHz
12.
800 KHz
13.
900 KHz
14.
1 MHz
15.
1.1 MHz
16.
1.5 MHz
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 64
WORKSHEET
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 65
6. RESULT:
INFERENCE:
The Cascode amplifier was constructed and input resistance and gain were
determined. The results are found to be as given below
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 66
Circuit Diagram
WITHOUT FILTER:
WITH FILTER:
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 67
Date
AIM:
To construct half wave rectifier with and without filter and to draw their input and output
waveforms and find out ripple factor.
S.No.
1.
2.
3.
4.
5
6
7
8
9
Requirement List
Components
Equipments
Other Accessories
Name
Transformer
Diode
Resistor
Capacitor
Regulated power supply
Signal Generator
CRO
Bread Board
Connecting Wires
Range
230 V / 6-0-(-6)
IN4007
1 k
100F
(0-30)V
(0-3)MHz
30 MHz
Single strand
Quantity
1
1
1
1
1
1
1
1
as reqd.
Requirements:
THEORY:
Half wave rectifier:
A rectifier is a circuit, which uses one or more diodes to convert A.C voltage into D.C voltage. In this
rectifier during the positive half cycle of the A.C input voltage, the diode is forward biased and
conducts for all voltages greater than the offset voltage of the semiconductor material used. The
voltage produced across the load resistor has same shape as that of the positive input half cycle of A.C
input voltage.
During the negative half cycle, the diode is reverse biased and it does not conduct. So there is no
current flow or voltage drop across load resistor. The net result is that only the positive half cycle of
the input voltage appears at the output.
FORMULA USED:
Ripple Factor =
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 68
MODEL GRAPH:
TABULATION
HALF WAVE RECTIFIER:
With filter
Time period
Output signal
Amplitude(V)
Time period
Ripple Factor
Ripple factor is defined as the ratio of rms value of ac component to the dc
component in the output.
Ripple factor
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 69
Vav the average or the dc content of the voltage across the load is given by
Ripple Factor
Efficiency
Efficiency, is the ratio of the dc output power to ac input power
Thus
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 70
PROCEDURE:
1.
2.
3.
4.
RESULT:
Thus the half wave rectifier was constructed and its input and output waveforms are
drawn. The ripple factor of capacitive filter is calculated as
Ripple factor=
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 71
Circuit Diagram
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 72
Requirement List
S.No.
1.
2.
3.
4.
5
6
7
8
Components
Equipments
Other Accessories
Exp. No
Name
Transformer
Diode
Resistor
Capacitor
Regulated power supply
Signal Generator
CRO
Bread Board
Range
230 V / 6-0-(-6)
IN4007
1 k
100f
(0-30)V
(0-3)MHz
30 MHz
-
Connecting Wires
Single strand
Quantity
1
2
1
2
1
1
1
1
as reqd.
Date:
AIM:
To construct a full wave rectifier and to calculate the ripple factor.
REQUIREMENTS
THEORY:
The full wave rectifier conducts for both the positive and negative half cycles of the input ac
supply. In order to rectify both the half cycles of the ac input, two diodes are used in this circuit. The
diodes feed a common load RL with the help of a centre tapped transformer. The ac voltage is applied
through a suitable power transformer with proper turns ratio. The rectifiers dc output is obtained
across the load. The dc load current for the full wave rectifier is twice that of the half wave rectifier.
The lowest ripple factor is twice that of the full wave rectifier. The efficiency of full wave rectification
is twice that of half wave rectification. The ripple factor also for the full wave rectifier is less
compared to the half wave rectifier.
FORMULA USED:
Ripple Factor =
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 73
MODEL GRAPH
TABULATOIN:
With filter
Time period
Output signal
Amplitude(V)
Time period
Ripple Factor
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 74
The average voltage or the dc voltage available across the load resistance is
Efficiency
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Page 75
PROCEDURE:
1. Connections are given as per the circuit diagram wiyhout filter.
2. Note the amplitude and time period of the input signal at the secondary winding of the
transformer and rectified output.
3. Repeat the same steps with the filter and measure Vdc.
4. Calculate the ripple factor.
5. Draw the graph for voltage versus time.
CONCLUSION
Thus, the full wave rectifier was constructed and the ripple factor was calculated as Ripple
factor =
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 76
MODEL WAVEFORM
V in = 50mV
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 77
Date:
AIM:
To construct a Class A power amplifier and observe the waveform and to compute maximum
power dissipation and efficiency.
REQUIREMENTS:
S.No.
1.
2.
3.
4.
5.
6.
7.
Name
Transistor
Resistor
Capacitor
Signal Generator
CRO
Regulated power supply
Bread Board
Range
SL100
61k,10K,1K, 2.2K
10F, 10F, 100F
(0-3)MHz
30MHz
(0-30)V
Quantity
1
1,1,2,1
1,1,1
1
1
1
1
THEORY:
The power amplifier is said to be Class A amplifier if the Q point and the input signal
are selected such that the output signal is obtained for a full input signal cycle.
For all values of input signal, the transistor remains in the active region and never enters into
cut-off or saturation region. When an a.c signal is applied, the collector voltage varies sinusoidally
hence the collector current also varies sinusoidally. The collector current flows for 360 0 (full cycle) of
the input signal. i e the angle of the collector current flow is 360 0 .
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 78
Department of ECE
Rajalakshmi Institute
Page 79
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set Vi =50 mv, using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 10 Hz to 1M Hz in regular steps and
note down the corresponding output voltage.
4. Plot the graph; Gain (dB) vs Frequency(Hz).
CONCLUSION:
Thus the Class A power amplifier was constructed. The following parameters were calculated:
`
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 80
CIRCUIT DIAGRAM
With Distortion
Without Distortion
Semester 03
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Page 81
Requirement List
Components
Equipments
Name
Transistor
Resistors
capacitor
DIODE
Regulated power supply
Signal Generator
CRO
Bread Board
Other Accessories
8.
Connecting Wires
Exp. No.
Range
SL100,SK100
4.7k, 15 k
100F
IN4007
(0-30)V
(0-3)MHz
30 MHz
-
Quantity
1,1
2,1
2
2
1
1
1
1
Single strand
as reqd.
Date:
AIM:
To construct a Class B complementary symmetry power amplifier and observe the waveforms
with and without cross-over distortion and to compute maximum power delivered and efficiency.
REQUIREMENTS:
THEORY:
A power amplifier is said to be Class B amplifier if the Q-point and the input signal are
selected such that the output signal is obtained only for one half cycle for a full input cycle. The Qpoint is selected on the X-axis. Hence, the transistor remains in the active region only for the positive
half of the input signal.
There are two types of Class B power amplifiers: Push Pull amplifier and complementary symmetry
amplifier. In the complementary symmetry amplifier, one n-p-n and another p-n-p transistor is used.
The matched pair of transistor are used in the common collector configuration. In the positive half
cycle of the input signal, the n-p-n transistor is driven into active region and starts conducting and in
negative half cycle, the p-n-p transistor is driven into conduction. However there is a period between
the crossing of the half cycles of the input signals, for which none of the transistor is active and
output, is zero
FORMULA:
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 82
Theoretical Calculation
= AC (output) / DC (Input) = Pac / Pdc
Pac = Vrms x Irms = Vm/2 x Im/2
Pac = VmIm / 2
Pdc = Vcc x Idc
Idc = Im /
Pdc = (Vcc x Im/)
Since two transistors involved
Pdc = (2Vcc x Im/)
= AC (output) / DC (Input) = Pac / Pdc
= [(VmIm/2) / (2VccIm/)]
for max output Vm = Vcc
= /4 = 0.7854
% = 78.54%
Practical Efficiency
= AC (output) / DC (Input) = Pac / Pdc
= [(VmIm/2) / (2VccIm/)]
= /4 x (Vm/Vcc) x 100
=
%=
To find max power dissipation
Pd = 0.4 x Pac (max)
= 0.4 x (Vcc2/2RL)
=
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 83
OBSERVATION
Input Voltage = 12V (p-P)
Amplitude (volts)
With Distortion
Without Distortion
MODEL GRAPH
PROCEDURE:
1. Connections are given as per the circuit diagram without diodes.
2. Observe the waveforms and note the amplitude and time period of the input signal and
distorted waveforms.
3. Connections are made with diodes.
4. Observe the waveforms and note the amplitude and time period of the input signal and
output signal.
5. Draw the waveforms for the readings.
6. Calculate the maximum output power and efficiency.
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 84
CONCLUSION:
Thus the Class B complementary symmetry power amplifier was constructed to observe
cross-over distortion and the circuit was modified to avoid the distortion. The following parameters
were calculated:
a)Maximum power dissipation =
b)Efficiency=
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 85
Differential Mode :
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 86
DIFFERENTIAL AMPLIFIER
Exp. No.:
Date:
1. OBJECTIVE:
To Design and Construct a Differential Amplifier using BJT
determine its:
a.
b.
c.
d.
2.
and to
Transfer Characteristics
Gain of the amplifier in common mode
Gain of the amplifier in differential mode
CMRR (Common Mode Rejection Ratio)
REQUIREMENTS:
S.N
o.
Requirement
Name
Range
Transistor [Active]
Quantity
BC 107
signal Generator
(0-3)MHz
CRO
30MHz
Regulated
supply
Bread Board
Components
2
Resistor [Passive]
Capacitor [Passive]
4
Equipment
power (0-30)V
1
1
Accessories
8
Connecting Wires
Single strand
as required
3. THEORY:
A differential amplifier is a type of electronic amplifier that amplifies
the difference between two voltages but does not amplify the particular
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 87
need
for
differential
amplifier
arises
in
many
physical
MODEL GRAPH:
Differential amplifier Transfer Characteristics:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 88
4. PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the Differential amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using
AC analysis.
4. Determine the Transfer characteristics of Differential amplifier by plotting
the graph for normalized differential input voltage [ (Vb1 V b2) / VT ] vs.
Normalized collector current [ Ic / Io].
5. Calculate the voltage gain of differential amplifier for differential mode
as Ad = 20log (V0/Vi) , Where Vi = V1 V2
6. Calculate the voltage gain of differential amplifier for Common mode
as AC = 20log (V0/Vi) , Where Vi = (V1+ V2 / 2 )
7. Find the Common mode rejection ratio of differential amplifier using the
formula given below.
CMRR= 20 log10 ( Ad/Ac)
Where Ad- Differential mode gain in dB
Ac Common Mode gain in dB
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 89
a. DC ANALYSIS:
iv)
To verify dc condition
1. VBE :
(forward bias)
2. VRC
= ____________
3. VCE
Q point analysis:
It is the procedure to choose the operating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ )
b. Maximum signal handling capacity :
It is the process to find the maximum input voltage that can be
handled by the amplifier, so that it amplifies the input signal without any
distortion.
Procedure:
vii.
Apply input signal Vin = 20 mV of 1Khz frequency to the
amplifier using the signal generator between base emitter
junction of the transistor. Find the sinusoidal output using
CRO across RL.
viii.
By increasing the amplitude of the input signal find
maximum input voltage V MSH across VBE at which the
sinusoidal signal gets distorted during the process which can
be seen in the CRO. The amplitude obtained at this point is
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 90
MSH
= _________ volts
5. TABULATION
a. Transfer Characteristics Calculation:
S.no
Input Voltage
Vi = (Vb1 Vb2) in Volts
Output Current
Ic2 in Ampere
1.
2.
3.
4.
5.
6.
b. CMRR Calculation:
To Find Differential Gain (Ad ) :
S. NO
INPUT
VOLTAGE
in volts
OUTPUT VOLTAGE [
VO] in Volts
Differntial gain in dB
Ad = 20log (V0/Vi)
Where Vi = Vi1 Vi2
33.
Vi1
34.
Vi2
INPUT
VOLTAGE
in volts
OUTPUT VOLTAGE
[ VO] in Volts
1.
Vi1
2.
Vi2
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 91
6. RESULT:
INFERENCE:
The Differential amplifier was constructed and input resistance and gain were
determined. The results are found to be as given below
d) Trans-Conductance of Differential amplifier ( in millisiemens) :
e) Differential mode gain in dB
g) CMRR in dB
CONCLUSION:
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 92
WORKSHEET
Semester 03
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Department of ECE
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Page 93
Semester 03
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Department of ECE
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Page 94
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 95
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice
simulation tool and to determine its:
a. Gain of the amplifier
b. Bandwidth of the amplifier
c. Gain -Bandwidth Product
2. REQUIREMENTS:
S.n
o
Requirements
Quantity
PC
Pspice Software
THEORY:
A common emitter amplifer is type of BJT amplifier which increases the
voltage level of the applied input signal Vin at output of collector.
The CE amplifier typically has a relatively high input resistance (1 - 10 K)
and a fairly high output resistance. Therefore it is generally used to drive
medium to high resistance loads. It is typically used in applications where a
small voltage signal needs to be amplified to a large voltage signal like radio
receivers.
The input signal Vin is applied to base emitter junction of the transistor and
amplifier output Vo is taken across collector terminal. Transistor is
maintained at the active region by using the resistors R1,R2 and Rc. A very
small change in base current produces a much larger change in collector
current. The output Vo of the common emitter amplifier is 180 degrees out
of phase with the applied the input signal V in.
Semester 03
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Department of ECE
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Page 96
Semester 03
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Department of ECE
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Page 97
2. Select the parts required for the circuit from the parts
them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output
waveforms
MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results
were determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 98
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 99
DATE:
1. OBJECTIVE:
To Design and Construct a Common Emitter Amplifier using Pspice
simulation tool and to determine its:
a. Gain of the amplifier
b. Bandwidth of the amplifier
c. Gain -Bandwidth Product
2. REQUIREMENTS:
S. No
1
2
THEORY:
Requirements
PC
Pspice
Software
Quantity
1
-
There are three basic types of FET amplifier or FET transistor namely
common source amplifier, common gate amplifier and source follower amplifier.
The common-source (CS) amplifier may be viewed as a transconductance
amplifier or as a voltage amplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating
the current going to the load.
ii) As a voltage amplifier, input voltage modulates the amount of current
flowing through the FET, changing the voltage across the output resistance
according to Ohm's law.
However, the FET device's output resistance typically is not high enough
for a reasonable transconductance amplifier (ideally infinite), nor low enough for
a decent voltage amplifier (ideally zero). Another major drawback is the
amplifier's limited high-frequency response. Therefore, in practice the output
often is routed through either a voltage follower (common-drain or CD stage), or
a current follower (common-gate or CG stage), to obtain more favorable output
and frequency characteristics
Semester 03
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Department of ECE
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Page 100
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 101
2. Select the parts required for the circuit from the parts
them in the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output
waveforms
MODEL GRAPH:
4.RESULT:
INFERENCE:
The Common Emitter Amplifier was simulated and the following results
were determined:
a) Gain of the amplifier :
b) Bandwidth of the amplifier :
c) Gain-Bandwidth product :
CONCLUSION:
Semester 03
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Department of ECE
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Page 102
WORKSHEET
Semester 03
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Department of ECE
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Page 103
DIGITAL EXPERIMENTS
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Page 104
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Department of ECE
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Page 105
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Department of ECE
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Page 106
Department of ECE
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Page 107
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Page 108
NAND Gate
NOR Gate
NOT Gate
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Page 109
OR Gate
AND Gate
Ex - OR Gate
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Page 110
Expt. No:
Date:
AIM:
To study various logic gates and Boolean Theorems And Laws to verify the
truth table.
COMPONENTS / EQUIPMENTS REQUIRED:
S. No.
Components /
Equipments
Specificatio
n
Quantity
1.
---
2.
AND Gate
IC7408
3.
OR Gate
IC7432
4.
NOT Gate
IC7404
5.
NAND Gate
IC7400
6.
NOR Gate
IC7402
7.
Ex-Or Gate
IC7486
8.
Connecting Wires
---
Sufficient Numbers
THEORY:
AND gate: The AND gate is a digital logic gate that implements logical
conjunction - it behaves according to the truth table given. A HIGH output (1)
results only if both the inputs to the AND gate are HIGH (1). If neither or only
one input to the AND gate is HIGH, a LOW output results. In another sense, the
function of AND effectively finds the minimum between two binary digits.
Semester 03
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Page 111
NAND gate: The Negated AND, NO AND or NAND gate is the opposite
of the digital AND gate, and behaves in a manner that corresponds to the
opposite of AND gate, as shown in the truth table. A LOW output results only if
both the inputs to the gate are HIGH. If one or both inputs are LOW, a HIGH
output results. The NAND gate is a universal gate in the sense that any
boolean function can be implemented by NAND gates. NAND gates can also be
made with more than two inputs, yielding an output of LOW if all of the inputs
are HIGH, and an output of HIGH if any of the inputs is LOW.
NOR gate
: The NOR gate is a digital logic gate that implements
logical NOR - it behaves according to the truth table to the right. A HIGH
output (1) results if both the inputs to the gate are LOW (0). If one or both input
is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the
OR operator. NOR is a functionally complete operationcombinations of NOR
gates can be combined to generate any other logical function. By contrast,
the OR operator is monotonic as it can only change LOW to HIGH but not vice
versa.
EX- OR gate: The XOR gate (sometimes EOR gate) is a digital logic
gate that implements an exclusive disjunction; that is, it behaves according to
the truth table shown on the right. A true output (1) results if one, and only
one, of the inputs to the gate is true (1). If both inputs are false (0) and both are
true (1), a false output (0) results. A way to remember XOR is "one or the other
but not both.
LOGIC DIARGAM:
AND Gate:
Logic Diagram:
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OR Gate:
Truth Table:
Logic Diagram
Department of ECE
Truth Table:
Rajalakshmi Institute
Page 112
Y=A+B
NOT Gate:
Logic Diagram:
Truth Table:
NAND Gate:
Truth
Y=A
Y= (AB)
NOR Gate:
Logic Diagram:
DeMorgan's Theorem:
Table:
Logic Diagram
Ex-OR Gate:
Truth Table:
Logic Diagram
Truth Table:
Department of ECE
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Observations:
Commutative Law:
Law:
Associative
A(BC)
(AB)
C
DeMorgans Law:
A
(A+B
)
A.B
PROCEDURE:
1. Give the connections as per the pin diagram (AND gate).
2. Switch on the trainer kit.
3. Apply the binary inputs at the appropriate terminal and observe the
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 114
Semester 03
of Technology
Department of ECE
Rajalakshmi Institute
Page 115
DATE:
1. OBJECTIVE:
To design and verify the truth table of the following code converters
a.
b.
c.
d.
S. No.
1.
2.
Components /
Equipments
Specifications
Quantity
---
Digital IC trainer
NOT, AND, OR, Ex-OR
Gate Connecting wires
IC7404,7408,7432,
7486
1 in each
3. THEORY:
Binary to GRAY Converter:
By representing the ten decimal digits with a four bit Gray code, we
have another form of BCD code. The Gray code however can be extended to
any number of bits and conversion between binary code and Gray code is
sometimes useful. The following rules apply for conversion:
1. The MSB in the Gray code is the same as the corresponding bit in the binary
number.
2. Going from left to right, add each adjacent pair of binary bits to get the
next Gray code bit. Disregard carries.
GRAY to Binary Converter:
To convert from Gray code to binary code, A similar method is used, at
there are some differences. The following rules apply:
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Page 116
B3
B2
B1
B0
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G3
Department of ECE
Gray code
G2
G1
G0
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Gray Code
G3
G2
G1
G0
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B3
Department of ECE
Binary Code
B2
B1
B0
Rajalakshmi Institute
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K-Map
K-Map
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BCD input
B3
B2
B1
B0
Excess 3 output
G3
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G2
G1
G0
K-Map
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K-Map
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Excess 3 Input
B3
B2
B1
B0
BCD Output
G3
K-Map for A:
G2
G1
G0
K-Map
for B:
K-Map for C:
K-Map
for D:
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Page 123
4. PROCEDURE:
1. Connections are given as per the circuit diagram (Binary to GRAY).
2. Switch on the power supply.
3. Verify the truth table given for different inputs.
4. Repeat the above procedures for other converters.
5. Results:
INFERENCE:
Thus the truth tables for Binary to Gray, Gray to Binary and BCD to
Excess3 converters were verified.
CONCLUSION:
Semester 03
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Department of ECE
Rajalakshmi Institute
Page 124
DATE:
1. OBJECTIVE:
To study the 4 bit binary adder/subtractor using IC7483.
2. REQUIREMENTS:
S.No
.
Specificati
ons
Quantity
OR gate
IC 7432
AND gate
IC 7408
IC 7483
Connecting wires
some
3. THEORY:
The full adder/sub tractors are capable of adding/subtracting only two
single digit binary numbers along with a carry input. But in practice we need to
add/subtract binary numbers, which are much longer than just one bit. To
add/subtract two n-bit binary numbers we need to use the n-bit parallel
subtractor/adder.
Binary adder:
IC type 7483 is a 4-bit binary parallel
adder/subtractor .The two 4-bit input binary numbers are A1 through A4 and B1
through B4. The sum is obtained from S1 through S4. C0 is the input carry and
C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power
supply and ground terminals. Then connect the four A inputs to a fixed binary
numbers such as 1001 and the B inputs and the input carry to five toggle
switches. The five outputs are applied to indicator lamps. Perform the addition of
a few binary numbers and check that the output sum and output carry give the
proper values. Show that when the input carry is equal to 1, it adds 1 to the
output sum.
Binary subtractor :
The subtraction of two binary numbers can be done by
taking the 2s complement of the subtrahend and adding it to the minuend. The
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Operand1 C0
C4
Operand2
B3 B2 B1 B0
O/P
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CARRY
S4
S3
S2
S1
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K MAP
Y = S4 (S3 + S2)
LOGIC DIAGRAM OF BCD ADDER
4. PROCEDURE:
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DATE:
1. OBJECTIVE:
To design and implement multiplexer and demultiplexer using logic gates
2. REQUIREMENTS :
S.No
.
Specificati
on
Quantity
OR gate
IC7432
AND gate
IC7411
NOT gate
IC7404
Connecting wires
3. THEORY:
Multiplexer:
It has a group of data inputs and a group of control inputs. The
control inputs are used to select one of the data inputs and connected to the
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4:1 MULTIPLEXER:
BLOCK DIAGRAM
Circuit Diagram:
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1:4 DEMULTIPLEXER:
BLOCK DIAGRAM
Circuit Diagram:
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TRUTH TABLE:
8X1 Multiplexer
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1X8 De-Multiplexer:
LOGIC DIAGRAM FOR 1X8 DEMULTIPLEXER:
TRUTH TABLE
1:8 DEMULTIPLEXER:
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4. PROCEDURE:
1. Connections are given as per in the circuit diagram.
2. Inputs are given through the logic switches.
3. Outputs are noted and verified with truth table
5.
RESULTS
INFERENCE :
Thus the truth table of multiplexer and demultiplexer was studied and
verified using logic gates.
CONCLUSION:
6. VIVA QUESTIONS:
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What is a multiplexer?
What are the applications of multiplexer?
What is the difference between multiplexer & demultiplexer?
In 2n: 1 multiplexer how many selection lines are used?
Draw a 2 to 1 multiplexer circuit
Draw a 1 to 2 demultiplexer circuit.
EXPERIMENT:
DATE:
1. OBJECTIVE:
To construct and verify the 8 X 3 Encoder using logic gates.
2. REQUIREMENTS:
S. No
Components /
Equipments
Specificati
on
Quantity
1.
2.
OR Gate
IC7432
3.
Connecting Wires
Sufficient Numbers
3. THEORY:
Digital Computers, Microprocessors and other digital systems are
binary operated whereas our language of communication is in decimal
numbers and alphabetical characters only. Therefore, the need arises for
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Encoder
Lgic Diagram:
Truth Table:
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Outputs:
4. PROCEDURE:
1. Construct the circuit as per the diagram
2. Switch on the power supply.
3. Apply the necessary input and observe the outputs to verify the truth
table.
5.
RESULTS:
INFERENCE:
Thus an 8 x 3 encoder is constructed and verified.
CONCLUSION:
6. REVIEW QUESTIONS:
1. Draw the basic block diagram of a practical decoder.
2. What is the need for decoder?
3. Name the procedure involved in decoding.
4. Give some practical applications where decoding is necessary.
5. List the advantages of decoding.
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Specification
1.
AND,OR Gate
IC7408,IC7432
2.
IC Trainer Kit
---
3.
Connecting Wires
---
Required
numbers
S. No.
Quantity
Truth Table:
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Circuit Diagram:
3. PROCEDURE:
1.
2.
3.
4.
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6.
REVIEW QUESTIONS:
1. Draw the basic block diagram of a practical decoder.
2. What is the need for decoder?
3. Name the procedure involved in decoding.
4. Give some practical applications where decoding is necessary.
5. List the advantages of decoding.
Quantity
1.
Components /
Equipments
Digital IC trainer kit
----
2.
IC 7473,7408
2,1
3.
Connecting wires
----
Sufficient Nos
S. No.
3. THEORY:
Synchronous Counter
Clock input is applied simultaneously to all flip-flops. The output of the first
FLIP-FLOP is connected to the input of second FLIP-FLOP and so on.
Design of synchronous counter
Step 1: Find the number of flip-flops required. For an n-bit counter, nflip-flops is
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CIRCUIT DIAGRAM:
Design of 3-bit synchronous up:
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Pin Diagram
Truth Table:
3 Bit Synchronous
UP Counter
3 Bit Synchronous
DOWN Counter
Clock
Q2
Q1
Q0
Cloc
k
Q2
Q1
Q0
4. PROCEDURE:
1. The connections are made as per the circuit diagram.
2. Switch on the power supply.
3. The input is given at the appropriate terminal and corresponding
output is observed and truth table is verified.
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5. RESULTS:
INFERENCE:
Thus the counters were constructed and their truth tables verified.
CONCLUSION:
6. REVIEW QUESTIONS
1. Name any four flip-flop used to construct the counter.
2. Draw the basic block diagram of a practical 4-bit counter.
3. What is MOD 5 counter?
4. What is the need for counters?
5. Give some practical applications of counters.
IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO SHIFT REGISTERS
EXPERIMENT:
DATE:
1. OBJECTIVE:
To implement the 4 bit shift register using flip flops and to study the
operations in the following modes.
(i)
(ii)
(iii)
(iv)
2. REQUIREMENTS:
S.No
.
D Flip Flop
Connecting wires
Range
Quantity
1
IC 7474
2
some
3. THEORY:
SHIFT REGISTER:
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Serial-input, Serial-output
Parallel-input, Serial-output
Serial-input, parallel-output
Parallel-output, parallel-output
The serial input is a single line going to the input of the leftmost flip-flop of
the register. The serial output is a single line from the output of the rightmost
flip-flop of the register, so that the bits stored in the register can come out
through this line one at a time.
The parallel output consists of N lines, one for each of the flip-flops in the
register, so the information stored in the register can be inspected through these
lines all at once.
PIN DIAGRAM:
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4. PROCEDURE:
1.
circuit.
2.
set inputs.
3.
4.
5.
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