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3 Description
2 Applications
HVAC Gateways
Residential Ductless Air Conditioning Outdoor
Units
Robotic Controls
Industrial Stepper Motors
Power Meter and Power Analyzers
Digital Input Modules for Factory Automation
SN7414,
SN74LS14
SN5414,
SN54LS14
PACKAGE
SOIC (14)
4.90 mm 3.91 mm
SSOP (14)
6.20 mm 5.30 mm
PDIP (14)
19.30 mm 6.35 mm
SO (14)
10.30 mm 5.30 mm
CDIP (14)
19.56 mm 6.67 mm
CFP (14)
9.21 mm 5.97 mm
LCCC (20)
8.89 mm 8.89 mm
Y
Copyright 2016, Texas Instruments Incorporated
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
18
18
18
18
18
18
4 Revision History
Changes from Revision B (February 2002) to Revision C
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Deleted Ordering Information table; see the Package Option Addendum at the end of the data sheet ............................... 1
Changed Package thermal impedance, RJA, values in Thermal Information table From: 86C/W To: 90.1C/W (D),
From: 96C/W To: 105.4C/W (DB), From: 80C/W To: 54.9C/W (N), and From: 76C/W To: 88.8C/W (NS)................... 4
10
5Y
4A
GND
4Y
2A
18
6Y
NC
17
NC
2Y
16
5A
NC
15
NC
3A
14
5Y
3Y
6A
3A
19
5A
Not to scale
13
11
NC
VCC
2Y
6Y
20
6A
12
12
13
11
2A
1A
1Y
VCC
10
14
1Y
1A
FK Package
20-Pin LCCC
Top View
4A
4Y
NC
GND
3Y
Not to scale
NC No internal connection
Pin Functions
PIN
I/O
DESCRIPTION
LCCC
1A
Channel 1 input
1Y
Channel 1 output
2A
Channel 2 input
2Y
Channel 2 output
3A
Channel 3 input
3Y
Channel 3 output
4A
13
Channel 4 input
4Y
12
Channel 4 output
5A
11
16
Channel 5 input
5Y
10
14
Channel 5 output
6A
13
19
Channel 6 input
6Y
12
18
Channel 6 output
GND
10
Ground
NC
1, 5, 7,
11, 15, 17
No internal connection
VCC
14
20
Power supply
NAME
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Input voltage
5.5
SNx4LS14
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
7
65
150
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to network ground terminal.
Electrostatic
discharge
1500
2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
VCC
Supply voltage
IOH
IOL
MIN
NOM
MAX
SN5414, SN54LS14
4.5
5.5
SN7414, SN74LS14
4.75
5.25
SN5414, SN7414
0.8
SN54LS14, SN74LS14
0.4
SN5414, SN7414
TA
UNIT
V
mA
16
SN54LS14
SN74LS14
SN5414, SN54LS14
55
125
SN7414, SN74LS14
70
mA
D (SOIC)
DB (SSOP)
N (PDIP)
NS (SO)
UNIT
14 PINS
14 PINS
14 PINS
14 PINS
90.1
105.4
54.9
88.8
C/W
50.3
57.3
42.5
46.5
C/W
RJB
44.3
52.7
34.7
47.5
C/W
JT
17.9
22.5
27.8
16.8
C/W
JB
44.1
52.2
34.6
47.2
C/W
RJA
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package termal impedance is calculated in accordance with JESD 51-7.
PARAMETER
VT+
VCC = 5 V
VT
VCC = 5 V
Hysteresis
(VT+ VT)
VCC = 5 V
VIK
VOH
MIN
TYP (2)
SNx414
1.5
1.7
SNx4LS14
1.4
1.6
1.9
SNx414
0.6
0.9
1.1
SNx4LS14
0.5
0.8
0.4
0.8
1.5
1.5
2.4
3.4
2.4
3.4
IT+
VCC = 5 V, VI = VT+
IT
VCC = 5 V, VI = VT
0.25
0.4
0.35
0.5
SNx4LS14
0.14
SNx414
0.56
SNx4LS14
0.18
IIH
1
0.1
40
20
IOS (3)
VCC = MAX
ICCH
VCC = MAX
ICCL
VCC = MAX
SNx414
mA
IIL
mA
II
(1)
(2)
(3)
0.4
0.43
0.2
SNx414
UNIT
MAX
0.8
1.2
SNx4LS14
0.4
SNx414
18
55
SNx4LS14
20
100
SNx414
22
36
SNx4LS14
8.6
16
SNx414
39
60
SNx4LS14
12
21
mA
A
mA
mA
mA
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V and TA = 25C.
Not more than one output should be shorted at a time.
FROM (INPUT)
TO (OUTPUT)
TEST CONDITIONS
MIN
tPLH
tPHL
TYP
MAX
15
22
ns
15
22
ns
UNIT
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VCC = 5 V
1.70
1.69
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
VCC = 5 V
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
1.60
75 50
25
25
50
75
100
125
75 50
25
25
50
75
100
125
TA Free-Air Temperature C
TA Free-Air Temperature C
850
VCC = 5 V
TA = 25C
VCC = 5 V
840
V T+ V T Hysteresis mV
830
820
810
800
790
780
770
760
750
75 50
25
25
50
75
100
740
125
760
820
840
860
880
900
2.0
TA = 25C
1.6
Positive-Going Threshold Voltage, VT+
1.4
TA = 25C
1.8
V T+ VT Hysteresis V
1.8
Threshold Voltage - V
800
2.0
1.2
1.0
0.8
Negative-Going Threshold Voltage, VT
0.6
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.4
0.2
0.2
0
0
4.5
5
5.25
4.75
VT+ VT Hysteresis mV
5.5
780
VT+ VT Hysteresis mV
TA Free-Air Temperature C
4.5
5
5.25
4.75
VCC Supply Voltage V
5.5
VO Output Voltage V
VCC = 5 V
TA = 25C
VT
VT+
0
0
0.4
0.8
1.2
1.6
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1.69
1.70
1.68
1.67
1.66
1.65
1.64
1.63
1.62
1.61
VCC = 5 V
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.80
1.60
75 50
25
25
50
75
100
75 50
125
TA Free-Air Temperature C
0
25
50
75
100
25
TA Free-Air Temperature C
125
850
V T+ VT Hysteresis V
VCC = 5 V
TA = 25C
VCC = 5 V
840
830
820
810
800
790
780
770
99% ARE
ABOVE
735 mV
760
750
75 50
25
25
50
75
100
720
125
TA Free-Air Temperature C
740
760
780
800
820
840
860
880
VT+ VT Hysteresis mV
2.0
VCC = 5 V
TA = 25C
TA = 25C
1.8
VT
VT+
1.4
VO Output Voltage V
Threshold Voltage V
1.6
1.2
Negative-Going Threshold Voltage, VT
1.0
0.8
Hysteresis, VT+ VT
0.6
1
0.4
0.2
0
0
4.5
4.75
5.25
5.5
0.8
0.4
1.2
1.6
VI Input Voltage V
VCC
VCC
RL
RL
From Output
Under Test
CL
From Output
Under Test
Test
Point
CL
Test
Point
RL
1.5 V
1.5 V
S1
tw
From Output
Under Test
Low-Level
Pulse
CL
1 k
1.5 V
1.5 V
S2
3V
Timing
Input
3V
Input
1.5 V
1.5 V
1.5 V
0V
0V
th
tsu
Data
Input
tPLH
3V
1.5 V
1.5 V
tPHL
In-Phase
Output
VOH
1.5 V
0V
1.5 V
VOL
tPHL
tPLH
Out-of-Phase
Output
VOH
1.5 V
1.5 V
VOL
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Output
Control
(low-level
enabling)
1.5 V
1.5 V
0V
tPZL
tPLZ
Waveform 1
1.5 V
1.5 V
VOL
tPZH
VOL + 0.5 V
tPHZ
VOH
Waveform 2
1.5 V
VOH 0.5 V
1.5 V
A.
B.
C.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
D.
S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open
for tPZL.
E.
All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 ; tr and tf 7
ns for Series SN5414 and SN7414 devices and tr and tf 2.5 ns for Series SN54S14 and SN74S14 devices.
F.
The outputs are measured one at a time with one input transition per measurement.
Figure 20. Voltage Waveforms Enable and Disable Times, 3-State Outputs
10
VCC
VCC
RL
RL
From Output
Under Test
CL
From Output
Under Test
Test
Point
CL
Test
Point
RL
1.3 V
1.3 V
S1
tw
From Output
Under Test
Low-Level
Pulse
CL
5 k
1.3 V
1.3 V
S2
3V
Timing
Input
3V
Input
1.3 V
1.3 V
1.3 V
0V
0V
th
tsu
Data
Input
tPLH
3V
1.3 V
1.3 V
tPHL
In-Phase
Output
VOH
1.3 V
1.3 V
0V
VOL
tPHL
tPLH
Out-of-Phase
Output
VOH
1.3 V
1.3 V
VOL
11
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3V
1.3 V
1.3 V
0V
tPZL
Waveform 1
tPLZ
1.5 V
1.3 V
VOL
tPZH
VOL + 0.5 V
tPHZ
VOH
Waveform 2
1.3 V
VOH 0.5 V
1.5 V
A.
B.
C.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
D.
S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open
for tPZL.
E.
Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F.
All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 50 , tr 1.5 ns,
tf 2.6 ns.
G.
The outputs are measured one at a time with one input transition per measurement.
Figure 27. Voltage Waveforms Enable and Disable Times, 3-State Outputs
12
8 Detailed Description
8.1 Overview
The SNx414 and SNx4LS14 Schmitt-Trigger devices contain six independent inverters. They perform the
Boolean function Y = A in positive logic.
Schmitt-Trigger inputs are designed to provide a minimum separation between positive and negative switching
thresholds. This allows for noisy or slow inputs that would cause problems such as oscillation or excessive
current draw with normal CMOS inputs.
Y
Copyright 2016, Texas Instruments Incorporated
INPUT A
OUTPUT Y
13
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14
VCC
Voltage
VT+(max)
VT+
VT+ Typical
VT+(min)
tdelay (max)
t delay (min)
VT
(max)
|W
VCC
VT (min)
ln | 1
|W
VCC
ln | 1
VC
VOUT
0.0
t0
t0 + 2
t0 + 22
t0 + 32
t0 + 42
t0 + 52
Time
Figure 29. Ideal Capacitor Voltage and Output Voltage With Positive Switching Threshold
15
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TTL System
VT+
VT
Input
CMOS
Sine-Wave
Oscillator
Output
0.1 Hz to 10 MHz
330
VT+
VT
Input
Input
Output
Open-Collector
Output
Input
Input
A
Output
VT+
Point A
Output
16
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float. In many cases, functions or parts of functions of
digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
three of the four buffer gates are used. Such inputs must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. Floating outputs are generally acceptable, unless the
part is a transceiver.
Input
Unused Input
Output
Output
Unused Input
Input
17
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PRODUCT FOLDER
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN5414
Click here
Click here
Click here
Click here
Click here
SN54LS14
Click here
Click here
Click here
Click here
Click here
SN7414
Click here
Click here
Click here
Click here
Click here
SN74LS14
Click here
Click here
Click here
Click here
Click here
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
18
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
5962-9665801Q2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
59629665801Q2A
SNJ54LS
14FK
5962-9665801QCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-9665801QC
A
SNJ54LS14J
5962-9665801QDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
5962-9665801QD
A
SNJ54LS14W
5962-9665801VDA
ACTIVE
CFP
14
TBD
A42
-55 to 125
5962-9665801VD
A
SNV54LS14W
JM38510/31302BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
31302BCA
M38510/31302BCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
JM38510/
31302BCA
SN5414J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SN5414J
SN54LS14J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SN54LS14J
SN7414D
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7414
SN7414DG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7414
SN7414DR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7414
SN7414N
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN7414N
SN7414N3
OBSOLETE
PDIP
14
TBD
Call TI
Call TI
0 to 70
SN7414NE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN7414N
SN7414NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
SN7414
SN74LS14D
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
Addendum-Page 1
Samples
www.ti.com
25-Oct-2016
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
SN74LS14DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DBRG4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DE4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DRE4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14DRG4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS14
SN74LS14N
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74LS14N
SN74LS14N3
OBSOLETE
PDIP
14
TBD
Call TI
Call TI
0 to 70
SN74LS14NE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74LS14N
SN74LS14NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS14
SNJ5414J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SNJ5414J
SNJ5414W
ACTIVE
CFP
14
TBD
A42
-55 to 125
SNJ5414W
SNJ54LS14FK
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
59629665801Q2A
SNJ54LS
14FK
SNJ54LS14J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-9665801QC
A
SNJ54LS14J
SNJ54LS14W
ACTIVE
CFP
14
TBD
A42
-55 to 125
5962-9665801QD
A
SNJ54LS14W
(1)
Samples
www.ti.com
25-Oct-2016
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN5414, SN54LS14, SN54LS14-SP, SN7414, SN74LS14 :
Addendum-Page 3
www.ti.com
25-Oct-2016
Addendum-Page 4
22-Mar-2016
Device
SN7414DR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN7414NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LS14DBR
SSOP
DB
14
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
SN74LS14DR
SOIC
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LS14NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
22-Mar-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN7414DR
SOIC
14
2500
367.0
367.0
38.0
SN7414NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74LS14DBR
SSOP
DB
14
2000
367.0
367.0
38.0
SN74LS14DR
SOIC
14
2500
367.0
367.0
38.0
SN74LS14NSR
SO
NS
14
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
08
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
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